1/* 2 * sun50i H616 DDR3-1333 timings, as programmed by Allwinner's boot0 3 * 4 * The chips are probably able to be driven by a faster clock, but boot0 5 * uses a more conservative timing (as usual). 6 * 7 * (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net> 8 * Based on H6 DDR3 timings: 9 * (C) Copyright 2018,2019 Arm Ltd. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14#include <common.h> 15#include <asm/arch/dram.h> 16#include <asm/arch/cpu.h> 17 18void mctl_set_timing_params(const struct dram_para *para) 19{ 20 struct sunxi_mctl_ctl_reg * const mctl_ctl = 21 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; 22 23 u8 tccd = 2; /* JEDEC: 4nCK */ 24 u8 tfaw = ns_to_t(50); /* JEDEC: 30 ns w/ 1K pages */ 25 u8 trrd = max(ns_to_t(6), 4); /* JEDEC: max(6 ns, 4nCK) */ 26 u8 trcd = ns_to_t(15); /* JEDEC: 13.5 ns */ 27 u8 trc = ns_to_t(53); /* JEDEC: 49.5 ns */ 28 u8 txp = max(ns_to_t(6), 3); /* JEDEC: max(6 ns, 3nCK) */ 29 u8 trtp = max(ns_to_t(8), 2); /* JEDEC: max(7.5 ns, 4nCK) */ 30 u8 trp = ns_to_t(15); /* JEDEC: >= 13.75 ns */ 31 u8 tras = ns_to_t(38); /* JEDEC >= 36 ns, <= 9*trefi */ 32 u16 trefi = ns_to_t(7800) / 32; /* JEDEC: 7.8us@Tcase <= 85C */ 33 u16 trfc = ns_to_t(350); /* JEDEC: 160 ns for 2Gb */ 34 u16 txsr = 4; /* ? */ 35 36 u8 tmrw = 0; /* ? */ 37 u8 tmrd = 4; /* JEDEC: 4nCK */ 38 u8 tmod = max(ns_to_t(15), 12); /* JEDEC: max(15 ns, 12nCK) */ 39 u8 tcke = max(ns_to_t(6), 3); /* JEDEC: max(5.625 ns, 3nCK) */ 40 u8 tcksrx = max(ns_to_t(10), 4); /* JEDEC: max(10 ns, 5nCK) */ 41 u8 tcksre = max(ns_to_t(10), 4); /* JEDEC: max(10 ns, 5nCK) */ 42 u8 tckesr = tcke + 1; /* JEDEC: tCKE(min) + 1nCK */ 43 u8 trasmax = (para->clk / 2) / 15; /* JEDEC: tREFI * 9 */ 44 u8 txs = ns_to_t(360) / 32; /* JEDEC: max(5nCK,tRFC+10ns) */ 45 u8 txsdll = 16; /* JEDEC: 512 nCK */ 46 u8 txsabort = 4; /* ? */ 47 u8 txsfast = 4; /* ? */ 48 u8 tcl = 7; /* JEDEC: CL / 2 => 6 */ 49 u8 tcwl = 5; /* JEDEC: 8 */ 50 u8 t_rdata_en = 9; /* ? */ 51 u8 t_wr_lat = 5; /* ? */ 52 53 u8 twtp; /* (WL + BL / 2 + tWR) / 2 */ 54 u8 twr2rd; /* (WL + BL / 2 + tWTR) / 2 */ 55 u8 trd2wr; /* (RL + BL / 2 + 2 - WL) / 2 */ 56 57 if (para->tpr2 & 0x100) { 58 tcl = 5; 59 tcwl = 4; 60 t_rdata_en = 5; 61 t_wr_lat = 3; 62 } 63 64 twtp = tcl + 2 + tcwl; 65 twr2rd = trtp + 2 + tcwl; 66 trd2wr = tcl + 3 - tcwl; 67 68 /* set DRAM timing */ 69 writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, 70 &mctl_ctl->dramtmg[0]); 71 writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]); 72 writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, 73 &mctl_ctl->dramtmg[2]); 74 writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]); 75 writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, 76 &mctl_ctl->dramtmg[4]); 77 writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke, 78 &mctl_ctl->dramtmg[5]); 79 /* Value suggested by ZynqMP manual and used by libdram */ 80 writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]); 81 writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs, 82 &mctl_ctl->dramtmg[8]); 83 writel(0x00020208, &mctl_ctl->dramtmg[9]); 84 writel(0xE0C05, &mctl_ctl->dramtmg[10]); 85 writel(0x440C021C, &mctl_ctl->dramtmg[11]); 86 writel(8, &mctl_ctl->dramtmg[12]); 87 writel(0xA100002, &mctl_ctl->dramtmg[13]); 88 writel(txsr, &mctl_ctl->dramtmg[14]); 89 90 clrbits_le32(&mctl_ctl->init[0], 3 << 30); 91 writel(0x420000, &mctl_ctl->init[1]); 92 writel(5, &mctl_ctl->init[2]); 93 writel(0x1f140004, &mctl_ctl->init[3]); 94 writel(0x00200000, &mctl_ctl->init[4]); 95 96 writel(0, &mctl_ctl->dfimisc); 97 clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660); 98 99 /* Configure DFI timing */ 100 writel(t_wr_lat | 0x2000000 | (t_rdata_en << 16) | 0x808000, 101 &mctl_ctl->dfitmg0); 102 writel(0x100202, &mctl_ctl->dfitmg1); 103 104 /* set refresh timing */ 105 writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg); 106} 107