1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2015 Marek Vasut <marex@denx.de> 4 */ 5 6#include <common.h> 7#include <asm/arch/clock_manager.h> 8#include <qts/pll_config.h> 9 10#define MAIN_VCO_BASE ( \ 11 (CFG_HPS_MAINPLLGRP_VCO_DENOM << \ 12 CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \ 13 (CFG_HPS_MAINPLLGRP_VCO_NUMER << \ 14 CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \ 15 ) 16 17#define PERI_VCO_BASE ( \ 18 (CFG_HPS_PERPLLGRP_VCO_PSRC << \ 19 CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \ 20 (CFG_HPS_PERPLLGRP_VCO_DENOM << \ 21 CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \ 22 (CFG_HPS_PERPLLGRP_VCO_NUMER << \ 23 CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \ 24 ) 25 26#define SDR_VCO_BASE ( \ 27 (CFG_HPS_SDRPLLGRP_VCO_SSRC << \ 28 CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \ 29 (CFG_HPS_SDRPLLGRP_VCO_DENOM << \ 30 CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \ 31 (CFG_HPS_SDRPLLGRP_VCO_NUMER << \ 32 CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \ 33 ) 34 35static const struct cm_config cm_default_cfg = { 36 /* main group */ 37 MAIN_VCO_BASE, 38 (CFG_HPS_MAINPLLGRP_MPUCLK_CNT << 39 CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET), 40 (CFG_HPS_MAINPLLGRP_MAINCLK_CNT << 41 CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET), 42 (CFG_HPS_MAINPLLGRP_DBGATCLK_CNT << 43 CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET), 44 (CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT << 45 CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET), 46 (CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT << 47 CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET), 48 (CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT << 49 CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET), 50 (CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK << 51 CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) | 52 (CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK << 53 CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) | 54 (CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK << 55 CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) | 56 (CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK << 57 CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET), 58 (CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK << 59 CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) | 60 (CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK << 61 CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET), 62 (CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK << 63 CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET), 64 (CFG_HPS_MAINPLLGRP_L4SRC_L4MP << 65 CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) | 66 (CFG_HPS_MAINPLLGRP_L4SRC_L4SP << 67 CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET), 68 69 /* peripheral group */ 70 PERI_VCO_BASE, 71 (CFG_HPS_PERPLLGRP_EMAC0CLK_CNT << 72 CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET), 73 (CFG_HPS_PERPLLGRP_EMAC1CLK_CNT << 74 CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET), 75 (CFG_HPS_PERPLLGRP_PERQSPICLK_CNT << 76 CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET), 77 (CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT << 78 CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET), 79 (CFG_HPS_PERPLLGRP_PERBASECLK_CNT << 80 CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET), 81 (CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT << 82 CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET), 83 (CFG_HPS_PERPLLGRP_DIV_USBCLK << 84 CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) | 85 (CFG_HPS_PERPLLGRP_DIV_SPIMCLK << 86 CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) | 87 (CFG_HPS_PERPLLGRP_DIV_CAN0CLK << 88 CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) | 89 (CFG_HPS_PERPLLGRP_DIV_CAN1CLK << 90 CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET), 91 (CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK << 92 CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET), 93 (CFG_HPS_PERPLLGRP_SRC_QSPI << 94 CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) | 95 (CFG_HPS_PERPLLGRP_SRC_NAND << 96 CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) | 97 (CFG_HPS_PERPLLGRP_SRC_SDMMC << 98 CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET), 99 100 /* sdram pll group */ 101 SDR_VCO_BASE, 102 (CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE << 103 CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) | 104 (CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT << 105 CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET), 106 (CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE << 107 CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) | 108 (CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT << 109 CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET), 110 (CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE << 111 CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) | 112 (CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT << 113 CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET), 114 (CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE << 115 CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) | 116 (CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT << 117 CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET), 118 119 /* altera group */ 120 CFG_HPS_ALTERAGRP_MPUCLK, 121}; 122 123const struct cm_config * const cm_get_default_config(void) 124{ 125 return &cm_default_cfg; 126} 127 128const unsigned int cm_get_osc_clk_hz(const int osc) 129{ 130 if (osc == 1) 131 return CFG_HPS_CLK_OSC1_HZ; 132 else if (osc == 2) 133 return CFG_HPS_CLK_OSC2_HZ; 134 else 135 return 0; 136} 137 138const unsigned int cm_get_f2s_per_ref_clk_hz(void) 139{ 140 return CFG_HPS_CLK_F2S_PER_REF_HZ; 141} 142 143const unsigned int cm_get_f2s_sdr_ref_clk_hz(void) 144{ 145 return CFG_HPS_CLK_F2S_SDR_REF_HZ; 146} 147