1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
4 *
5 */
6
7#include <altera.h>
8#include <common.h>
9#include <asm/arch/mailbox_s10.h>
10#include <asm/arch/misc.h>
11#include <asm/arch/reset_manager.h>
12#include <asm/arch/system_manager.h>
13#include <asm/io.h>
14#include <asm/global_data.h>
15#include <env.h>
16#include <errno.h>
17#include <init.h>
18#include <log.h>
19#include <mach/clock_manager.h>
20
21DECLARE_GLOBAL_DATA_PTR;
22
23/*
24 * FPGA programming support for SoC FPGA Stratix 10
25 */
26static Altera_desc altera_fpga[] = {
27	{
28		/* Family */
29		Intel_FPGA_SDM_Mailbox,
30		/* Interface type */
31		secure_device_manager_mailbox,
32		/* No limitation as additional data will be ignored */
33		-1,
34		/* No device function table */
35		NULL,
36		/* Base interface address specified in driver */
37		NULL,
38		/* No cookie implementation */
39		0
40	},
41};
42
43
44/*
45 * Print CPU information
46 */
47#if defined(CONFIG_DISPLAY_CPUINFO)
48int print_cpuinfo(void)
49{
50	puts("CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
51
52	return 0;
53}
54#endif
55
56#ifdef CONFIG_ARCH_MISC_INIT
57int arch_misc_init(void)
58{
59	char qspi_string[13];
60
61	sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
62	env_set("qspi_clock", qspi_string);
63
64	return 0;
65}
66#endif
67
68int arch_early_init_r(void)
69{
70	socfpga_fpga_add(&altera_fpga[0]);
71
72	return 0;
73}
74
75/* Return 1 if FPGA is ready otherwise return 0 */
76int is_fpga_config_ready(void)
77{
78	return (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGA_CONFIG) &
79		SYSMGR_FPGACONFIG_READY_MASK) == SYSMGR_FPGACONFIG_READY_MASK;
80}
81
82void do_bridge_reset(int enable, unsigned int mask)
83{
84	/* Check FPGA status before bridge enable */
85	if (!is_fpga_config_ready()) {
86		puts("FPGA not ready. Bridge reset aborted!\n");
87		return;
88	}
89
90	socfpga_bridges_reset(enable);
91}
92