1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd 4 * Copyright (c) 2016 Andreas F��rber 5 */ 6 7#include <common.h> 8#include <init.h> 9#include <syscon.h> 10#include <asm/armv8/mmu.h> 11#include <asm/arch-rockchip/bootrom.h> 12#include <asm/arch-rockchip/clock.h> 13#include <asm/arch-rockchip/cru_rk3368.h> 14#include <asm/arch-rockchip/grf_rk3368.h> 15#include <asm/arch-rockchip/hardware.h> 16#include <linux/bitops.h> 17#include <linux/delay.h> 18 19#define IMEM_BASE 0xFF8C0000 20 21/* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 4K) */ 22#define MCU_SRAM_BASE (IMEM_BASE + 1024 * 4) 23#define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28) 24#define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12) 25/* exsram may using by mcu to accessing dram(0x0-0x20000000) */ 26#define MCU_EXSRAM_BASE (0) 27#define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28) 28#define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12) 29/* experi no used, reserved value = 0 */ 30#define MCU_EXPERI_BASE (0) 31#define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28) 32#define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12) 33 34static struct mm_region rk3368_mem_map[] = { 35 { 36 .virt = 0x0UL, 37 .phys = 0x0UL, 38 .size = 0x80000000UL, 39 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 40 PTE_BLOCK_INNER_SHARE 41 }, { 42 .virt = 0xf0000000UL, 43 .phys = 0xf0000000UL, 44 .size = 0x10000000UL, 45 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 46 PTE_BLOCK_NON_SHARE | 47 PTE_BLOCK_PXN | PTE_BLOCK_UXN 48 }, { 49 /* List terminator */ 50 0, 51 } 52}; 53 54struct mm_region *mem_map = rk3368_mem_map; 55 56const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { 57 [BROM_BOOTSOURCE_EMMC] = "/mmc@ff0f0000", 58 [BROM_BOOTSOURCE_SPINOR] = "/spi@ff120000/flash@0", 59 [BROM_BOOTSOURCE_SD] = "/mmc@ff0c0000", 60}; 61 62#ifdef CONFIG_ARCH_EARLY_INIT_R 63static int mcu_init(void) 64{ 65 struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 66 struct rk3368_cru *cru = rockchip_get_cru(); 67 68 rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK, 69 MCU_SRAM_BASE_BIT31_BIT28 << MCU_SRAM_BASE_BIT31_BIT28_SHIFT); 70 rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK, 71 MCU_SRAM_BASE_BIT27_BIT12 << MCU_SRAM_BASE_BIT27_BIT12_SHIFT); 72 rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK, 73 MCU_EXSRAM_BASE_BIT31_BIT28 << MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT); 74 rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK, 75 MCU_EXSRAM_BASE_BIT27_BIT12 << MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT); 76 rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK, 77 MCU_EXPERI_BASE_BIT31_BIT28 << MCU_EXPERI_BASE_BIT31_BIT28_SHIFT); 78 rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK, 79 MCU_EXPERI_BASE_BIT27_BIT12 << MCU_EXPERI_BASE_BIT27_BIT12_SHIFT); 80 81 rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK, 82 (MCU_PLL_SEL_GPLL << MCU_PLL_SEL_SHIFT) | 83 (5 << MCU_CLK_DIV_SHIFT)); 84 85 /* mcu dereset, for start running */ 86 rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK); 87 88 return 0; 89} 90 91int arch_early_init_r(void) 92{ 93 return mcu_init(); 94} 95#endif 96 97#ifdef CONFIG_SPL_BUILD 98/* 99 * The SPL (and also the full U-Boot stage on the RK3368) will run in 100 * secure mode (i.e. EL3) and an ATF will eventually be booted before 101 * starting up the operating system... so we can initialize the SGRF 102 * here and rely on the ATF installing the final (secure) policy 103 * later. 104 */ 105static inline uintptr_t sgrf_soc_con_addr(unsigned int no) 106{ 107 const uintptr_t SGRF_BASE = 108 (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); 109 110 return SGRF_BASE + sizeof(u32) * no; 111} 112 113static inline uintptr_t sgrf_busdmac_addr(unsigned int no) 114{ 115 const uintptr_t SGRF_BASE = 116 (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); 117 const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100; 118 const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET; 119 120 return SGRF_BUSDMAC_BASE + sizeof(u32) * no; 121} 122 123static void sgrf_init(void) 124{ 125 struct rk3368_cru * const cru = 126 (struct rk3368_cru * const)rockchip_get_cru(); 127 const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0); 128 const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2); 129 const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12); 130 131 /* Set all configurable IP to 'non secure'-mode */ 132 rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC); 133 rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC); 134 rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC); 135 136 /* 137 * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c 138 * Original comment: "ddr space set no secure mode" 139 */ 140 rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC); 141 rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC); 142 rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC); 143 144 /* Set 'secure dma' to 'non secure'-mode */ 145 rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC); 146 rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC); 147 148 dsb(); /* barrier */ 149 150 rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ); 151 rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ); 152 153 dsb(); /* barrier */ 154 udelay(10); 155 156 rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ); 157 rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ); 158} 159 160int arch_cpu_init(void) 161{ 162 /* Reset security, so we can use DMA in the MMC drivers */ 163 sgrf_init(); 164 165 return 0; 166} 167#endif 168 169#ifdef CONFIG_DEBUG_UART_BOARD_INIT 170void board_debug_uart_init(void) 171{ 172 /* 173 * N.B.: This is called before the device-model has been 174 * initialised. For this reason, we can not access 175 * the GRF address range using the syscon API. 176 */ 177#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) 178 struct rk3368_grf * const grf = 179 (struct rk3368_grf * const)0xff770000; 180 181 enum { 182 GPIO2D1_MASK = GENMASK(3, 2), 183 GPIO2D1_GPIO = 0, 184 GPIO2D1_UART0_SOUT = (1 << 2), 185 186 GPIO2D0_MASK = GENMASK(1, 0), 187 GPIO2D0_GPIO = 0, 188 GPIO2D0_UART0_SIN = (1 << 0), 189 }; 190 191 /* Enable early UART0 on the RK3368 */ 192 rk_clrsetreg(&grf->gpio2d_iomux, 193 GPIO2D0_MASK, GPIO2D0_UART0_SIN); 194 rk_clrsetreg(&grf->gpio2d_iomux, 195 GPIO2D1_MASK, GPIO2D1_UART0_SOUT); 196#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1c0000) 197 struct rk3368_pmu_grf * const pmugrf __maybe_unused = 198 (struct rk3368_pmu_grf * const)0xff738000; 199 200 enum { 201 /* UART4 */ 202 GPIO0D2_MASK = GENMASK(5, 4), 203 GPIO0D2_GPIO = 0, 204 GPIO0D2_UART4_SOUT = (3 << 4), 205 206 GPIO0D3_MASK = GENMASK(7, 6), 207 GPIO0D3_GPIO = 0, 208 GPIO0D3_UART4_SIN = (3 << 6), 209 }; 210 211 /* Enable early UART4 on the PX5 */ 212 rk_clrsetreg(&pmugrf->gpio0d_iomux, 213 GPIO0D2_MASK | GPIO0D3_MASK, 214 GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN); 215#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000) 216 struct rk3368_grf * const grf = 217 (struct rk3368_grf * const)0xff770000; 218 219 enum { 220 GPIO2A6_SHIFT = 12, 221 GPIO2A6_MASK = GENMASK(13, 12), 222 GPIO2A6_GPIO = 0, 223 GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT), 224 225 GPIO2A5_SHIFT = 10, 226 GPIO2A5_MASK = GENMASK(11, 10), 227 GPIO2A5_GPIO = 0, 228 GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT), 229 }; 230 231 /* Enable early UART2 on the RK3368 */ 232 rk_clrsetreg(&grf->gpio2a_iomux, 233 GPIO2A6_MASK, GPIO2A6_UART2_SIN); 234 rk_clrsetreg(&grf->gpio2a_iomux, 235 GPIO2A5_MASK, GPIO2A5_UART2_SOUT); 236#endif 237} 238#endif 239