1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017 Rockchip Electronics Co., Ltd
4 */
5#include <common.h>
6#include <clk.h>
7#include <dm.h>
8#include <fdt_support.h>
9#include <init.h>
10#include <spl.h>
11#include <asm/armv8/mmu.h>
12#include <asm/arch-rockchip/bootrom.h>
13#include <asm/arch-rockchip/grf_px30.h>
14#include <asm/arch-rockchip/hardware.h>
15#include <asm/arch-rockchip/uart.h>
16#include <asm/arch-rockchip/clock.h>
17#include <asm/arch-rockchip/cru_px30.h>
18#include <dt-bindings/clock/px30-cru.h>
19
20const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
21	[BROM_BOOTSOURCE_EMMC] = "/mmc@ff390000",
22	[BROM_BOOTSOURCE_SPINOR] = "/spi@ff3a0000/flash@0",
23	[BROM_BOOTSOURCE_SD] = "/mmc@ff370000",
24};
25
26static struct mm_region px30_mem_map[] = {
27	{
28		.virt = 0x0UL,
29		.phys = 0x0UL,
30		.size = 0xff000000UL,
31		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
32			 PTE_BLOCK_INNER_SHARE
33	}, {
34		.virt = 0xff000000UL,
35		.phys = 0xff000000UL,
36		.size = 0x01000000UL,
37		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
38			 PTE_BLOCK_NON_SHARE |
39			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
40	}, {
41		/* List terminator */
42		0,
43	}
44};
45
46struct mm_region *mem_map = px30_mem_map;
47
48#define PMU_PWRDN_CON			0xff000018
49#define PMUGRF_BASE			0xff010000
50#define GRF_BASE			0xff140000
51#define CRU_BASE			0xff2b0000
52#define PMUCRU_BASE			0xff2bc000
53#define VIDEO_PHY_BASE			0xff2e0000
54#define SERVICE_CORE_ADDR		0xff508000
55#define DDR_FW_BASE			0xff534000
56
57#define FW_DDR_CON			0x40
58
59#define QOS_PRIORITY			0x08
60
61#define QOS_PRIORITY_LEVEL(h, l)	((((h) & 3) << 8) | ((l) & 3))
62
63/* GRF_GPIO1AL_IOMUX */
64enum {
65	GPIO1A3_SHIFT		= 12,
66	GPIO1A3_MASK		= 0xf << GPIO1A3_SHIFT,
67	GPIO1A3_GPIO		= 0,
68	GPIO1A3_FLASH_D3,
69	GPIO1A3_EMMC_D3,
70	GPIO1A3_SFC_SIO3,
71
72	GPIO1A2_SHIFT		= 8,
73	GPIO1A2_MASK		= 0xf << GPIO1A2_SHIFT,
74	GPIO1A2_GPIO		= 0,
75	GPIO1A2_FLASH_D2,
76	GPIO1A2_EMMC_D2,
77	GPIO1A2_SFC_SIO2,
78
79	GPIO1A1_SHIFT		= 4,
80	GPIO1A1_MASK		= 0xf << GPIO1A1_SHIFT,
81	GPIO1A1_GPIO		= 0,
82	GPIO1A1_FLASH_D1,
83	GPIO1A1_EMMC_D1,
84	GPIO1A1_SFC_SIO1,
85
86	GPIO1A0_SHIFT		= 0,
87	GPIO1A0_MASK		= 0xf << GPIO1A0_SHIFT,
88	GPIO1A0_GPIO		= 0,
89	GPIO1A0_FLASH_D0,
90	GPIO1A0_EMMC_D0,
91	GPIO1A0_SFC_SIO0,
92};
93
94/* GRF_GPIO1AH_IOMUX */
95enum {
96	GPIO1A4_SHIFT		= 0,
97	GPIO1A4_MASK		= 0xf << GPIO1A4_SHIFT,
98	GPIO1A4_GPIO		= 0,
99	GPIO1A4_FLASH_D4,
100	GPIO1A4_EMMC_D4,
101	GPIO1A4_SFC_CSN0,
102};
103
104/* GRF_GPIO1BL_IOMUX */
105enum {
106	GPIO1B1_SHIFT		= 4,
107	GPIO1B1_MASK		= 0xf << GPIO1B1_SHIFT,
108	GPIO1B1_GPIO		= 0,
109	GPIO1B1_FLASH_RDY,
110	GPIO1B1_EMMC_CLKOUT,
111	GPIO1B1_SFC_CLK,
112};
113
114/* GRF_GPIO1BH_IOMUX */
115enum {
116	GPIO1B7_SHIFT		= 12,
117	GPIO1B7_MASK		= 0xf << GPIO1B7_SHIFT,
118	GPIO1B7_GPIO		= 0,
119	GPIO1B7_FLASH_RDN,
120	GPIO1B7_UART3_RXM1,
121	GPIO1B7_SPI0_CLK,
122
123	GPIO1B6_SHIFT		= 8,
124	GPIO1B6_MASK		= 0xf << GPIO1B6_SHIFT,
125	GPIO1B6_GPIO		= 0,
126	GPIO1B6_FLASH_CS1,
127	GPIO1B6_UART3_TXM1,
128	GPIO1B6_SPI0_CSN,
129};
130
131/* GRF_GPIO1CL_IOMUX */
132enum {
133	GPIO1C1_SHIFT		= 4,
134	GPIO1C1_MASK		= 0xf << GPIO1C1_SHIFT,
135	GPIO1C1_GPIO		= 0,
136	GPIO1C1_UART1_TX,
137
138	GPIO1C0_SHIFT		= 0,
139	GPIO1C0_MASK		= 0xf << GPIO1C0_SHIFT,
140	GPIO1C0_GPIO		= 0,
141	GPIO1C0_UART1_RX,
142};
143
144/* GRF_GPIO1DL_IOMUX */
145enum {
146	GPIO1D3_SHIFT		= 12,
147	GPIO1D3_MASK		= 0xf << GPIO1D3_SHIFT,
148	GPIO1D3_GPIO		= 0,
149	GPIO1D3_SDMMC_D1,
150	GPIO1D3_UART2_RXM0,
151
152	GPIO1D2_SHIFT		= 8,
153	GPIO1D2_MASK		= 0xf << GPIO1D2_SHIFT,
154	GPIO1D2_GPIO		= 0,
155	GPIO1D2_SDMMC_D0,
156	GPIO1D2_UART2_TXM0,
157};
158
159/* GRF_GPIO1DH_IOMUX */
160enum {
161	GPIO1D7_SHIFT		= 12,
162	GPIO1D7_MASK		= 0xf << GPIO1D7_SHIFT,
163	GPIO1D7_GPIO		= 0,
164	GPIO1D7_SDMMC_CMD,
165
166	GPIO1D6_SHIFT		= 8,
167	GPIO1D6_MASK		= 0xf << GPIO1D6_SHIFT,
168	GPIO1D6_GPIO		= 0,
169	GPIO1D6_SDMMC_CLK,
170
171	GPIO1D5_SHIFT		= 4,
172	GPIO1D5_MASK		= 0xf << GPIO1D5_SHIFT,
173	GPIO1D5_GPIO		= 0,
174	GPIO1D5_SDMMC_D3,
175
176	GPIO1D4_SHIFT		= 0,
177	GPIO1D4_MASK		= 0xf << GPIO1D4_SHIFT,
178	GPIO1D4_GPIO		= 0,
179	GPIO1D4_SDMMC_D2,
180};
181
182/* GRF_GPIO2BH_IOMUX */
183enum {
184	GPIO2B6_SHIFT		= 8,
185	GPIO2B6_MASK		= 0xf << GPIO2B6_SHIFT,
186	GPIO2B6_GPIO		= 0,
187	GPIO2B6_CIF_D1M0,
188	GPIO2B6_UART2_RXM1,
189
190	GPIO2B4_SHIFT		= 0,
191	GPIO2B4_MASK		= 0xf << GPIO2B4_SHIFT,
192	GPIO2B4_GPIO		= 0,
193	GPIO2B4_CIF_D0M0,
194	GPIO2B4_UART2_TXM1,
195};
196
197/* GRF_GPIO3AL_IOMUX */
198enum {
199	GPIO3A2_SHIFT		= 8,
200	GPIO3A2_MASK		= 0xf << GPIO3A2_SHIFT,
201	GPIO3A2_GPIO		= 0,
202	GPIO3A2_UART5_TX	= 4,
203
204	GPIO3A1_SHIFT		= 4,
205	GPIO3A1_MASK		= 0xf << GPIO3A1_SHIFT,
206	GPIO3A1_GPIO		= 0,
207	GPIO3A1_UART5_RX	= 4,
208};
209
210/* PMUGRF_GPIO0BL_IOMUX */
211enum {
212	GPIO0B3_SHIFT		= 6,
213	GPIO0B3_MASK		= 0x3 << GPIO0B3_SHIFT,
214	GPIO0B3_GPIO		= 0,
215	GPIO0B3_UART0_RX,
216	GPIO0B3_PMU_DEBUG1,
217
218	GPIO0B2_SHIFT		= 4,
219	GPIO0B2_MASK		= 0x3 << GPIO0B2_SHIFT,
220	GPIO0B2_GPIO		= 0,
221	GPIO0B2_UART0_TX,
222	GPIO0B2_PMU_DEBUG0,
223};
224
225/* PMUGRF_GPIO0CL_IOMUX */
226enum {
227	GPIO0C1_SHIFT		= 2,
228	GPIO0C1_MASK		= 0x3 << GPIO0C1_SHIFT,
229	GPIO0C1_GPIO		= 0,
230	GPIO0C1_PWM_3,
231	GPIO0C1_UART3_RXM0,
232	GPIO0C1_PMU_DEBUG4,
233
234	GPIO0C0_SHIFT		= 0,
235	GPIO0C0_MASK		= 0x3 << GPIO0C0_SHIFT,
236	GPIO0C0_GPIO		= 0,
237	GPIO0C0_PWM_1,
238	GPIO0C0_UART3_TXM0,
239	GPIO0C0_PMU_DEBUG3,
240};
241
242int arch_cpu_init(void)
243{
244	static struct px30_grf * const grf = (void *)GRF_BASE;
245	static struct px30_cru * const cru = (void *)CRU_BASE;
246	u32 __maybe_unused val;
247
248#ifdef CONFIG_SPL_BUILD
249	/* We do some SoC one time setting here. */
250	/* Disable the ddr secure region setting to make it non-secure */
251	writel(0x0, DDR_FW_BASE + FW_DDR_CON);
252
253	/* Set cpu qos priority */
254	writel(QOS_PRIORITY_LEVEL(1, 1), SERVICE_CORE_ADDR + QOS_PRIORITY);
255
256#if !defined(CONFIG_DEBUG_UART_BOARD_INIT) || \
257	(CONFIG_DEBUG_UART_BASE != 0xff160000) || \
258	(CONFIG_DEBUG_UART_CHANNEL != 0)
259	/* fix sdmmc pinmux if not using uart2-channel0 as debug uart */
260	rk_clrsetreg(&grf->gpio1dl_iomux,
261		     GPIO1D3_MASK | GPIO1D2_MASK,
262		     GPIO1D3_SDMMC_D1 << GPIO1D3_SHIFT |
263		     GPIO1D2_SDMMC_D0 << GPIO1D2_SHIFT);
264	rk_clrsetreg(&grf->gpio1dh_iomux,
265		     GPIO1D7_MASK | GPIO1D6_MASK | GPIO1D5_MASK | GPIO1D4_MASK,
266		     GPIO1D7_SDMMC_CMD << GPIO1D7_SHIFT |
267		     GPIO1D6_SDMMC_CLK << GPIO1D6_SHIFT |
268		     GPIO1D5_SDMMC_D3 << GPIO1D5_SHIFT |
269		     GPIO1D4_SDMMC_D2 << GPIO1D4_SHIFT);
270#endif
271
272#ifdef CONFIG_ROCKCHIP_SFC
273	rk_clrsetreg(&grf->gpio1al_iomux,
274		     GPIO1A3_MASK | GPIO1A2_MASK | GPIO1A1_MASK | GPIO1A0_MASK,
275		     GPIO1A3_SFC_SIO3 << GPIO1A3_SHIFT |
276		     GPIO1A2_SFC_SIO2 << GPIO1A2_SHIFT |
277		     GPIO1A1_SFC_SIO1 << GPIO1A1_SHIFT |
278		     GPIO1A0_SFC_SIO0 << GPIO1A0_SHIFT);
279	rk_clrsetreg(&grf->gpio1ah_iomux, GPIO1A4_MASK,
280		     GPIO1A4_SFC_CSN0 << GPIO1A4_SHIFT);
281	rk_clrsetreg(&grf->gpio1bl_iomux, GPIO1B1_MASK,
282		     GPIO1B1_SFC_CLK << GPIO1B1_SHIFT);
283#endif
284
285#endif
286
287	/* Enable PD_VO (default disable at reset) */
288	rk_clrreg(PMU_PWRDN_CON, 1 << 13);
289
290	/* Disable video phy bandgap by default */
291	writel(0x82, VIDEO_PHY_BASE + 0x0000);
292	writel(0x05, VIDEO_PHY_BASE + 0x03ac);
293
294	/* Clear the force_jtag */
295	rk_clrreg(&grf->cpu_con[1], 1 << 7);
296
297	/* Make TSADC and WDT trigger a first global reset */
298	clrsetbits_le32(&cru->glb_rst_con, 0x3, 0x3);
299
300	return 0;
301}
302
303#ifdef CONFIG_DEBUG_UART_BOARD_INIT
304void board_debug_uart_init(void)
305{
306#if defined(CONFIG_DEBUG_UART_BASE) && \
307	(((CONFIG_DEBUG_UART_BASE == 0xff168000) && \
308	(CONFIG_DEBUG_UART_CHANNEL != 1)) || \
309	CONFIG_DEBUG_UART_BASE == 0xff030000)
310	static struct px30_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
311#endif
312#if !defined(CONFIG_DEBUG_UART_BASE) || \
313	(CONFIG_DEBUG_UART_BASE != 0xff158000 && \
314	 CONFIG_DEBUG_UART_BASE != 0xff168000 && \
315	 CONFIG_DEBUG_UART_BASE != 0xff178000 && \
316	 CONFIG_DEBUG_UART_BASE != 0xff030000) || \
317	(defined(CONFIG_DEBUG_UART_BASE) && \
318	 (CONFIG_DEBUG_UART_BASE == 0xff158000 || \
319	  CONFIG_DEBUG_UART_BASE == 0xff168000 || \
320	  CONFIG_DEBUG_UART_BASE == 0xff178000))
321	static struct px30_grf * const grf = (void *)GRF_BASE;
322	static struct px30_cru * const cru = (void *)CRU_BASE;
323#endif
324#if defined(CONFIG_DEBUG_UART_BASE) && CONFIG_DEBUG_UART_BASE == 0xff030000
325	static struct px30_pmucru * const pmucru = (void *)PMUCRU_BASE;
326#endif
327
328#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff158000)
329	/* uart_sel_clk default select 24MHz */
330	rk_clrsetreg(&cru->clksel_con[34],
331		     UART1_PLL_SEL_MASK | UART1_DIV_CON_MASK,
332		     UART1_PLL_SEL_24M << UART1_PLL_SEL_SHIFT | 0);
333	rk_clrsetreg(&cru->clksel_con[35],
334		     UART1_CLK_SEL_MASK,
335		     UART1_CLK_SEL_UART1 << UART1_CLK_SEL_SHIFT);
336
337	rk_clrsetreg(&grf->gpio1cl_iomux,
338		     GPIO1C1_MASK | GPIO1C0_MASK,
339		     GPIO1C1_UART1_TX << GPIO1C1_SHIFT |
340		     GPIO1C0_UART1_RX << GPIO1C0_SHIFT);
341#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff168000)
342	/* GRF_IOFUNC_CON0 */
343	enum {
344		CON_IOMUX_UART3SEL_SHIFT	= 9,
345		CON_IOMUX_UART3SEL_MASK = 1 << CON_IOMUX_UART3SEL_SHIFT,
346		CON_IOMUX_UART3SEL_M0	= 0,
347		CON_IOMUX_UART3SEL_M1,
348	};
349
350	/* uart_sel_clk default select 24MHz */
351	rk_clrsetreg(&cru->clksel_con[40],
352		     UART3_PLL_SEL_MASK | UART3_DIV_CON_MASK,
353		     UART3_PLL_SEL_24M << UART3_PLL_SEL_SHIFT | 0);
354	rk_clrsetreg(&cru->clksel_con[41],
355		     UART3_CLK_SEL_MASK,
356		     UART3_CLK_SEL_UART3 << UART3_CLK_SEL_SHIFT);
357
358#if (CONFIG_DEBUG_UART_CHANNEL == 1)
359	rk_clrsetreg(&grf->iofunc_con0,
360		     CON_IOMUX_UART3SEL_MASK,
361		     CON_IOMUX_UART3SEL_M1 << CON_IOMUX_UART3SEL_SHIFT);
362
363	rk_clrsetreg(&grf->gpio1bh_iomux,
364		     GPIO1B7_MASK | GPIO1B6_MASK,
365		     GPIO1B7_UART3_RXM1 << GPIO1B7_SHIFT |
366		     GPIO1B6_UART3_TXM1 << GPIO1B6_SHIFT);
367#else
368	rk_clrsetreg(&grf->iofunc_con0,
369		     CON_IOMUX_UART3SEL_MASK,
370		     CON_IOMUX_UART3SEL_M0 << CON_IOMUX_UART3SEL_SHIFT);
371
372	rk_clrsetreg(&pmugrf->gpio0cl_iomux,
373		     GPIO0C1_MASK | GPIO0C0_MASK,
374		     GPIO0C1_UART3_RXM0 << GPIO0C1_SHIFT |
375		     GPIO0C0_UART3_TXM0 << GPIO0C0_SHIFT);
376#endif /* CONFIG_DEBUG_UART_CHANNEL == 1 */
377
378#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff178000)
379	/* uart_sel_clk default select 24MHz */
380	rk_clrsetreg(&cru->clksel_con[46],
381		     UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK,
382		     UART5_PLL_SEL_24M << UART5_PLL_SEL_SHIFT | 0);
383	rk_clrsetreg(&cru->clksel_con[47],
384		     UART5_CLK_SEL_MASK,
385		     UART5_CLK_SEL_UART5 << UART5_CLK_SEL_SHIFT);
386
387	rk_clrsetreg(&grf->gpio3al_iomux,
388		     GPIO3A2_MASK | GPIO3A1_MASK,
389		     GPIO3A2_UART5_TX << GPIO3A2_SHIFT |
390		     GPIO3A1_UART5_RX << GPIO3A1_SHIFT);
391#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff030000)
392	/* uart_sel_clk default select 24MHz */
393	rk_clrsetreg(&pmucru->pmu_clksel_con[3],
394		     UART0_PLL_SEL_MASK | UART0_DIV_CON_MASK,
395		     UART0_PLL_SEL_24M << UART0_PLL_SEL_SHIFT | 0);
396	rk_clrsetreg(&pmucru->pmu_clksel_con[4],
397		     UART0_CLK_SEL_MASK,
398		     UART0_CLK_SEL_UART0 << UART0_CLK_SEL_SHIFT);
399
400	rk_clrsetreg(&pmugrf->gpio0bl_iomux,
401		     GPIO0B3_MASK | GPIO0B2_MASK,
402		     GPIO0B3_UART0_RX << GPIO0B3_SHIFT |
403		     GPIO0B2_UART0_TX << GPIO0B2_SHIFT);
404#else
405	/* GRF_IOFUNC_CON0 */
406	enum {
407		CON_IOMUX_UART2SEL_SHIFT	= 10,
408		CON_IOMUX_UART2SEL_MASK = 3 << CON_IOMUX_UART2SEL_SHIFT,
409		CON_IOMUX_UART2SEL_M0	= 0,
410		CON_IOMUX_UART2SEL_M1,
411		CON_IOMUX_UART2SEL_USBPHY,
412	};
413
414	/* uart_sel_clk default select 24MHz */
415	rk_clrsetreg(&cru->clksel_con[37],
416		     UART2_PLL_SEL_MASK | UART2_DIV_CON_MASK,
417		     UART2_PLL_SEL_24M << UART2_PLL_SEL_SHIFT | 0);
418	rk_clrsetreg(&cru->clksel_con[38],
419		     UART2_CLK_SEL_MASK,
420		     UART2_CLK_SEL_UART2 << UART2_CLK_SEL_SHIFT);
421
422#if (CONFIG_DEBUG_UART_CHANNEL == 1)
423	/* Enable early UART2 */
424	rk_clrsetreg(&grf->iofunc_con0,
425		     CON_IOMUX_UART2SEL_MASK,
426		     CON_IOMUX_UART2SEL_M1 << CON_IOMUX_UART2SEL_SHIFT);
427
428	rk_clrsetreg(&grf->gpio2bh_iomux,
429		     GPIO2B6_MASK | GPIO2B4_MASK,
430		     GPIO2B6_UART2_RXM1 << GPIO2B6_SHIFT |
431		     GPIO2B4_UART2_TXM1 << GPIO2B4_SHIFT);
432#else
433	rk_clrsetreg(&grf->iofunc_con0,
434		     CON_IOMUX_UART2SEL_MASK,
435		     CON_IOMUX_UART2SEL_M0 << CON_IOMUX_UART2SEL_SHIFT);
436
437	rk_clrsetreg(&grf->gpio1dl_iomux,
438		     GPIO1D3_MASK | GPIO1D2_MASK,
439		     GPIO1D3_UART2_RXM0 << GPIO1D3_SHIFT |
440		     GPIO1D2_UART2_TXM0 << GPIO1D2_SHIFT);
441#endif /* CONFIG_DEBUG_UART_CHANNEL == 1 */
442
443#endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */
444}
445#endif /* CONFIG_DEBUG_UART_BOARD_INIT */
446