1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Timing and Organization details of the ddr device parts used in OMAP5
4 * EVM
5 *
6 * (C) Copyright 2010
7 * Texas Instruments, <www.ti.com>
8 *
9 * Aneesh V <aneesh@ti.com>
10 * Sricharan R <r.sricharan@ti.com>
11 */
12
13#include <common.h>
14#include <asm/emif.h>
15#include <asm/arch/sys_proto.h>
16
17/*
18 * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
19 * EVM. Since the parts used and geometry are identical for
20 * evm for a given OMAP5 revision, this information is kept
21 * here instead of being in board directory. However the key functions
22 * exported are weakly linked so that they can be over-ridden in the board
23 * directory if there is a OMAP5 board in the future that uses a different
24 * memory device or geometry.
25 *
26 * For any new board with different memory devices over-ride one or more
27 * of the following functions as per the CONFIG flags you intend to enable:
28 * - emif_get_reg_dump()
29 * - emif_get_dmm_regs()
30 * - emif_get_device_details()
31 * - emif_get_device_timings()
32 */
33
34#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
35const struct emif_regs emif_regs_532_mhz_2cs = {
36	.sdram_config_init		= 0x80800EBA,
37	.sdram_config			= 0x808022BA,
38	.ref_ctrl			= 0x0000081A,
39	.sdram_tim1			= 0x772F6873,
40	.sdram_tim2			= 0x304a129a,
41	.sdram_tim3			= 0x02f7e45f,
42	.read_idle_ctrl			= 0x00050000,
43	.zq_config			= 0x000b3215,
44	.temp_alert_config		= 0x08000a05,
45	.emif_ddr_phy_ctlr_1_init	= 0x0E28420d,
46	.emif_ddr_phy_ctlr_1		= 0x0E28420d,
47	.emif_ddr_ext_phy_ctrl_1	= 0x04020080,
48	.emif_ddr_ext_phy_ctrl_2	= 0x28C518A3,
49	.emif_ddr_ext_phy_ctrl_3	= 0x518A3146,
50	.emif_ddr_ext_phy_ctrl_4	= 0x0014628C,
51	.emif_ddr_ext_phy_ctrl_5	= 0x04010040
52};
53
54const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
55	.sdram_config_init		= 0x80800EBA,
56	.sdram_config			= 0x808022BA,
57	.ref_ctrl			= 0x0000081A,
58	.sdram_tim1			= 0x772F6873,
59	.sdram_tim2			= 0x304a129a,
60	.sdram_tim3			= 0x02f7e45f,
61	.read_idle_ctrl			= 0x00050000,
62	.zq_config			= 0x100b3215,
63	.temp_alert_config		= 0x08000a05,
64	.emif_ddr_phy_ctlr_1_init	= 0x0E30400d,
65	.emif_ddr_phy_ctlr_1		= 0x0E30400d,
66	.emif_ddr_ext_phy_ctrl_1	= 0x04020080,
67	.emif_ddr_ext_phy_ctrl_2	= 0x28C518A3,
68	.emif_ddr_ext_phy_ctrl_3	= 0x518A3146,
69	.emif_ddr_ext_phy_ctrl_4	= 0x0014628C,
70	.emif_ddr_ext_phy_ctrl_5	= 0xC330CC33,
71};
72
73const struct emif_regs emif_regs_266_mhz_2cs = {
74	.sdram_config_init		= 0x80800EBA,
75	.sdram_config			= 0x808022BA,
76	.ref_ctrl			= 0x0000040D,
77	.sdram_tim1			= 0x2A86B419,
78	.sdram_tim2			= 0x1025094A,
79	.sdram_tim3			= 0x026BA22F,
80	.read_idle_ctrl			= 0x00050000,
81	.zq_config			= 0x000b3215,
82	.temp_alert_config		= 0x08000a05,
83	.emif_ddr_phy_ctlr_1_init	= 0x0E28420d,
84	.emif_ddr_phy_ctlr_1		= 0x0E28420d,
85	.emif_ddr_ext_phy_ctrl_1	= 0x04020080,
86	.emif_ddr_ext_phy_ctrl_2	= 0x0A414829,
87	.emif_ddr_ext_phy_ctrl_3	= 0x14829052,
88	.emif_ddr_ext_phy_ctrl_4	= 0x000520A4,
89	.emif_ddr_ext_phy_ctrl_5	= 0x04010040
90};
91
92const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
93	.sdram_config_init		= 0x61851B32,
94	.sdram_config			= 0x61851B32,
95	.sdram_config2			= 0x0,
96	.ref_ctrl			= 0x00001035,
97	.sdram_tim1			= 0xCCCF36B3,
98	.sdram_tim2			= 0x308F7FDA,
99	.sdram_tim3			= 0x027F88A8,
100	.read_idle_ctrl			= 0x00050000,
101	.zq_config			= 0x0007190B,
102	.temp_alert_config		= 0x00000000,
103	.emif_ddr_phy_ctlr_1_init	= 0x0020420A,
104	.emif_ddr_phy_ctlr_1		= 0x0024420A,
105	.emif_ddr_ext_phy_ctrl_1	= 0x04040100,
106	.emif_ddr_ext_phy_ctrl_2	= 0x00000000,
107	.emif_ddr_ext_phy_ctrl_3	= 0x00000000,
108	.emif_ddr_ext_phy_ctrl_4	= 0x00000000,
109	.emif_ddr_ext_phy_ctrl_5	= 0x04010040,
110	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
111	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
112	.emif_rd_wr_lvl_ctl		= 0x00000000,
113	.emif_rd_wr_exec_thresh		= 0x00000305
114};
115
116const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
117	.sdram_config_init              = 0x61851B32,
118	.sdram_config                   = 0x61851B32,
119	.sdram_config2			= 0x0,
120	.ref_ctrl                       = 0x00001035,
121	.sdram_tim1                     = 0xCCCF36B3,
122	.sdram_tim2                     = 0x308F7FDA,
123	.sdram_tim3                     = 0x027F88A8,
124	.read_idle_ctrl                 = 0x00050000,
125	.zq_config                      = 0x1007190B,
126	.temp_alert_config              = 0x00000000,
127	.emif_ddr_phy_ctlr_1_init       = 0x0030400A,
128	.emif_ddr_phy_ctlr_1            = 0x0034400A,
129	.emif_ddr_ext_phy_ctrl_1        = 0x04040100,
130	.emif_ddr_ext_phy_ctrl_2        = 0x00000000,
131	.emif_ddr_ext_phy_ctrl_3        = 0x00000000,
132	.emif_ddr_ext_phy_ctrl_4        = 0x00000000,
133	.emif_ddr_ext_phy_ctrl_5        = 0x4350D435,
134	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
135	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
136	.emif_rd_wr_lvl_ctl             = 0x00000000,
137	.emif_rd_wr_exec_thresh         = 0x40000305
138};
139
140const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
141	.dmm_lisa_map_0 = 0x0,
142	.dmm_lisa_map_1 = 0x0,
143	.dmm_lisa_map_2 = 0x80740300,
144	.dmm_lisa_map_3 = 0xFF020100,
145	.is_ma_present	= 0x1
146};
147
148static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
149{
150	switch (omap_revision()) {
151	case OMAP5430_ES1_0:
152		*regs = &emif_regs_532_mhz_2cs;
153		break;
154	case OMAP5432_ES1_0:
155		*regs = &emif_regs_ddr3_532_mhz_1cs;
156		break;
157	case OMAP5430_ES2_0:
158		*regs = &emif_regs_532_mhz_2cs_es2;
159		break;
160	case OMAP5432_ES2_0:
161	default:
162		*regs = &emif_regs_ddr3_532_mhz_1cs_es2;
163		break;
164	}
165}
166
167void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
168	__attribute__((weak, alias("emif_get_reg_dump_sdp")));
169
170static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
171						**dmm_lisa_regs)
172{
173	switch (omap_revision()) {
174	case OMAP5430_ES1_0:
175	case OMAP5430_ES2_0:
176	case OMAP5432_ES1_0:
177	case OMAP5432_ES2_0:
178	default:
179		*dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
180		break;
181	}
182
183}
184
185void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
186	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
187#else
188
189static const struct lpddr2_device_details dev_4G_S4_details = {
190	.type		= LPDDR2_TYPE_S4,
191	.density	= LPDDR2_DENSITY_4Gb,
192	.io_width	= LPDDR2_IO_WIDTH_32,
193	.manufacturer	= LPDDR2_MANUFACTURER_SAMSUNG
194};
195
196static void emif_get_device_details_sdp(u32 emif_nr,
197		struct lpddr2_device_details *cs0_device_details,
198		struct lpddr2_device_details *cs1_device_details)
199{
200	/* EMIF1 & EMIF2 have identical configuration */
201	*cs0_device_details = dev_4G_S4_details;
202	*cs1_device_details = dev_4G_S4_details;
203}
204
205void emif_get_device_details(u32 emif_nr,
206		struct lpddr2_device_details *cs0_device_details,
207		struct lpddr2_device_details *cs1_device_details)
208	__attribute__((weak, alias("emif_get_device_details_sdp")));
209
210#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
211
212const u32 ext_phy_ctrl_const_base[] = {
213	0x01004010,
214	0x00001004,
215	0x04010040,
216	0x01004010,
217	0x00001004,
218	0x00000000,
219	0x00000000,
220	0x00000000,
221	0x80080080,
222	0x00800800,
223	0x08102040,
224	0x00000001,
225	0x540A8150,
226	0xA81502a0,
227	0x002A0540,
228	0x00000000,
229	0x00000000,
230	0x00000000,
231	0x00000077,
232	0x0
233};
234
235const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
236	0x01004010,
237	0x00001004,
238	0x04010040,
239	0x01004010,
240	0x00001004,
241	0x00000000,
242	0x00000000,
243	0x00000000,
244	0x80080080,
245	0x00800800,
246	0x08102040,
247	0x00000002,
248	0x0,
249	0x0,
250	0x0,
251	0x00000000,
252	0x00000000,
253	0x00000000,
254	0x00000057,
255	0x0
256};
257
258const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
259	0x50D4350D,
260	0x00000D43,
261	0x04010040,
262	0x01004010,
263	0x00001004,
264	0x00000000,
265	0x00000000,
266	0x00000000,
267	0x80080080,
268	0x00800800,
269	0x08102040,
270	0x00000002,
271	0x00000000,
272	0x00000000,
273	0x00000000,
274	0x00000000,
275	0x00000000,
276	0x00000000,
277	0x00000057,
278	0x0
279};
280
281/* Ext phy ctrl 1-35 regs */
282const u32
283dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
284	0x10040100,
285	0x00910091,
286	0x00950095,
287	0x009B009B,
288	0x009E009E,
289	0x00980098,
290	0x00340034,
291	0x00350035,
292	0x00340034,
293	0x00310031,
294	0x00340034,
295	0x007F007F,
296	0x007F007F,
297	0x007F007F,
298	0x007F007F,
299	0x007F007F,
300	0x00480048,
301	0x004A004A,
302	0x00520052,
303	0x00550055,
304	0x00500050,
305	0x00000000,
306	0x00600020,
307	0x40011080,
308	0x08102040,
309	0x0,
310	0x0,
311	0x0,
312	0x0,
313	0x0,
314	0x0,
315	0x0,
316	0x0,
317	0x0,
318	0x0
319};
320
321/* Ext phy ctrl 1-35 regs */
322const u32
323dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
324	0x10040100,
325	0x00910091,
326	0x00950095,
327	0x009B009B,
328	0x009E009E,
329	0x00980098,
330	0x00330033,
331	0x00330033,
332	0x002F002F,
333	0x00320032,
334	0x00310031,
335	0x007F007F,
336	0x007F007F,
337	0x007F007F,
338	0x007F007F,
339	0x007F007F,
340	0x00520052,
341	0x00520052,
342	0x00470047,
343	0x00490049,
344	0x00500050,
345	0x00000000,
346	0x00600020,
347	0x40011080,
348	0x08102040,
349	0x0,
350	0x0,
351	0x0,
352	0x0,
353	0x0,
354	0x0,
355	0x0,
356	0x0,
357	0x0,
358	0x0
359};
360
361/* Ext phy ctrl 1-35 regs */
362const u32
363dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
364	0x10040100,
365	0x00A400A4,
366	0x00A900A9,
367	0x00B000B0,
368	0x00B000B0,
369	0x00A400A4,
370	0x00390039,
371	0x00320032,
372	0x00320032,
373	0x00320032,
374	0x00440044,
375	0x00550055,
376	0x00550055,
377	0x00550055,
378	0x00550055,
379	0x007F007F,
380	0x004D004D,
381	0x00430043,
382	0x00560056,
383	0x00540054,
384	0x00600060,
385	0x0,
386	0x00600020,
387	0x40010080,
388	0x08102040,
389	0x0,
390	0x0,
391	0x0,
392	0x0,
393	0x0,
394	0x0,
395	0x0,
396	0x0,
397	0x0,
398	0x0
399};
400
401const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = {
402	0x04040100,
403	0x006B009F,
404	0x006B00A2,
405	0x006B00A8,
406	0x006B00A8,
407	0x006B00B2,
408	0x002F002F,
409	0x002F002F,
410	0x002F002F,
411	0x002F002F,
412	0x002F002F,
413	0x00600073,
414	0x00600071,
415	0x0060007C,
416	0x0060007E,
417	0x00600084,
418	0x00400053,
419	0x00400051,
420	0x0040005C,
421	0x0040005E,
422	0x00400064,
423	0x00800080,
424	0x00800080,
425	0x40010080,
426	0x08102040,
427	0x005B008F,
428	0x005B0092,
429	0x005B0098,
430	0x005B0098,
431	0x005B00A2,
432	0x00300043,
433	0x00300041,
434	0x0030004C,
435	0x0030004E,
436	0x00300054,
437	0x00000077
438};
439
440const struct lpddr2_mr_regs mr_regs = {
441	.mr1	= MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
442	.mr2	= 0x6,
443	.mr3	= 0x1,
444	.mr10	= MR10_ZQ_ZQINIT,
445	.mr16	= MR16_REF_FULL_ARRAY
446};
447
448void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
449					     const u32 **regs,
450					     u32 *size)
451{
452	switch (omap_revision()) {
453	case OMAP5430_ES1_0:
454	case OMAP5430_ES2_0:
455		*regs = ext_phy_ctrl_const_base;
456		*size = ARRAY_SIZE(ext_phy_ctrl_const_base);
457		break;
458	case OMAP5432_ES1_0:
459		*regs = ddr3_ext_phy_ctrl_const_base_es1;
460		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
461		break;
462	case OMAP5432_ES2_0:
463		*regs = ddr3_ext_phy_ctrl_const_base_es2;
464		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
465		break;
466	case DRA752_ES1_0:
467	case DRA752_ES1_1:
468	case DRA752_ES2_0:
469		if (emif_nr == 1) {
470			*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
471			*size =
472			ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
473		} else {
474			*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
475			*size =
476			ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
477		}
478		break;
479	case DRA722_ES1_0:
480		*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
481		*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
482		break;
483	case DRA762_ES1_0:
484	case DRA762_ABZ_ES1_0:
485	case DRA762_ACD_ES1_0:
486	case DRA722_ES2_0:
487	case DRA722_ES2_1:
488		*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
489		*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);
490		break;
491	default:
492		*regs = ddr3_ext_phy_ctrl_const_base_es2;
493		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
494
495	}
496}
497
498void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
499{
500	*regs = &mr_regs;
501}
502
503static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs)
504{
505	u32 *ext_phy_ctrl_base = 0;
506	u32 *emif_ext_phy_ctrl_base = 0;
507	u32 emif_nr;
508	const u32 *ext_phy_ctrl_const_regs;
509	u32 i = 0;
510	u32 size;
511
512	emif_nr = (base == EMIF1_BASE) ? 1 : 2;
513
514	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
515
516	ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
517	emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
518
519	/* Configure external phy control timing registers */
520	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
521		writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
522		/* Update shadow registers */
523		writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
524	}
525
526	/*
527	 * external phy 6-24 registers do not change with
528	 * ddr frequency
529	 */
530	emif_get_ext_phy_ctrl_const_regs(emif_nr,
531					 &ext_phy_ctrl_const_regs, &size);
532
533	for (i = 0; i < size; i++) {
534		writel(ext_phy_ctrl_const_regs[i],
535		       emif_ext_phy_ctrl_base++);
536		/* Update shadow registers */
537		writel(ext_phy_ctrl_const_regs[i],
538		       emif_ext_phy_ctrl_base++);
539	}
540}
541
542static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
543{
544	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
545	u32 *emif_ext_phy_ctrl_base = 0;
546	u32 emif_nr;
547	const u32 *ext_phy_ctrl_const_regs;
548	u32 i, hw_leveling, size, phy;
549
550	emif_nr = (base == EMIF1_BASE) ? 1 : 2;
551
552	hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;
553	phy = regs->emif_ddr_phy_ctlr_1_init;
554
555	emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);
556
557	emif_get_ext_phy_ctrl_const_regs(emif_nr,
558					 &ext_phy_ctrl_const_regs, &size);
559
560	writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]);
561	writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]);
562
563	/*
564	 * Copy the predefined PHY register values
565	 * if leveling is disabled.
566	 */
567	if (phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)
568		for (i = 1; i < 6; i++) {
569			writel(ext_phy_ctrl_const_regs[i],
570			       &emif_ext_phy_ctrl_base[i * 2]);
571			writel(ext_phy_ctrl_const_regs[i],
572			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
573		}
574
575	if (phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK)
576		for (i = 6; i < 11; i++) {
577			writel(ext_phy_ctrl_const_regs[i],
578			       &emif_ext_phy_ctrl_base[i * 2]);
579			writel(ext_phy_ctrl_const_regs[i],
580			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
581		}
582
583	if (phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)
584		for (i = 11; i < 25; i++) {
585			writel(ext_phy_ctrl_const_regs[i],
586			       &emif_ext_phy_ctrl_base[i * 2]);
587			writel(ext_phy_ctrl_const_regs[i],
588			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
589		}
590
591	if (hw_leveling) {
592		/*
593		 * Write the init value for HW levling to occur
594		 */
595		for (i = 21; i < 35; i++) {
596			writel(ext_phy_ctrl_const_regs[i],
597			       &emif_ext_phy_ctrl_base[i * 2]);
598			writel(ext_phy_ctrl_const_regs[i],
599			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
600		}
601	}
602}
603
604void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
605{
606	if (is_omap54xx())
607		do_ext_phy_settings_omap5(base, regs);
608	else
609		do_ext_phy_settings_dra7(base, regs);
610}
611
612#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
613static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
614	.max_freq	= 532000000,
615	.RL		= 8,
616	.tRPab		= 21,
617	.tRCD		= 18,
618	.tWR		= 15,
619	.tRASmin	= 42,
620	.tRRD		= 10,
621	.tWTRx2		= 15,
622	.tXSR		= 140,
623	.tXPx2		= 15,
624	.tRFCab		= 130,
625	.tRTPx2		= 15,
626	.tCKE		= 3,
627	.tCKESR		= 15,
628	.tZQCS		= 90,
629	.tZQCL		= 360,
630	.tZQINIT	= 1000,
631	.tDQSCKMAXx2	= 11,
632	.tRASmax	= 70,
633	.tFAW		= 50
634};
635
636static const struct lpddr2_min_tck min_tck = {
637	.tRL		= 3,
638	.tRP_AB		= 3,
639	.tRCD		= 3,
640	.tWR		= 3,
641	.tRAS_MIN	= 3,
642	.tRRD		= 2,
643	.tWTR		= 2,
644	.tXP		= 2,
645	.tRTP		= 2,
646	.tCKE		= 3,
647	.tCKESR		= 3,
648	.tFAW		= 8
649};
650
651static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
652	&timings_jedec_532_mhz
653};
654
655static const struct lpddr2_device_timings dev_4G_S4_timings = {
656	.ac_timings	= ac_timings,
657	.min_tck	= &min_tck,
658};
659
660/*
661 * List of status registers to be controlled back to control registers
662 * after initial leveling
663 * readreg, writereg
664 */
665const struct read_write_regs omap5_bug_00339_regs[] = {
666	{ 8,  5 },
667	{ 9,  6 },
668	{ 10, 7 },
669	{ 14, 8 },
670	{ 15, 9 },
671	{ 16, 10 },
672	{ 11, 2 },
673	{ 12, 3 },
674	{ 13, 4 },
675	{ 17, 11 },
676	{ 18, 12 },
677	{ 19, 13 },
678};
679
680const struct read_write_regs dra_bug_00339_regs[] = {
681	{ 7,  7 },
682	{ 8,  8 },
683	{ 9,  9 },
684	{ 10, 10 },
685	{ 11, 11 },
686	{ 12, 2 },
687	{ 13, 3 },
688	{ 14, 4 },
689	{ 15, 5 },
690	{ 16, 6 },
691	{ 17, 12 },
692	{ 18, 13 },
693	{ 19, 14 },
694	{ 20, 15 },
695	{ 21, 16 },
696	{ 22, 17 },
697	{ 23, 18 },
698	{ 24, 19 },
699	{ 25, 20 },
700	{ 26, 21}
701};
702
703const struct read_write_regs *get_bug_regs(u32 *iterations)
704{
705	const struct read_write_regs *bug_00339_regs_ptr = NULL;
706
707	switch (omap_revision()) {
708	case OMAP5430_ES1_0:
709	case OMAP5430_ES2_0:
710	case OMAP5432_ES1_0:
711	case OMAP5432_ES2_0:
712		bug_00339_regs_ptr = omap5_bug_00339_regs;
713		*iterations = sizeof(omap5_bug_00339_regs)/
714			     sizeof(omap5_bug_00339_regs[0]);
715		break;
716	case DRA762_ABZ_ES1_0:
717	case DRA762_ACD_ES1_0:
718	case DRA762_ES1_0:
719	case DRA752_ES1_0:
720	case DRA752_ES1_1:
721	case DRA752_ES2_0:
722	case DRA722_ES1_0:
723	case DRA722_ES2_0:
724	case DRA722_ES2_1:
725		bug_00339_regs_ptr = dra_bug_00339_regs;
726		*iterations = sizeof(dra_bug_00339_regs)/
727			     sizeof(dra_bug_00339_regs[0]);
728		break;
729	default:
730		printf("\n Error: UnKnown SOC");
731	}
732
733	return bug_00339_regs_ptr;
734}
735
736void emif_get_device_timings_sdp(u32 emif_nr,
737		const struct lpddr2_device_timings **cs0_device_timings,
738		const struct lpddr2_device_timings **cs1_device_timings)
739{
740	/* Identical devices on EMIF1 & EMIF2 */
741	*cs0_device_timings = &dev_4G_S4_timings;
742	*cs1_device_timings = &dev_4G_S4_timings;
743}
744
745void emif_get_device_timings(u32 emif_nr,
746		const struct lpddr2_device_timings **cs0_device_timings,
747		const struct lpddr2_device_timings **cs1_device_timings)
748	__attribute__((weak, alias("emif_get_device_timings_sdp")));
749
750#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
751