1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6#ifndef _SYS_ENV_LIB_H 7#define _SYS_ENV_LIB_H 8 9#include "../../../drivers/ddr/marvell/a38x/ddr3_init.h" 10 11/* Serdes definitions */ 12#define COMMON_PHY_BASE_ADDR 0x18300 13 14#define DEVICE_CONFIGURATION_REG0 0x18284 15#define DEVICE_CONFIGURATION_REG1 0x18288 16#define COMMON_PHY_CONFIGURATION1_REG 0x18300 17#define COMMON_PHY_CONFIGURATION2_REG 0x18304 18#define COMMON_PHY_CONFIGURATION4_REG 0x1830c 19#define COMMON_PHY_STATUS1_REG 0x18318 20#define COMMON_PHYS_SELECTORS_REG 0x183fc 21#define SOC_CONTROL_REG1 0x18204 22#define GENERAL_PURPOSE_RESERVED0_REG 0x182e0 23#define GBE_CONFIGURATION_REG 0x18460 24#define DEVICE_SAMPLE_AT_RESET1_REG 0x18600 25#define DEVICE_SAMPLE_AT_RESET2_REG 0x18604 26#define DEV_ID_REG 0x18238 27 28#define CORE_PLL_PARAMETERS_REG 0xe42e0 29#define CORE_PLL_CONFIG_REG 0xe42e4 30 31#define QSGMII_CONTROL_REG1 0x18494 32 33#define DEV_ID_REG_DEVICE_ID_OFFS 16 34#define DEV_ID_REG_DEVICE_ID_MASK 0xffff0000 35 36#define SAR_FREQ_OFFSET 10 37#define SAR_FREQ_MASK 0x1f 38#define SAR_DEV_ID_OFFS 27 39#define SAR_DEV_ID_MASK 0x7 40 41#define POWER_AND_PLL_CTRL_REG 0xa0004 42#define CALIBRATION_CTRL_REG 0xa0008 43#define DFE_REG0 0xa001c 44#define DFE_REG3 0xa0028 45#define RESET_DFE_REG 0xa0148 46#define LOOPBACK_REG 0xa008c 47#define SYNC_PATTERN_REG 0xa0090 48#define INTERFACE_REG 0xa0094 49#define ISOLATE_REG 0xa0098 50#define MISC_REG 0xa013c 51#define GLUE_REG 0xa0140 52#define GENERATION_DIVIDER_FORCE_REG 0xa0144 53#define PLLINTP_REG1 0xa0150 54#define PCIE_REG0 0xa0120 55#define LANE_ALIGN_REG0 0xa0124 56#define SQUELCH_FFE_SETTING_REG 0xa0018 57#define G1_SETTINGS_0_REG 0xa0034 58#define G1_SETTINGS_1_REG 0xa0038 59#define G1_SETTINGS_3_REG 0xa0440 60#define G1_SETTINGS_4_REG 0xa0444 61#define G2_SETTINGS_0_REG 0xa003c 62#define G2_SETTINGS_1_REG 0xa0040 63#define G2_SETTINGS_2_REG 0xa00f8 64#define G2_SETTINGS_3_REG 0xa0448 65#define G2_SETTINGS_4_REG 0xa044c 66#define G3_SETTINGS_0_REG 0xa0044 67#define G3_SETTINGS_1_REG 0xa0048 68#define G3_SETTINGS_3_REG 0xa0450 69#define G3_SETTINGS_4_REG 0xa0454 70#define VTHIMPCAL_CTRL_REG 0xa0104 71#define REF_REG0 0xa0134 72#define CAL_REG6 0xa0168 73#define RX_REG2 0xa0184 74#define RX_REG3 0xa0188 75#define PCIE_REG1 0xa0288 76#define PCIE_REG3 0xa0290 77#define LANE_CFG0_REG 0xa0600 78#define LANE_CFG1_REG 0xa0604 79#define LANE_CFG4_REG 0xa0620 80#define LANE_CFG5_REG 0xa0624 81#define GLOBAL_CLK_CTRL 0xa0704 82#define GLOBAL_TEST_CTRL 0xa0708 83#define GLOBAL_MISC_CTRL 0xa0718 84#define GLOBAL_CLK_SRC_HI 0xa0710 85 86#define GLOBAL_CLK_CTRL 0xa0704 87#define GLOBAL_MISC_CTRL 0xa0718 88#define GLOBAL_PM_CTRL 0xa0740 89 90/* SATA registers */ 91#define SATA_CTRL_REG_IND_ADDR 0xa80a0 92#define SATA_CTRL_REG_IND_DATA 0xa80a4 93 94#define SATA_VENDOR_PORT_0_REG_ADDR 0xa8178 95#define SATA_VENDOR_PORT_1_REG_ADDR 0xa81f8 96#define SATA_VENDOR_PORT_0_REG_DATA 0xa817c 97#define SATA_VENDOR_PORT_1_REG_DATA 0xa81fc 98 99/* Reference clock values and mask */ 100#define POWER_AND_PLL_CTRL_REG_100MHZ_VAL 0x0 101#define POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1 0x1 102#define POWER_AND_PLL_CTRL_REG_25MHZ_VAL_2 0x2 103#define POWER_AND_PLL_CTRL_REG_40MHZ_VAL 0x3 104#define GLOBAL_PM_CTRL_REG_25MHZ_VAL 0x7 105#define GLOBAL_PM_CTRL_REG_40MHZ_VAL 0xc 106#define LANE_CFG4_REG_25MHZ_VAL 0x200 107#define LANE_CFG4_REG_40MHZ_VAL 0x300 108 109#define POWER_AND_PLL_CTRL_REG_MASK (~(0x1f)) 110#define GLOBAL_PM_CTRL_REG_MASK (~(0xff)) 111#define LANE_CFG4_REG_MASK (~(0x1f00)) 112 113#define REF_CLK_SELECTOR_VAL_PEX0(reg_val) (reg_val >> 2) & 0x1 114#define REF_CLK_SELECTOR_VAL_PEX1(reg_val) (reg_val >> 3) & 0x1 115#define REF_CLK_SELECTOR_VAL_PEX2(reg_val) (reg_val >> 30) & 0x1 116#define REF_CLK_SELECTOR_VAL_PEX3(reg_val) (reg_val >> 31) & 0x1 117#define REF_CLK_SELECTOR_VAL(reg_val) (reg_val & 0x1) 118 119#define MAX_SELECTOR_VAL 10 120 121/* TWSI addresses */ 122/* starting from A38x A0, i2c address of EEPROM is 0x57 */ 123#define EEPROM_I2C_ADDR (sys_env_device_rev_get() == \ 124 MV_88F68XX_Z1_ID ? 0x50 : 0x57) 125#define RD_GET_MODE_ADDR 0x4c 126#define DB_GET_MODE_SLM1363_ADDR 0x25 127#define DB_GET_MODE_SLM1364_ADDR 0x24 128#define DB381_GET_MODE_SLM1426_1427_ADDR 0x56 129 130/* DB-BP Board 'SatR' mapping */ 131#define SATR_DB_LANE1_MAX_OPTIONS 7 132#define SATR_DB_LANE1_CFG_MASK 0x7 133#define SATR_DB_LANE1_CFG_OFFSET 0 134#define SATR_DB_LANE2_MAX_OPTIONS 4 135#define SATR_DB_LANE2_CFG_MASK 0x38 136#define SATR_DB_LANE2_CFG_OFFSET 3 137 138/* GP Board 'SatR' mapping */ 139#define SATR_GP_LANE1_CFG_MASK 0x4 140#define SATR_GP_LANE1_CFG_OFFSET 2 141#define SATR_GP_LANE2_CFG_MASK 0x8 142#define SATR_GP_LANE2_CFG_OFFSET 3 143 144/* For setting MPP2 and MPP3 to be TWSI mode and MPP 0,1 to UART mode */ 145#define MPP_CTRL_REG 0x18000 146#define MPP_SET_MASK (~(0xffff)) 147#define MPP_SET_DATA (0x1111) 148#define MPP_UART1_SET_MASK (~(0xff000)) 149#define MPP_UART1_SET_DATA (0x66000) 150 151#define DFX_PIPE_SELECT_PIPE0_ACTIVE_OFFS 0 152/* DFX_PIPE_SELECT_XBAR_CLIENT_SEL_OFFS: Since address completion in 14bit 153 * address mode, and given that [14:8] => [19:13], the 2 lower bits [9:8] => 154 * [14:13] are dismissed. hence field offset is also shifted to 10 155 */ 156#define DFX_PIPE_SELECT_XBAR_CLIENT_SEL_OFFS 10 157 158#define RTC_MEMORY_CTRL_REG_BASE 0xE6000 159#define RTC_MEMORY_WRAPPER_COUNT 8 160#define RTC_MEMORY_WRAPPER_REG(i) (RTC_MEMORY_CTRL_REG_BASE + ((i) * 0x40)) 161#define RTC_MEMORY_CTRL_PDLVMC_FIELD_OFFS 6 162#define RTC_MEMORY_WRAPPER_CTRL_VAL (0x1 << RTC_MEMORY_CTRL_PDLVMC_FIELD_OFFS) 163 164#define AVS_DEBUG_CNTR_REG 0xe4124 165#define AVS_DEBUG_CNTR_DEFAULT_VALUE 0x08008073 166 167#define AVS_ENABLED_CONTROL 0xe4130 168#define AVS_LOW_VDD_LIMIT_OFFS 4 169#define AVS_LOW_VDD_LIMIT_MASK (0xff << AVS_LOW_VDD_LIMIT_OFFS) 170#define AVS_LOW_VDD_LIMIT_VAL (0x27 << AVS_LOW_VDD_LIMIT_OFFS) 171#define AVS_LOW_VDD_SLOW_VAL (0x23 << AVS_LOW_VDD_LIMIT_OFFS) 172 173#define AVS_HIGH_VDD_LIMIT_OFFS 12 174#define AVS_HIGH_VDD_LIMIT_MASK (0xff << AVS_HIGH_VDD_LIMIT_OFFS) 175#define AVS_HIGH_VDD_LIMIT_VAL (0x27 << AVS_HIGH_VDD_LIMIT_OFFS) 176#define AVS_HIGH_VDD_SLOW_VAL (0x23 << AVS_HIGH_VDD_LIMIT_OFFS) 177 178/* Board ID numbers */ 179#define MARVELL_BOARD_ID_MASK 0x10 180/* Customer boards for A38x */ 181#define A38X_CUSTOMER_BOARD_ID_BASE 0x0 182#define A38X_CUSTOMER_BOARD_ID0 (A38X_CUSTOMER_BOARD_ID_BASE + 0) 183#define A38X_CUSTOMER_BOARD_ID1 (A38X_CUSTOMER_BOARD_ID_BASE + 1) 184#define A38X_MV_MAX_CUSTOMER_BOARD_ID (A38X_CUSTOMER_BOARD_ID_BASE + 2) 185#define A38X_MV_CUSTOMER_BOARD_NUM (A38X_MV_MAX_CUSTOMER_BOARD_ID - \ 186 A38X_CUSTOMER_BOARD_ID_BASE) 187 188/* Marvell boards for A38x */ 189#define A38X_MARVELL_BOARD_ID_BASE 0x10 190#define RD_NAS_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 0) 191#define DB_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 1) 192#define RD_AP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 2) 193#define DB_AP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 3) 194#define DB_GP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 4) 195#define DB_BP_6821_ID (A38X_MARVELL_BOARD_ID_BASE + 5) 196#define DB_AMC_6820_ID (A38X_MARVELL_BOARD_ID_BASE + 6) 197#define A38X_MV_MAX_MARVELL_BOARD_ID (A38X_MARVELL_BOARD_ID_BASE + 7) 198#define A38X_MV_MARVELL_BOARD_NUM (A38X_MV_MAX_MARVELL_BOARD_ID - \ 199 A38X_MARVELL_BOARD_ID_BASE) 200 201#define CUTOMER_BOARD_ID_BASE A38X_CUSTOMER_BOARD_ID_BASE 202#define CUSTOMER_BOARD_ID0 A38X_CUSTOMER_BOARD_ID0 203#define CUSTOMER_BOARD_ID1 A38X_CUSTOMER_BOARD_ID1 204#define MV_MAX_CUSTOMER_BOARD_ID A38X_MV_MAX_CUSTOMER_BOARD_ID 205#define MV_CUSTOMER_BOARD_NUM A38X_MV_CUSTOMER_BOARD_NUM 206#define MARVELL_BOARD_ID_BASE A38X_MARVELL_BOARD_ID_BASE 207#define MV_MAX_MARVELL_BOARD_ID A38X_MV_MAX_MARVELL_BOARD_ID 208#define MV_MARVELL_BOARD_NUM A38X_MV_MARVELL_BOARD_NUM 209#define MV_DEFAULT_BOARD_ID DB_68XX_ID 210#define MV_DEFAULT_DEVICE_ID MV_6811 211 212#define MV_INVALID_BOARD_ID 0xffffffff 213 214/* device revesion */ 215#define DEV_VERSION_ID_REG 0x1823c 216#define REVISON_ID_OFFS 8 217#define REVISON_ID_MASK 0xf00 218 219/* A38x revisions */ 220#define MV_88F68XX_Z1_ID 0x0 221#define MV_88F68XX_A0_ID 0x4 222#define MV_88F68XX_B0_ID 0xa 223 224#define MPP_CONTROL_REG(id) (0x18000 + (id * 4)) 225#define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00) 226#define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04) 227#define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10) 228#define MV_GPP_REGS_BASE(unit) (0x18100 + ((unit) * 0x40)) 229 230#define MPP_REG_NUM(GPIO_NUM) (GPIO_NUM / 8) 231#define MPP_MASK(GPIO_NUM) (0xf << 4 * (GPIO_NUM - \ 232 (MPP_REG_NUM(GPIO_NUM) * 8))); 233#define GPP_REG_NUM(GPIO_NUM) (GPIO_NUM / 32) 234#define GPP_MASK(GPIO_NUM) (1 << GPIO_NUM % 32) 235 236/* device ID */ 237/* Armada 38x Family */ 238#define MV_6810_DEV_ID 0x6810 239#define MV_6811_DEV_ID 0x6811 240#define MV_6820_DEV_ID 0x6820 241#define MV_6828_DEV_ID 0x6828 242 243enum { 244 MV_6810, 245 MV_6820, 246 MV_6811, 247 MV_6828, 248}; 249 250#define MV_6820_INDEX 0 251#define MV_6810_INDEX 1 252#define MV_6811_INDEX 2 253#define MV_6828_INDEX 3 254 255#define MAX_DEV_ID_NUM 4 256 257#define MV_6820_INDEX 0 258#define MV_6810_INDEX 1 259#define MV_6811_INDEX 2 260#define MV_6828_INDEX 3 261 262enum unit_id { 263 PEX_UNIT_ID, 264 ETH_GIG_UNIT_ID, 265 USB3H_UNIT_ID, 266 USB3D_UNIT_ID, 267 SATA_UNIT_ID, 268 QSGMII_UNIT_ID, 269 XAUI_UNIT_ID, 270 RXAUI_UNIT_ID, 271 MAX_UNITS_ID 272}; 273 274struct board_wakeup_gpio { 275 u32 board_id; 276 int gpio_num; 277}; 278 279enum suspend_wakeup_status { 280 SUSPEND_WAKEUP_DISABLED, 281 SUSPEND_WAKEUP_ENABLED, 282 SUSPEND_WAKEUP_ENABLED_GPIO_DETECTED, 283}; 284 285/* 286 * GPIO status indication for Suspend Wakeup: 287 * If suspend to RAM is supported and GPIO inidcation is implemented, 288 * set the gpio number 289 * If suspend to RAM is supported but GPIO indication is not implemented 290 * set '-2' 291 * If suspend to RAM is not supported set '-1' 292 */ 293#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT 294#define MV_BOARD_WAKEUP_GPIO_INFO { \ 295 {A38X_CUSTOMER_BOARD_ID0, -1 }, \ 296 {A38X_CUSTOMER_BOARD_ID0, -1 }, \ 297}; 298 299#else 300 301#define MV_BOARD_WAKEUP_GPIO_INFO { \ 302 {RD_NAS_68XX_ID, -2 }, \ 303 {DB_68XX_ID, -1 }, \ 304 {RD_AP_68XX_ID, -2 }, \ 305 {DB_AP_68XX_ID, -2 }, \ 306 {DB_GP_68XX_ID, -2 }, \ 307 {DB_BP_6821_ID, -2 }, \ 308 {DB_AMC_6820_ID, -2 }, \ 309}; 310#endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */ 311 312u32 mv_board_tclk_get(void); 313u32 mv_board_id_get(void); 314u32 mv_board_id_index_get(u32 board_id); 315u32 sys_env_unit_max_num_get(enum unit_id unit); 316enum suspend_wakeup_status sys_env_suspend_wakeup_check(void); 317u8 sys_env_device_rev_get(void); 318u32 sys_env_device_id_get(void); 319u16 sys_env_model_get(void); 320struct dlb_config *sys_env_dlb_config_ptr_get(void); 321u32 sys_env_get_cs_ena_from_reg(void); 322 323#endif /* _SYS_ENV_LIB_H */ 324