#
117481d2 |
|
29-Jan-2023 |
Pali Rohár <pali@kernel.org> |
arm: mvebu: Remove A39x relicts Signed-off-by: Pali Rohár <pali@kernel.org> |
#
50b5544c |
|
09-Dec-2021 |
Stefan Eichenberger <eichest@gmail.com> |
arm: mvebu: a38x: serdes: improve USB3 electrical configuration This is a backport from Marvell U-Boot: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell commit 381d029e7a ("fix: serdes: a38x, a39x: Improve USB3 electrical configuration") Improves electrical USB3 receiver jitter tolerance test: - De-Emphasize force, in functional mode the transmitter should always have 3.5db de-emphasize, so we are forcing it. - After forcing De-Emphasize, choose 3.5db (After forcing, default is 6dB so need to change it to 3.5dB). - Align90 set to 0x58 - this is the sample point in the receiver, after the clock is recovered this sampler samples at the chosen value, usually it is supposed to be 0x60(which is the center of the eye), but sometimes after adding jitter and ISI the center of the eye can move slightly and the sample point is not necessarily the exact center, and after optimization (searching the middle of the eye manually) it was seen that the center of the eye is actually 0x58 and not 0x60. - FFE Res and FFE Cap set to 0xE & 0xF respectively: improves this settings is adequate according to how the USB3 spec defines the interconnect, thus improves USB3 jitter tolerance settings. - Change the resolution of the DFE to 0x3 which is 6mV(highest resolution) , this avoids the DFE to saturate and cease to work. - HPF set to 0x3 which is 5Khz high pass filter, the function of the HPF is to filter the low frequency patterns(below 5Khz) to make sure that the signal is not a noise, the setting before was 0x1(205Khz), and the change came since the USB3 CP0 pattern, that is used in the USB3 jitter tolerance testing, is similar to PRBS15, which has 2^15=32768bits which is 32768*200ps (200ps is one Unit interval in USB3(5Gbps)) = 6.5us, which is in frequency terms: 152Khz. since the PRBS15 is a random pattern and can theoretically have once in a while a pattern that will be at frequency of 152Khz, hence the previous setting (205khz HPF) can possibly filter this pattern which can cause to an error in the receiver, thus this change to avoid such scenarios. Signed-off-by: Stefan Eichenberger <eichest@gmail.com> Signed-off-by: René Straub <rene.straub@netmodule.com> Reviewed-by: Stefan Roese <sr@denx.de> |
#
15942805 |
|
05-Mar-2021 |
Pali Rohár <pali@kernel.org> |
arm: mvebu: a38x: Remove dead code ARMADA_39X Config option ARMADA_39X is never set so remove all dead code hidden under ifdef CONFIG_ARMADA_39X blocks. Also remove useless checks for CONFIG_ARMADA_38X define as this macro is always defined for a38x code path. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> |
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de> |
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de> |
#
28be54dc |
|
27-May-2018 |
Rabeeh Khoury <rabeeh@solid-run.com> |
mvebu: a38x: Force receiver detected on PCIe lanes Some QCA988x based modules presence is not detected by the SERDES lanes, so force this detection which will trigger the LTSSM state machine to negotiate link. An example of such a card is WLE900VX. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Tested-by: Chris Packham <judge.packham@gmail.com> Tested-by: Mario Six <mario.six@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de> |
#
c4195d55 |
|
09-May-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: a38x: move sys_env_device_rev_get Move sys_env_device_rev_get() from the ddr training code to sys_env_lib.c (which currently resides with the serdes code). This brings sys_env_device_rev_get() into line with sys_env_device_id_get() and sys_env_model_get(). Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
544acb07 |
|
23-Oct-2015 |
Kevin Smith <kevin.smith@elecsyscorp.com> |
arm: mvebu: a38x: Remove unsupported topologies A lot of extra configuration information was left over in the Marvell serdes and DDR3 initialization code for boards that U-boot does not support. Remove this extra config information, and the concept of fixing up board topologies with information loaded from an EEPROM. If this needs to be done, it should be handled in the board file, not in core code. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Luka Perkov <luka.perkov@sartura.hr> |
#
edb47025 |
|
20-Apr-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: Add Armada 38x SERDES / PHY init code from Marvell bin_hdr This code is ported from the Marvell bin_hdr code into mainline SPL U-Boot. It needs to be executed very early so that the devices connected to the serdes PHY are configured correctly. Signed-off-by: Stefan Roese <sr@denx.de> |
#
50b5544c |
|
09-Dec-2021 |
Stefan Eichenberger <eichest@gmail.com> |
arm: mvebu: a38x: serdes: improve USB3 electrical configuration This is a backport from Marvell U-Boot: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell commit 381d029e7a ("fix: serdes: a38x, a39x: Improve USB3 electrical configuration") Improves electrical USB3 receiver jitter tolerance test: - De-Emphasize force, in functional mode the transmitter should always have 3.5db de-emphasize, so we are forcing it. - After forcing De-Emphasize, choose 3.5db (After forcing, default is 6dB so need to change it to 3.5dB). - Align90 set to 0x58 - this is the sample point in the receiver, after the clock is recovered this sampler samples at the chosen value, usually it is supposed to be 0x60(which is the center of the eye), but sometimes after adding jitter and ISI the center of the eye can move slightly and the sample point is not necessarily the exact center, and after optimization (searching the middle of the eye manually) it was seen that the center of the eye is actually 0x58 and not 0x60. - FFE Res and FFE Cap set to 0xE & 0xF respectively: improves this settings is adequate according to how the USB3 spec defines the interconnect, thus improves USB3 jitter tolerance settings. - Change the resolution of the DFE to 0x3 which is 6mV(highest resolution) , this avoids the DFE to saturate and cease to work. - HPF set to 0x3 which is 5Khz high pass filter, the function of the HPF is to filter the low frequency patterns(below 5Khz) to make sure that the signal is not a noise, the setting before was 0x1(205Khz), and the change came since the USB3 CP0 pattern, that is used in the USB3 jitter tolerance testing, is similar to PRBS15, which has 2^15=32768bits which is 32768*200ps (200ps is one Unit interval in USB3(5Gbps)) = 6.5us, which is in frequency terms: 152Khz. since the PRBS15 is a random pattern and can theoretically have once in a while a pattern that will be at frequency of 152Khz, hence the previous setting (205khz HPF) can possibly filter this pattern which can cause to an error in the receiver, thus this change to avoid such scenarios. Signed-off-by: Stefan Eichenberger <eichest@gmail.com> Signed-off-by: René Straub <rene.straub@netmodule.com> Reviewed-by: Stefan Roese <sr@denx.de> |
#
15942805 |
|
05-Mar-2021 |
Pali Rohár <pali@kernel.org> |
arm: mvebu: a38x: Remove dead code ARMADA_39X Config option ARMADA_39X is never set so remove all dead code hidden under ifdef CONFIG_ARMADA_39X blocks. Also remove useless checks for CONFIG_ARMADA_38X define as this macro is always defined for a38x code path. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> |
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de> |
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de> |
#
28be54dc |
|
27-May-2018 |
Rabeeh Khoury <rabeeh@solid-run.com> |
mvebu: a38x: Force receiver detected on PCIe lanes Some QCA988x based modules presence is not detected by the SERDES lanes, so force this detection which will trigger the LTSSM state machine to negotiate link. An example of such a card is WLE900VX. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Tested-by: Chris Packham <judge.packham@gmail.com> Tested-by: Mario Six <mario.six@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de> |
#
c4195d55 |
|
09-May-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: a38x: move sys_env_device_rev_get Move sys_env_device_rev_get() from the ddr training code to sys_env_lib.c (which currently resides with the serdes code). This brings sys_env_device_rev_get() into line with sys_env_device_id_get() and sys_env_model_get(). Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
544acb07 |
|
23-Oct-2015 |
Kevin Smith <kevin.smith@elecsyscorp.com> |
arm: mvebu: a38x: Remove unsupported topologies A lot of extra configuration information was left over in the Marvell serdes and DDR3 initialization code for boards that U-boot does not support. Remove this extra config information, and the concept of fixing up board topologies with information loaded from an EEPROM. If this needs to be done, it should be handled in the board file, not in core code. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Luka Perkov <luka.perkov@sartura.hr> |
#
edb47025 |
|
20-Apr-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: Add Armada 38x SERDES / PHY init code from Marvell bin_hdr This code is ported from the Marvell bin_hdr code into mainline SPL U-Boot. It needs to be executed very early so that the devices connected to the serdes PHY are configured correctly. Signed-off-by: Stefan Roese <sr@denx.de> |
#
15942805 |
|
05-Mar-2021 |
Pali Rohár <pali@kernel.org> |
arm: mvebu: a38x: Remove dead code ARMADA_39X Config option ARMADA_39X is never set so remove all dead code hidden under ifdef CONFIG_ARMADA_39X blocks. Also remove useless checks for CONFIG_ARMADA_38X define as this macro is always defined for a38x code path. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> |
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de> |
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de> |
#
28be54dc |
|
27-May-2018 |
Rabeeh Khoury <rabeeh@solid-run.com> |
mvebu: a38x: Force receiver detected on PCIe lanes Some QCA988x based modules presence is not detected by the SERDES lanes, so force this detection which will trigger the LTSSM state machine to negotiate link. An example of such a card is WLE900VX. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Tested-by: Chris Packham <judge.packham@gmail.com> Tested-by: Mario Six <mario.six@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de> |
#
c4195d55 |
|
09-May-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: a38x: move sys_env_device_rev_get Move sys_env_device_rev_get() from the ddr training code to sys_env_lib.c (which currently resides with the serdes code). This brings sys_env_device_rev_get() into line with sys_env_device_id_get() and sys_env_model_get(). Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
544acb07 |
|
23-Oct-2015 |
Kevin Smith <kevin.smith@elecsyscorp.com> |
arm: mvebu: a38x: Remove unsupported topologies A lot of extra configuration information was left over in the Marvell serdes and DDR3 initialization code for boards that U-boot does not support. Remove this extra config information, and the concept of fixing up board topologies with information loaded from an EEPROM. If this needs to be done, it should be handled in the board file, not in core code. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Luka Perkov <luka.perkov@sartura.hr> |
#
edb47025 |
|
20-Apr-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: Add Armada 38x SERDES / PHY init code from Marvell bin_hdr This code is ported from the Marvell bin_hdr code into mainline SPL U-Boot. It needs to be executed very early so that the devices connected to the serdes PHY are configured correctly. Signed-off-by: Stefan Roese <sr@denx.de> |
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
ad91fdff |
|
25-Feb-2020 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
d997ad03 |
|
27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
|
#
cc66ebde |
|
10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
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d997ad03 |
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27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
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cc66ebde |
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10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
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d997ad03 |
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27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
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cc66ebde |
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10-Jul-2019 |
Baruch Siach <baruch@tkos.co.il> |
arm: mvebu: set 38x and 39x AVS on lower frequency Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
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d997ad03 |
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27-Nov-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: add revision id for Armada-385 B0 Marvell have release a B0 revision of the Armada-385 SoC. This fixes a hardware errata enabling RGMII to work when the Ethernet voltage is configured to 3.3V. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
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28be54dc |
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27-May-2018 |
Rabeeh Khoury <rabeeh@solid-run.com> |
mvebu: a38x: Force receiver detected on PCIe lanes Some QCA988x based modules presence is not detected by the SERDES lanes, so force this detection which will trigger the LTSSM state machine to negotiate link. An example of such a card is WLE900VX. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Tested-by: Chris Packham <judge.packham@gmail.com> Tested-by: Mario Six <mario.six@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
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c4195d55 |
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09-May-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: a38x: move sys_env_device_rev_get Move sys_env_device_rev_get() from the ddr training code to sys_env_lib.c (which currently resides with the serdes code). This brings sys_env_device_rev_get() into line with sys_env_device_id_get() and sys_env_model_get(). Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
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83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
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544acb07 |
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23-Oct-2015 |
Kevin Smith <kevin.smith@elecsyscorp.com> |
arm: mvebu: a38x: Remove unsupported topologies A lot of extra configuration information was left over in the Marvell serdes and DDR3 initialization code for boards that U-boot does not support. Remove this extra config information, and the concept of fixing up board topologies with information loaded from an EEPROM. If this needs to be done, it should be handled in the board file, not in core code. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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edb47025 |
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20-Apr-2015 |
Stefan Roese <sr@denx.de> |
arm: mvebu: Add Armada 38x SERDES / PHY init code from Marvell bin_hdr This code is ported from the Marvell bin_hdr code into mainline SPL U-Boot. It needs to be executed very early so that the devices connected to the serdes PHY are configured correctly. Signed-off-by: Stefan Roese <sr@denx.de>
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