1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * LPC32xx dram init 4 * 5 * (C) Copyright 2014 DENX Software Engineering GmbH 6 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> 7 * 8 * This is called by SPL to gain access to the SDR DRAM. 9 * 10 * This code runs from SRAM. 11 */ 12 13#include <common.h> 14#include <netdev.h> 15#include <asm/arch/cpu.h> 16#include <asm/arch/clk.h> 17#include <asm/arch/wdt.h> 18#include <asm/arch/emc.h> 19#include <asm/io.h> 20#include <linux/delay.h> 21 22static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; 23static struct emc_regs *emc = (struct emc_regs *)EMC_BASE; 24 25void ddr_init(struct emc_dram_settings *dram) 26{ 27 uint32_t ck; 28 29 /* Enable EMC interface and choose little endian mode */ 30 writel(1, &emc->ctrl); 31 writel(0, &emc->config); 32 /* Select maximum EMC Dynamic Memory Refresh Time */ 33 writel(0x7FF, &emc->refresh); 34 /* Determine CLK */ 35 ck = get_sdram_clk_rate(); 36 /* Configure SDRAM */ 37 writel(dram->cmddelay, &clk->sdramclk_ctrl); 38 writel(dram->config0, &emc->config0); 39 writel(dram->rascas0, &emc->rascas0); 40 writel(dram->rdconfig, &emc->read_config); 41 /* Set timings */ 42 writel((ck / dram->trp) & 0x0000000F, &emc->t_rp); 43 writel((ck / dram->tras) & 0x0000000F, &emc->t_ras); 44 writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex); 45 writel((ck / dram->twr) & 0x0000000F, &emc->t_wr); 46 writel((ck / dram->trc) & 0x0000001F, &emc->t_rc); 47 writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc); 48 writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr); 49 writel(dram->trrd, &emc->t_rrd); 50 writel(dram->tmrd, &emc->t_mrd); 51 writel(dram->tcdlr, &emc->t_cdlr); 52 /* Dynamic refresh */ 53 writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); 54 udelay(10); 55 /* Force all clocks, enable inverted ck, issue NOP command */ 56 writel(0x00000193, &emc->control); 57 udelay(100); 58 /* Keep all clocks enabled, issue a PRECHARGE ALL command */ 59 writel(0x00000113, &emc->control); 60 /* Fast dynamic refresh for at least a few SDRAM ck cycles */ 61 writel((((128) >> 4) & 0x7FF), &emc->refresh); 62 udelay(10); 63 /* set correct dynamic refresh timing */ 64 writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); 65 udelay(10); 66 /* set normal mode to CAS=3 */ 67 writel(0x00000093, &emc->control); 68 readl(EMC_DYCS0_BASE | dram->mode); 69 /* set extended mode to all zeroes */ 70 writel(0x00000093, &emc->control); 71 readl(EMC_DYCS0_BASE | dram->emode); 72 /* stop forcing clocks, keep inverted clock, issue normal mode */ 73 writel(0x00000010, &emc->control); 74} 75