1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com>
4 */
5
6#include <common.h>
7#include <cpu_func.h>
8#include <init.h>
9#include <net.h>
10#include <netdev.h>
11#include <asm/arch/cpu.h>
12#include <asm/arch/clk.h>
13#include <asm/arch/wdt.h>
14#include <asm/arch/sys_proto.h>
15#include <asm/io.h>
16
17static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
18static struct wdt_regs  *wdt = (struct wdt_regs *)WDT_BASE;
19
20void reset_cpu(void)
21{
22	/* Enable watchdog clock */
23	setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
24
25	/* Reset pulse length is 13005 peripheral clock frames */
26	writel(13000, &wdt->pulse);
27
28	/* Force WDOG_RESET2 and RESOUT_N signal active */
29	writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,
30	       &wdt->mctrl);
31
32	while (1)
33		/* NOP */;
34}
35
36#if defined(CONFIG_ARCH_CPU_INIT)
37int arch_cpu_init(void)
38{
39	/*
40	 * It might be necessary to flush data cache, if U-Boot is loaded
41	 * from kickstart bootloader, e.g. from S1L loader
42	 */
43	flush_dcache_all();
44
45	return 0;
46}
47#else
48#error "You have to select CONFIG_ARCH_CPU_INIT"
49#endif
50
51#if defined(CONFIG_DISPLAY_CPUINFO)
52int print_cpuinfo(void)
53{
54	printf("CPU:   NXP LPC32XX\n");
55	printf("CPU clock:        %uMHz\n", get_hclk_pll_rate() / 1000000);
56	printf("AHB bus clock:    %uMHz\n", get_hclk_clk_rate() / 1000000);
57	printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
58
59	return 0;
60}
61#endif
62