1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * K3: AM62A SoC definitions, structures etc.
4 *
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8#ifndef __ASM_ARCH_AM62A_HARDWARE_H
9#define __ASM_ARCH_AM62A_HARDWARE_H
10
11#include <config.h>
12#ifndef __ASSEMBLY__
13#include <linux/bitops.h>
14#endif
15
16#define PADCFG_MMR0_BASE			0x04080000
17#define PADCFG_MMR1_BASE			0x000f0000
18#define CTRL_MMR0_BASE				0x00100000
19#define MCU_CTRL_MMR0_BASE			0x04500000
20#define WKUP_CTRL_MMR0_BASE			0x43000000
21
22#define CTRLMMR_MAIN_DEVSTAT			(WKUP_CTRL_MMR0_BASE + 0x30)
23#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK	GENMASK(6, 3)
24#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT	3
25#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK	GENMASK(9, 7)
26#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT	7
27#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK	GENMASK(12, 10)
28#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT	10
29#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK	BIT(13)
30#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT	13
31
32/* Primary Bootmode MMC Config macros */
33#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK	0x4
34#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT	2
35#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK	0x1
36#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT	0
37
38/* Primary Bootmode USB Config macros */
39#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT	1
40#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK	0x02
41
42/* Backup Bootmode USB Config macros */
43#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK	0x01
44
45/*
46 * The CTRL_MMR0 memory space is divided into several equally-spaced
47 * partitions, so defining the partition size allows us to determine
48 * register addresses common to those partitions.
49 */
50#define CTRL_MMR0_PARTITION_SIZE		0x4000
51
52/*
53 * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism
54 * shared register definitions. The same registers are also used for
55 * PADCFG_MMR lock/kick-mechanism.
56 */
57#define CTRLMMR_LOCK_KICK0			0x1008
58#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL		0x68ef3490
59#define CTRLMMR_LOCK_KICK1			0x100c
60#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL		0xd172bc5a
61
62#define MCU_CTRL_LFXOSC_CTRL			(MCU_CTRL_MMR0_BASE + 0x8038)
63#define MCU_CTRL_LFXOSC_TRIM			(MCU_CTRL_MMR0_BASE + 0x803c)
64#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL		BIT(7)
65
66#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL		(MCU_CTRL_MMR0_BASE + 0x8058)
67#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL	(0x3)
68
69#define ROM_EXTENDED_BOOT_DATA_INFO		0x43c3f1e0
70
71#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM         0x7000F290
72
73/*
74 * During the boot process ROM will kill anything that writes to OCSRAM.
75 * This means the wakeup SPL cannot use this region during boot. To
76 * complicate things, TIFS will set a firewall between HSM RAM and the
77 * main domain.
78 *
79 * So, during the wakeup SPL, we will need to store the EEPROM data
80 * somewhere in HSM RAM, and the main domain's SPL will need to store it
81 * somewhere in OCSRAM
82 */
83#ifdef CONFIG_CPU_V7R
84#define TI_SRAM_SCRATCH_BOARD_EEPROM_START	0x43c30000
85#else
86#define TI_SRAM_SCRATCH_BOARD_EEPROM_START	0x70000001
87#endif /* CONFIG_CPU_V7R */
88
89#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
90
91static const u32 put_device_ids[] = {};
92
93static const u32 put_core_ids[] = {};
94
95#endif
96
97#endif /* __ASM_ARCH_AM62A_HARDWARE_H */
98