1// SPDX-License-Identifier: GPL-2.0 2/* 3 * AM625: SoC specific initialization 4 * 5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ 6 * Suman Anna <s-anna@ti.com> 7 */ 8 9#include <spl.h> 10#include <asm/io.h> 11#include <asm/arch/hardware.h> 12#include "sysfw-loader.h" 13#include "common.h" 14#include <dm.h> 15#include <dm/uclass-internal.h> 16#include <dm/pinctrl.h> 17#include <dm/ofnode.h> 18 19#define RTC_BASE_ADDRESS 0x2b1f0000 20#define REG_K3RTC_S_CNT_LSW (RTC_BASE_ADDRESS + 0x18) 21#define REG_K3RTC_KICK0 (RTC_BASE_ADDRESS + 0x70) 22#define REG_K3RTC_KICK1 (RTC_BASE_ADDRESS + 0x74) 23 24/* Magic values for lock/unlock */ 25#define K3RTC_KICK0_UNLOCK_VALUE 0x83e70b13 26#define K3RTC_KICK1_UNLOCK_VALUE 0x95a4f1e0 27 28/* TISCI DEV ID for A53 Clock */ 29#define AM62X_DEV_A53SS0_CORE_0_DEV_ID 135 30 31/* 32 * This uninitialized global variable would normal end up in the .bss section, 33 * but the .bss is cleared between writing and reading this variable, so move 34 * it to the .data section. 35 */ 36u32 bootindex __section(".data"); 37static struct rom_extended_boot_data bootdata __section(".data"); 38 39static void store_boot_info_from_rom(void) 40{ 41 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); 42 memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO, 43 sizeof(struct rom_extended_boot_data)); 44} 45 46static void ctrl_mmr_unlock(void) 47{ 48 /* Unlock all WKUP_CTRL_MMR0 module registers */ 49 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0); 50 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1); 51 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2); 52 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3); 53 mmr_unlock(WKUP_CTRL_MMR0_BASE, 4); 54 mmr_unlock(WKUP_CTRL_MMR0_BASE, 5); 55 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6); 56 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7); 57 58 /* Unlock all CTRL_MMR0 module registers */ 59 mmr_unlock(CTRL_MMR0_BASE, 0); 60 mmr_unlock(CTRL_MMR0_BASE, 1); 61 mmr_unlock(CTRL_MMR0_BASE, 2); 62 mmr_unlock(CTRL_MMR0_BASE, 4); 63 mmr_unlock(CTRL_MMR0_BASE, 6); 64 65 /* Unlock all MCU_CTRL_MMR0 module registers */ 66 mmr_unlock(MCU_CTRL_MMR0_BASE, 0); 67 mmr_unlock(MCU_CTRL_MMR0_BASE, 1); 68 mmr_unlock(MCU_CTRL_MMR0_BASE, 2); 69 mmr_unlock(MCU_CTRL_MMR0_BASE, 3); 70 mmr_unlock(MCU_CTRL_MMR0_BASE, 4); 71 mmr_unlock(MCU_CTRL_MMR0_BASE, 6); 72 73 /* Unlock PADCFG_CTRL_MMR padconf registers */ 74 mmr_unlock(PADCFG_MMR0_BASE, 1); 75 mmr_unlock(PADCFG_MMR1_BASE, 1); 76} 77 78static __maybe_unused void enable_mcu_esm_reset(void) 79{ 80 /* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z to '0' (low active) */ 81 u32 stat = readl(CTRLMMR_MCU_RST_CTRL); 82 83 stat &= RST_CTRL_ESM_ERROR_RST_EN_Z_MASK; 84 writel(stat, CTRLMMR_MCU_RST_CTRL); 85} 86 87/* 88 * RTC Erratum i2327 Workaround for Silicon Revision 1 89 * 90 * Due to a bug in initial synchronization out of cold power on, 91 * IRQ status can get locked infinitely if we do not unlock RTC 92 * 93 * This workaround *must* be applied within 1 second of power on, 94 * So, this is closest point to be able to guarantee the max 95 * timing. 96 * 97 * https://www.ti.com/lit/er/sprz487c/sprz487c.pdf 98 */ 99static __maybe_unused void rtc_erratumi2327_init(void) 100{ 101 u32 counter; 102 103 /* 104 * If counter has gone past 1, nothing we can do, leave 105 * system locked! This is the only way we know if RTC 106 * can be used for all practical purposes. 107 */ 108 counter = readl(REG_K3RTC_S_CNT_LSW); 109 if (counter > 1) 110 return; 111 /* 112 * Need to set this up at the very start 113 * MUST BE DONE under 1 second of boot. 114 */ 115 writel(K3RTC_KICK0_UNLOCK_VALUE, REG_K3RTC_KICK0); 116 writel(K3RTC_KICK1_UNLOCK_VALUE, REG_K3RTC_KICK1); 117} 118 119#if CONFIG_IS_ENABLED(OF_CONTROL) 120static int get_a53_cpu_clock_index(ofnode node) 121{ 122 int count, i; 123 struct ofnode_phandle_args *args; 124 ofnode clknode; 125 126 clknode = ofnode_path("/bus@f0000/system-controller@44043000/clock-controller"); 127 if (!ofnode_valid(clknode)) 128 return -1; 129 130 count = ofnode_count_phandle_with_args(node, "assigned-clocks", "#clock-cells", 0); 131 132 for (i = 0; i < count; i++) { 133 if (!ofnode_parse_phandle_with_args(node, "assigned-clocks", 134 "#clock-cells", 0, i, args)) { 135 if (ofnode_equal(clknode, args->node) && 136 args->args[0] == AM62X_DEV_A53SS0_CORE_0_DEV_ID) 137 return i; 138 } 139 } 140 141 return -1; 142} 143 144static void fixup_a53_cpu_freq_by_speed_grade(void) 145{ 146 int index, size; 147 u32 *rates; 148 ofnode node; 149 150 node = ofnode_path("/a53@0"); 151 if (!ofnode_valid(node)) 152 return; 153 154 rates = fdt_getprop_w(ofnode_to_fdt(node), ofnode_to_offset(node), 155 "assigned-clock-rates", &size); 156 157 index = get_a53_cpu_clock_index(node); 158 159 if (!rates || index < 0 || index >= (size / sizeof(u32))) { 160 printf("Wrong A53 assigned-clocks configuration\n"); 161 return; 162 } 163 164 rates[index] = cpu_to_fdt32(k3_get_a53_max_frequency()); 165 166 printf("Changed A53 CPU frequency to %dHz (%c grade) in DT\n", 167 k3_get_a53_max_frequency(), k3_get_speed_grade()); 168} 169#else 170static void fixup_a53_cpu_freq_by_speed_grade(void) 171{ 172} 173#endif 174 175void board_init_f(ulong dummy) 176{ 177 struct udevice *dev; 178 int ret; 179 180 if (IS_ENABLED(CONFIG_CPU_V7R)) { 181 setup_k3_mpu_regions(); 182 rtc_erratumi2327_init(); 183 } 184 185 /* 186 * Cannot delay this further as there is a chance that 187 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section. 188 */ 189 store_boot_info_from_rom(); 190 191 ctrl_mmr_unlock(); 192 193 /* Init DM early */ 194 spl_early_init(); 195 196 /* 197 * Process pinctrl for the serial0 and serial3, aka WKUP_UART0 and 198 * MAIN_UART1 modules and continue regardless of the result of pinctrl. 199 * Do this without probing the device, but instead by searching the 200 * device that would request the given sequence number if probed. The 201 * UARTs will be used by the DM firmware and TIFS firmware images 202 * respectively and the firmware depend on SPL to initialize the pin 203 * settings. 204 */ 205 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev); 206 if (!ret) 207 pinctrl_select_state(dev, "default"); 208 209 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev); 210 if (!ret) 211 pinctrl_select_state(dev, "default"); 212 213 preloader_console_init(); 214 215 /* 216 * Allow establishing an early console as required for example when 217 * doing a UART-based boot. Note that this console may not "survive" 218 * through a SYSFW PM-init step and will need a re-init in some way 219 * due to changing module clock frequencies. 220 */ 221 if (IS_ENABLED(CONFIG_K3_EARLY_CONS)) 222 early_console_init(); 223 224 /* 225 * Configure and start up system controller firmware. Provide 226 * the U-Boot console init function to the SYSFW post-PM configuration 227 * callback hook, effectively switching on (or over) the console 228 * output. 229 */ 230 if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) { 231 ret = is_rom_loaded_sysfw(&bootdata); 232 if (!ret) 233 panic("ROM has not loaded TIFS firmware\n"); 234 235 k3_sysfw_loader(true, NULL, NULL); 236 } 237 238 /* 239 * Relocate boot information to OCRAM (after TIFS has opend this 240 * region for us) so the next bootloader stages can keep access to 241 * primary vs backup bootmodes. 242 */ 243 if (IS_ENABLED(CONFIG_CPU_V7R)) 244 writel(bootindex, K3_BOOT_PARAM_TABLE_INDEX_OCRAM); 245 246 /* 247 * Force probe of clk_k3 driver here to ensure basic default clock 248 * configuration is always done. 249 */ 250 if (IS_ENABLED(CONFIG_SPL_CLK_K3)) { 251 ret = uclass_get_device_by_driver(UCLASS_CLK, 252 DM_DRIVER_GET(ti_clk), 253 &dev); 254 if (ret) 255 printf("Failed to initialize clk-k3!\n"); 256 } 257 258 /* Output System Firmware version info */ 259 k3_sysfw_print_ver(); 260 261 if (IS_ENABLED(CONFIG_ESM_K3)) { 262 /* Probe/configure ESM0 */ 263 ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev); 264 if (ret) 265 printf("esm main init failed: %d\n", ret); 266 267 /* Probe/configure MCUESM */ 268 ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev); 269 if (ret) 270 printf("esm mcu init failed: %d\n", ret); 271 272 enable_mcu_esm_reset(); 273 } 274 275 if (IS_ENABLED(CONFIG_K3_AM64_DDRSS)) { 276 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 277 if (ret) 278 panic("DRAM init failed: %d\n", ret); 279 } 280 spl_enable_cache(); 281 282 fixup_a53_cpu_freq_by_speed_grade(); 283} 284 285u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) 286{ 287 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); 288 u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> 289 MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; 290 u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> 291 MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; 292 293 switch (bootmode) { 294 case BOOT_DEVICE_EMMC: 295 if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) 296 return MMCSD_MODE_EMMCBOOT; 297 if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4)) 298 return MMCSD_MODE_FS; 299 return MMCSD_MODE_EMMCBOOT; 300 case BOOT_DEVICE_MMC: 301 if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK) 302 return MMCSD_MODE_RAW; 303 default: 304 return MMCSD_MODE_FS; 305 } 306} 307 308u32 spl_boot_device(void) 309{ 310 return get_boot_device(); 311} 312