1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Based on the iomux-v3.c from Linux kernel:
4 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
5 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
6 *                       <armlinux@phytec.de>
7 *
8 * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
9 */
10#include <asm/io.h>
11#include <asm/arch/imx-regs.h>
12#include <asm/mach-imx/iomux-v3.h>
13#include <asm/mach-imx/sys_proto.h>
14
15static void *base = (void *)IOMUXC_BASE_ADDR;
16
17/*
18 * configures a single pad in the iomuxer
19 */
20void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
21{
22	u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
23	u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
24	u32 sel_input_ofs =
25		(pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
26	u32 sel_input =
27		(pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
28	u32 pad_ctrl_ofs =
29		(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
30	u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
31
32#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
33	/* Check whether LVE bit needs to be set */
34	if (pad_ctrl & PAD_CTL_LVE) {
35		pad_ctrl &= ~PAD_CTL_LVE;
36		pad_ctrl |= PAD_CTL_LVE_BIT;
37	}
38#endif
39
40#ifdef CONFIG_IOMUX_LPSR
41	u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT;
42
43#ifdef CONFIG_MX7
44	if (lpsr == IOMUX_CONFIG_LPSR) {
45		base = (void *)IOMUXC_LPSR_BASE_ADDR;
46		mux_mode &= ~IOMUX_CONFIG_LPSR;
47		/* set daisy chain sel_input */
48		if (sel_input_ofs)
49			sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
50	}
51#else
52	if (is_mx6ull() || is_mx6sll()) {
53		if (lpsr == IOMUX_CONFIG_LPSR) {
54			base = (void *)IOMUXC_SNVS_BASE_ADDR;
55			mux_mode &= ~IOMUX_CONFIG_LPSR;
56		}
57	}
58#endif
59#endif
60
61	if (is_mx7() || is_mx6ull() || is_mx6sll() || mux_ctrl_ofs)
62		__raw_writel(mux_mode, base + mux_ctrl_ofs);
63
64	if (sel_input_ofs)
65		__raw_writel(sel_input, base + sel_input_ofs);
66
67#ifdef CONFIG_IOMUX_SHARE_CONF_REG
68	if (!(pad_ctrl & NO_PAD_CTRL))
69		__raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
70			base + pad_ctrl_ofs);
71#else
72	if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
73		__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
74#if defined(CONFIG_MX6SLL)
75	else if ((pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
76		clrbits_le32(base + pad_ctrl_ofs, PAD_CTL_IPD_BIT);
77#endif
78#endif
79
80#ifdef CONFIG_IOMUX_LPSR
81	if (lpsr == IOMUX_CONFIG_LPSR)
82		base = (void *)IOMUXC_BASE_ADDR;
83#endif
84
85}
86
87/* configures a list of pads within declared with IOMUX_PADS macro */
88void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
89				      unsigned count)
90{
91	iomux_v3_cfg_t const *p = pad_list;
92	int stride;
93	int i;
94
95#if defined(CONFIG_MX6QDL)
96	stride = 2;
97	if (!is_mx6dq() && !is_mx6dqp())
98		p += 1;
99#else
100	stride = 1;
101#endif
102	for (i = 0; i < count; i++) {
103		imx_iomux_v3_setup_pad(*p);
104		p += stride;
105	}
106}
107
108void imx_iomux_set_gpr_register(int group, int start_bit,
109					int num_bits, int value)
110{
111	int i = 0;
112	u32 reg;
113	reg = readl(base + group * 4);
114	while (num_bits) {
115		reg &= ~(1<<(start_bit + i));
116		i++;
117		num_bits--;
118	}
119	reg |= (value << start_bit);
120	writel(reg, base + group * 4);
121}
122
123#ifdef CONFIG_IOMUX_SHARE_CONF_REG
124void imx_iomux_gpio_set_direction(unsigned int gpio,
125				unsigned int direction)
126{
127	u32 reg;
128	/*
129	 * Only on Vybrid the input/output buffer enable flags
130	 * are part of the shared mux/conf register.
131	 */
132	reg = readl(base + (gpio << 2));
133
134	if (direction)
135		reg |= 0x2;
136	else
137		reg &= ~0x2;
138
139	writel(reg, base + (gpio << 2));
140}
141
142void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state)
143{
144	*gpio_state = readl(base + (gpio << 2)) &
145		((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE);
146}
147#endif
148