1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Samsung Electronics 4 * Thomas Abraham <thomas.ab@samsung.com> 5 */ 6 7#include <common.h> 8#include <asm/armv8/mmu.h> 9#include <linux/sizes.h> 10 11#if IS_ENABLED(CONFIG_EXYNOS7420) 12 13static struct mm_region exynos7420_mem_map[] = { 14 { 15 .virt = 0x10000000UL, 16 .phys = 0x10000000UL, 17 .size = 0x10000000UL, 18 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 19 PTE_BLOCK_NON_SHARE | 20 PTE_BLOCK_PXN | PTE_BLOCK_UXN, 21 }, { 22 .virt = 0x40000000UL, 23 .phys = 0x40000000UL, 24 .size = 0x80000000UL, 25 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 26 PTE_BLOCK_INNER_SHARE, 27 }, { 28 /* List terminator */ 29 }, 30}; 31 32struct mm_region *mem_map = exynos7420_mem_map; 33 34#elif CONFIG_IS_ENABLED(EXYNOS7870) 35 36static struct mm_region exynos7870_mem_map[] = { 37 { 38 .virt = 0x10000000UL, 39 .phys = 0x10000000UL, 40 .size = 0x10000000UL, 41 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 42 PTE_BLOCK_NON_SHARE | 43 PTE_BLOCK_PXN | PTE_BLOCK_UXN, 44 }, 45 { 46 .virt = 0x40000000UL, 47 .phys = 0x40000000UL, 48 .size = 0x3E400000UL, 49 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 50 PTE_BLOCK_INNER_SHARE, 51 }, 52 { 53 .virt = 0x80000000UL, 54 .phys = 0x80000000UL, 55 .size = 0x40000000UL, 56 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 57 PTE_BLOCK_INNER_SHARE, 58 }, 59 60 { 61 /* List terminator */ 62 }, 63}; 64 65struct mm_region *mem_map = exynos7870_mem_map; 66 67#elif CONFIG_IS_ENABLED(EXYNOS7880) 68 69static struct mm_region exynos7880_mem_map[] = { 70 { 71 .virt = 0x10000000UL, 72 .phys = 0x10000000UL, 73 .size = 0x10000000UL, 74 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 75 PTE_BLOCK_NON_SHARE | 76 PTE_BLOCK_PXN | PTE_BLOCK_UXN, 77 }, 78 { 79 .virt = 0x40000000UL, 80 .phys = 0x40000000UL, 81 .size = 0x3E400000UL, 82 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 83 PTE_BLOCK_INNER_SHARE, 84 }, 85 { 86 .virt = 0x80000000UL, 87 .phys = 0x80000000UL, 88 .size = 0x80000000UL, 89 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 90 PTE_BLOCK_INNER_SHARE, 91 }, 92 93 { 94 /* List terminator */ 95 }, 96}; 97 98struct mm_region *mem_map = exynos7880_mem_map; 99 100#elif IS_ENABLED(CONFIG_EXYNOS850) 101 102static struct mm_region exynos850_mem_map[] = { 103 { 104 /* Peripheral block */ 105 .virt = 0x10000000UL, 106 .phys = 0x10000000UL, 107 .size = SZ_256M, 108 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 109 PTE_BLOCK_NON_SHARE | 110 PTE_BLOCK_PXN | PTE_BLOCK_UXN 111 }, { 112 /* DDR, 32-bit area */ 113 .virt = 0x80000000UL, 114 .phys = 0x80000000UL, 115 .size = SZ_2G, 116 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 117 PTE_BLOCK_INNER_SHARE 118 }, { 119 /* DDR, 64-bit area */ 120 .virt = 0x880000000UL, 121 .phys = 0x880000000UL, 122 .size = SZ_2G, 123 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 124 PTE_BLOCK_INNER_SHARE 125 }, { 126 /* List terminator */ 127 } 128}; 129 130struct mm_region *mem_map = exynos850_mem_map; 131 132#endif 133