1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Chip-specific header file for the AT91SAM9x5 family
4 *
5 *  Copyright (C) 2012-2013 Atmel Corporation.
6 *
7 * Definitions for the SoC:
8 * AT91SAM9x5 & AT91SAM9N12
9 */
10
11#ifndef __AT91SAM9X5_H__
12#define __AT91SAM9X5_H__
13
14/*
15 * Peripheral identifiers/interrupts.
16 */
17#define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
18#define ATMEL_ID_SYS	1	/* System Controller Interrupt */
19#define ATMEL_ID_PIOAB	2	/* Parallel I/O Controller A and B */
20#define ATMEL_ID_PIOCD	3	/* Parallel I/O Controller C and D */
21#define ATMEL_ID_SMD	4	/* SMD Soft Modem (SMD), only for AT91SAM9X5 */
22#define ATMEL_ID_FUSE	4	/* FUSE Controller, only for AT91SAM9N12 */
23#define ATMEL_ID_USART0	5	/* USART 0 */
24#define ATMEL_ID_USART1	6	/* USART 1 */
25#define ATMEL_ID_USART2	7	/* USART 2 */
26#define ATMEL_ID_USART3	8	/* USART 3 */
27#define ATMEL_ID_TWI0	9	/* Two-Wire Interface 0 */
28#define ATMEL_ID_TWI1	10	/* Two-Wire Interface 1 */
29#define ATMEL_ID_TWI2	11	/* Two-Wire Interface 2 */
30#define ATMEL_ID_HSMCI0	12	/* High Speed Multimedia Card Interface 0 */
31#define ATMEL_ID_SPI0	13	/* Serial Peripheral Interface 0 */
32#define ATMEL_ID_SPI1	14	/* Serial Peripheral Interface 1 */
33#define ATMEL_ID_UART0	15	/* UART 0 */
34#define ATMEL_ID_UART1	16	/* UART 1 */
35#define ATMEL_ID_TC01	17	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
36#define ATMEL_ID_PWM	18	/* Pulse Width Modulation Controller */
37#define ATMEL_ID_ADC	19	/* ADC Controller */
38#define ATMEL_ID_DMAC0	20	/* DMA Controller 0 */
39#define ATMEL_ID_DMAC1	21	/* DMA Controller 1 */
40#define ATMEL_ID_UHPHS	22	/* USB Host High Speed */
41#define ATMEL_ID_UDPHS	23	/* USB Device High Speed */
42#define ATMEL_ID_EMAC0	24	/* Ethernet MAC0 */
43#define ATMEL_ID_LCDC	25	/* LCD Controller */
44#define ATMEL_ID_HSMCI1	26	/* High Speed Multimedia Card Interface 1 */
45#define ATMEL_ID_EMAC1	27	/* Ethernet MAC1 */
46#define ATMEL_ID_SSC	28	/* Synchronous Serial Controller */
47#define ATMEL_ID_TRNG	30	/* True Random Number Generator */
48#define ATMEL_ID_IRQ	31	/* Advanced Interrupt Controller */
49
50/*
51 * User Peripheral physical base addresses.
52 */
53#define ATMEL_BASE_SPI0		0xf0000000
54#define ATMEL_BASE_SPI1		0xf0004000
55#define ATMEL_BASE_HSMCI0	0xf0008000
56#define ATMEL_BASE_HSMCI1	0xf000c000
57#define ATMEL_BASE_SSC		0xf0010000
58#define ATMEL_BASE_CAN0		0xf8000000
59#define ATMEL_BASE_CAN1		0xf8004000
60#define ATMEL_BASE_TC0		0xf8008000
61#define ATMEL_BASE_TC1		0xf8008040
62#define ATMEL_BASE_TC2		0xf8008080
63#define ATMEL_BASE_TC3		0xf800c000
64#define ATMEL_BASE_TC4		0xf800c040
65#define ATMEL_BASE_TC5		0xf800c080
66#define ATMEL_BASE_TWI0		0xf8010000
67#define ATMEL_BASE_TWI1		0xf8014000
68#define ATMEL_BASE_TWI2		0xf8018000
69#define ATMEL_BASE_USART0	0xf801c000
70#define ATMEL_BASE_USART1	0xf8020000
71#define ATMEL_BASE_USART2	0xf8024000
72#define ATMEL_BASE_USART3	0xf8028000
73#define ATMEL_BASE_EMAC0	0xf802c000
74#define ATMEL_BASE_EMAC1	0xf8030000
75#define ATMEL_BASE_PWM		0xf8034000
76#define ATMEL_BASE_LCDC		0xf8038000
77#define ATMEL_BASE_UDPHS	0xf803c000
78#define ATMEL_BASE_UART0	0xf8040000
79#define ATMEL_BASE_UART1	0xf8044000
80#define ATMEL_BASE_ISI		0xf8048000
81#define ATMEL_BASE_ADC		0xf804c000
82#define ATMEL_BASE_SYS		0xffffc000
83
84/*
85 * System Peripherals
86 */
87#define ATMEL_BASE_FUSE		0xffffdc00
88#define ATMEL_BASE_MATRIX	0xffffde00
89#define ATMEL_BASE_PMECC	0xffffe000
90#define ATMEL_BASE_PMERRLOC	0xffffe600
91#define ATMEL_BASE_DDRSDRC	0xffffe800
92#define ATMEL_BASE_SMC		0xffffea00
93#define ATMEL_BASE_DMAC0	0xffffec00
94#define ATMEL_BASE_DMAC1	0xffffee00
95#define ATMEL_BASE_AIC		0xfffff000
96#define ATMEL_BASE_DBGU		0xfffff200
97#define ATMEL_BASE_PIOA		0xfffff400
98#define ATMEL_BASE_PIOB		0xfffff600
99#define ATMEL_BASE_PIOC		0xfffff800
100#define ATMEL_BASE_PIOD		0xfffffa00
101#define ATMEL_BASE_PMC		0xfffffc00
102#define ATMEL_BASE_RSTC		0xfffffe00
103#define ATMEL_BASE_SHDWC	0xfffffe10
104#define ATMEL_BASE_PIT		0xfffffe30
105#define ATMEL_BASE_WDT		0xfffffe40
106#define ATMEL_BASE_GPBR		0xfffffe60
107#define ATMEL_BASE_RTC		0xfffffeb0
108
109/*
110 * Internal Memory.
111 */
112#define ATMEL_BASE_ROM		0x00100000 /* Internal ROM base address */
113#define ATMEL_BASE_SRAM		0x00300000 /* Internal SRAM base address */
114
115#ifdef CONFIG_AT91SAM9N12
116#define ATMEL_BASE_OHCI		0x00500000 /* USB Host controller */
117#else	/* AT91SAM9X5 */
118#define ATMEL_BASE_SMD		0x00400000 /* SMD Controller */
119#define ATMEL_BASE_UDPHS_FIFO	0x00500000 /* USB Device HS controller */
120#define ATMEL_BASE_OHCI		0x00600000 /* USB Host controller (OHCI) */
121#define ATMEL_BASE_EHCI		0x00700000 /* USB Host controller (EHCI) */
122#endif
123
124/*
125 * External memory
126 */
127#define ATMEL_BASE_CS0		0x10000000
128#define ATMEL_BASE_CS1		0x20000000
129#define ATMEL_BASE_CS2		0x30000000
130#define ATMEL_BASE_CS3		0x40000000
131#define ATMEL_BASE_CS4		0x50000000
132#define ATMEL_BASE_CS5		0x60000000
133
134/* 9x5 series chip id definitions */
135#define ARCH_ID_AT91SAM9X5	0x819a05a0
136#define ARCH_ID_VERSION_MASK	0x1f
137#define ARCH_EXID_AT91SAM9G15	0x00000000
138#define ARCH_EXID_AT91SAM9G35	0x00000001
139#define ARCH_EXID_AT91SAM9X35	0x00000002
140#define ARCH_EXID_AT91SAM9G25	0x00000003
141#define ARCH_EXID_AT91SAM9X25	0x00000004
142
143#define cpu_is_at91sam9x5()	(get_chip_id() == ARCH_ID_AT91SAM9X5)
144#define cpu_is_at91sam9g15()	(cpu_is_at91sam9x5() && \
145			(get_extension_chip_id() == ARCH_EXID_AT91SAM9G15))
146#define cpu_is_at91sam9g25()	(cpu_is_at91sam9x5() && \
147			(get_extension_chip_id() == ARCH_EXID_AT91SAM9G25))
148#define cpu_is_at91sam9g35()	(cpu_is_at91sam9x5() && \
149			(get_extension_chip_id() == ARCH_EXID_AT91SAM9G35))
150#define cpu_is_at91sam9x25()	(cpu_is_at91sam9x5() && \
151			(get_extension_chip_id() == ARCH_EXID_AT91SAM9X25))
152#define cpu_is_at91sam9x35()	(cpu_is_at91sam9x5() && \
153			(get_extension_chip_id() == ARCH_EXID_AT91SAM9X35))
154
155/*
156 * Cpu Name
157 */
158#ifdef CONFIG_AT91SAM9N12
159#define ATMEL_CPU_NAME	"AT91SAM9N12"
160#else	/* AT91SAM9X5 */
161#define ATMEL_CPU_NAME	get_cpu_name()
162#endif
163
164/* Timer */
165#define CFG_SYS_TIMER_COUNTER	0xfffffe3c
166
167/*
168 * Other misc defines
169 */
170#define ATMEL_PIO_PORTS         4
171#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
172#define ATMEL_ID_UHP		ATMEL_ID_UHPHS
173
174/*
175 * PMECC table in ROM
176 */
177#define ATMEL_PMECC_INDEX_OFFSET_512	0x8000
178#define ATMEL_PMECC_INDEX_OFFSET_1024	0x10000
179
180/*
181 * at91sam9x5 specific prototypes
182 */
183#ifndef __ASSEMBLY__
184unsigned int get_chip_id(void);
185unsigned int get_extension_chip_id(void);
186unsigned int has_emac1(void);
187unsigned int has_emac0(void);
188unsigned int has_lcdc(void);
189char *get_cpu_name(void);
190#endif
191
192#endif
193