1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Multicore Navigator definitions
4 *
5 * (C) Copyright 2012-2014
6 *     Texas Instruments Incorporated, <www.ti.com>
7 */
8
9#ifndef _KEYSTONE_NAV_H_
10#define _KEYSTONE_NAV_H_
11
12#include <asm/arch/hardware.h>
13#include <asm/io.h>
14
15#define QM_OK                    0
16#define QM_ERR                  -1
17#define QM_DESC_TYPE_HOST        0
18#define QM_DESC_PSINFO_IN_DESCR  0
19#define QM_DESC_DEFAULT_DESCINFO    (QM_DESC_TYPE_HOST << 30) | \
20					(QM_DESC_PSINFO_IN_DESCR << 22)
21
22/* Packet Info */
23#define QM_DESC_PINFO_EPIB              1
24#define QM_DESC_PINFO_RETURN_OWN        1
25#define QM_DESC_DEFAULT_PINFO           (QM_DESC_PINFO_EPIB << 31) | \
26					(QM_DESC_PINFO_RETURN_OWN << 15)
27
28struct qm_cfg_reg {
29	u32	revision;
30	u32	__pad1;
31	u32	divert;
32	u32	link_ram_base0;
33	u32	link_ram_size0;
34	u32	link_ram_base1;
35	u32	link_ram_size1;
36	u32	link_ram_base2;
37	u32	starvation[0];
38};
39
40struct	descr_mem_setup_reg {
41	u32	base_addr;
42	u32	start_idx;
43	u32	desc_reg_size;
44	u32	_res0;
45};
46
47struct qm_reg_queue {
48	u32	entry_count;
49	u32	byte_count;
50	u32	packet_size;
51	u32	ptr_size_thresh;
52};
53
54struct qm_config {
55	/* QM module addresses */
56	u32	stat_cfg;	/* status and config		*/
57	struct qm_reg_queue *queue;	/* management region	*/
58	u32	mngr_vbusm;	/* management region (VBUSM)	*/
59	u32	i_lram;		/* internal linking RAM		*/
60	struct qm_reg_queue *proxy;
61	u32	status_ram;
62	struct qm_cfg_reg *mngr_cfg;
63				/* Queue manager config region	*/
64	u32	intd_cfg;	/* QMSS INTD config region	*/
65	struct	descr_mem_setup_reg *desc_mem;
66				/* descritor memory setup region*/
67	u32	region_num;
68	u32	pdsp_cmd;	/* PDSP1 command interface	*/
69	u32	pdsp_ctl;	/* PDSP1 control registers	*/
70	u32	pdsp_iram;
71	/* QM configuration parameters */
72
73	u32	qpool_num;	/* */
74};
75
76struct qm_host_desc {
77	u32 desc_info;
78	u32 tag_info;
79	u32 packet_info;
80	u32 buff_len;
81	u32 buff_ptr;
82	u32 next_bdptr;
83	u32 orig_buff_len;
84	u32 orig_buff_ptr;
85	u32 timestamp;
86	u32 swinfo[3];
87	u32 ps_data[20];
88};
89
90#define HDESC_NUM        256
91
92int	qm_init(void);
93void	qm_close(void);
94void	qm_push(struct qm_host_desc *hd, u32 qnum);
95struct qm_host_desc *qm_pop(u32 qnum);
96
97void	qm_buff_push(struct qm_host_desc *hd, u32 qnum,
98		     void *buff_ptr, u32 buff_len);
99
100struct	qm_host_desc *qm_pop_from_free_pool(void);
101void	queue_close(u32 qnum);
102
103/*
104 * DMA API
105 */
106#define CPDMA_REG_VAL_MAKE_RX_FLOW_A(einfo, psinfo, rxerr, desc, \
107				     psloc, sopoff, qmgr, qnum) \
108	(((einfo & 1) << 30)  | \
109	 ((psinfo & 1) << 29) | \
110	 ((rxerr & 1) << 28)  | \
111	 ((desc & 3) << 26)   | \
112	 ((psloc & 1) << 25)  | \
113	 ((sopoff & 0x1ff) << 16) | \
114	 ((qmgr & 3) << 12)   | \
115	 ((qnum & 0xfff) << 0))
116
117#define CPDMA_REG_VAL_MAKE_RX_FLOW_D(fd0qm, fd0qnum, fd1qm, fd1qnum) \
118	(((fd0qm & 3) << 28)  | \
119	 ((fd0qnum & 0xfff) << 16) | \
120	 ((fd1qm & 3) << 12)  | \
121	 ((fd1qnum & 0xfff) <<  0))
122
123#define CPDMA_CHAN_A_ENABLE ((u32)1 << 31)
124#define CPDMA_CHAN_A_TDOWN  (1 << 30)
125#define TDOWN_TIMEOUT_COUNT  100
126
127struct global_ctl_regs {
128	u32	revision;
129	u32	perf_control;
130	u32	emulation_control;
131	u32	priority_control;
132	u32	qm_base_addr[4];
133};
134
135struct tx_chan_regs {
136	u32	cfg_a;
137	u32	cfg_b;
138	u32	res[6];
139};
140
141struct rx_chan_regs {
142	u32	cfg_a;
143	u32	res[7];
144};
145
146struct rx_flow_regs {
147	u32	control;
148	u32	tags;
149	u32	tag_sel;
150	u32	fdq_sel[2];
151	u32	thresh[3];
152};
153
154struct pktdma_cfg {
155	struct global_ctl_regs	*global;
156	struct tx_chan_regs	*tx_ch;
157	u32			tx_ch_num;
158	struct rx_chan_regs	*rx_ch;
159	u32			rx_ch_num;
160	u32			*tx_sched;
161	struct rx_flow_regs	*rx_flows;
162	u32			rx_flow_num;
163
164	u32			rx_free_q;
165	u32			rx_rcv_q;
166	u32			tx_snd_q;
167
168	u32			rx_flow; /* flow that is used for RX */
169};
170
171extern struct pktdma_cfg netcp_pktdma;
172
173/*
174 * packet dma user allocates memory for rx buffers
175 * and describe it in the following structure
176 */
177struct rx_buff_desc {
178	u8	*buff_ptr;
179	u32	num_buffs;
180	u32	buff_len;
181	u32	rx_flow;
182};
183
184int ksnav_close(struct pktdma_cfg *pktdma);
185int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers);
186int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2);
187void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes);
188void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd);
189
190#endif  /* _KEYSTONE_NAV_H_ */
191