1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2010
4 * Texas Instruments, <www.ti.com>
5 * Aneesh V <aneesh@ti.com>
6 */
7#ifndef _PL310_H_
8#define _PL310_H_
9
10/* Register bit fields */
11#define PL310_AUX_CTRL_ASSOCIATIVITY_MASK	(1 << 16)
12#define L2X0_DYNAMIC_CLK_GATING_EN		(1 << 1)
13#define L2X0_STNDBY_MODE_EN			(1 << 0)
14#define L2X0_CTRL_EN				1
15#define L2X0_CTRL_OFF				0x100
16
17#define L310_SHARED_ATT_OVERRIDE_ENABLE		(1 << 22)
18#define L310_AUX_CTRL_DATA_PREFETCH_MASK	(1 << 28)
19#define L310_AUX_CTRL_INST_PREFETCH_MASK	(1 << 29)
20#define L310_LATENCY_CTRL_SETUP(n)		((n) << 0)
21#define L310_LATENCY_CTRL_RD(n)			((n) << 4)
22#define L310_LATENCY_CTRL_WR(n)			((n) << 8)
23
24#define L2X0_CACHE_ID_PART_MASK     (0xf << 6)
25#define L2X0_CACHE_ID_PART_L310     (3 << 6)
26#define L2X0_CACHE_ID_RTL_MASK          0x3f
27#define L2X0_CACHE_ID_RTL_R3P2          0x8
28
29#ifndef __ASSEMBLY__
30
31#include <linux/types.h>
32
33struct pl310_regs {
34	u32 pl310_cache_id;
35	u32 pl310_cache_type;
36	u32 pad1[62];
37	u32 pl310_ctrl;
38	u32 pl310_aux_ctrl;
39	u32 pl310_tag_latency_ctrl;
40	u32 pl310_data_latency_ctrl;
41	u32 pad2[60];
42	u32 pl310_event_cnt_ctrl;
43	u32 pl310_event_cnt1_cfg;
44	u32 pl310_event_cnt0_cfg;
45	u32 pl310_event_cnt1_val;
46	u32 pl310_event_cnt0_val;
47	u32 pl310_intr_mask;
48	u32 pl310_masked_intr_stat;
49	u32 pl310_raw_intr_stat;
50	u32 pl310_intr_clear;
51	u32 pad3[323];
52	u32 pl310_cache_sync;
53	u32 pad4[15];
54	u32 pl310_inv_line_pa;
55	u32 pad5[2];
56	u32 pl310_inv_way;
57	u32 pad6[12];
58	u32 pl310_clean_line_pa;
59	u32 pad7[1];
60	u32 pl310_clean_line_idx;
61	u32 pl310_clean_way;
62	u32 pad8[12];
63	u32 pl310_clean_inv_line_pa;
64	u32 pad9[1];
65	u32 pl310_clean_inv_line_idx;
66	u32 pl310_clean_inv_way;
67	u32 pad10[64];
68	u32 pl310_lockdown_dbase;
69	u32 pl310_lockdown_ibase;
70	u32 pad11[190];
71	u32 pl310_addr_filter_start;
72	u32 pl310_addr_filter_end;
73	u32 pad12[190];
74	u32 pl310_test_operation;
75	u32 pad13[3];
76	u32 pl310_line_data;
77	u32 pad14[7];
78	u32 pl310_line_tag;
79	u32 pad15[3];
80	u32 pl310_debug_ctrl;
81	u32 pad16[7];
82	u32 pl310_prefetch_ctrl;
83	u32 pad17[7];
84	u32 pl310_power_ctrl;
85};
86
87void pl310_inval_all(void);
88void pl310_clean_inval_all(void);
89void pl310_inval_range(u32 start, u32 end);
90void pl310_clean_inval_range(u32 start, u32 end);
91
92#endif
93
94#endif
95