1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * tegra_i2s.h - Definitions for Tegra124 I2S driver.
4 * Note, some structures (ex, CIF) are different in Tegra114.
5 *
6 * NVIDIA Tegra I2S controller
7 * Modified from dc tegra_regs.h
8 *
9 * Copyright 2018 Google LLC
10 *
11 * Copyright (c) 2011-2013, NVIDIA CORPORATION.  All rights reserved.
12 */
13
14#ifndef _TEGRA_I2S_H_
15#define _TEGRA_I2S_H_
16
17struct i2s_ctlr {
18	u32 ctrl;		/* I2S_CTRL_0, 0x00 */
19	u32 timing;		/* I2S_TIMING_0, 0x04 */
20	u32 offset;		/* I2S_OFFSET_0, 0x08 */
21	u32 ch_ctrl;		/* I2S_CH_CTRL_0, 0x0C */
22	u32 slot_ctrl;		/* I2S_SLOT_CTRL_0, 0x10 */
23	u32 cif_tx_ctrl;	/* I2S_CIF_TX_CTRL_0, 0x14 */
24	u32 cif_rx_ctrl;	/* I2S_CIF_RX_CTRL_0, 0x18 */
25	u32 flowctl;		/* I2S_FLOWCTL_0, 0x1C */
26	u32 tx_step;		/* I2S_TX_STEP_0, 0x20 */
27	u32 flow_status;	/* I2S_FLOW_STATUS_0, 0x24 */
28	u32 flow_total;		/* I2S_FLOW_TOTAL_0, 0x28 */
29	u32 flow_over;		/* I2S_FLOW_OVER_0, 0x2C */
30	u32 flow_under;		/* I2S_FLOW_UNDER_0, 0x30 */
31	u32 reserved[12];	/* RESERVED, 0x34 - 0x60 */
32	u32 slot_ctrl2;		/* I2S_SLOT_CTRL2_0, 0x64*/
33};
34
35enum {
36	I2S_CTRL_XFER_EN_TX = 1 << 31,
37	I2S_CTRL_XFER_EN_RX = 1 << 30,
38	I2S_CTRL_CG_EN = 1 << 29,
39	I2S_CTRL_SOFT_RESET = 1 << 28,
40	I2S_CTRL_TX_FLOWCTL_EN = 1 << 27,
41
42	I2S_CTRL_OBS_SEL_SHIFT = 24,
43	I2S_CTRL_OBS_SEL_MASK = 7 << I2S_CTRL_OBS_SEL_SHIFT,
44
45	I2S_FRAME_FORMAT_LRCK = 0,
46	I2S_FRAME_FORMAT_FSYNC = 1,
47
48	I2S_CTRL_FRAME_FORMAT_SHIFT = 12,
49	I2S_CTRL_FRAME_FORMAT_MASK = 7 << I2S_CTRL_FRAME_FORMAT_SHIFT,
50	I2S_CTRL_FRAME_FORMAT_LRCK = I2S_FRAME_FORMAT_LRCK <<
51				     I2S_CTRL_FRAME_FORMAT_SHIFT,
52	I2S_CTRL_FRAME_FORMAT_FSYNC = I2S_FRAME_FORMAT_FSYNC <<
53				      I2S_CTRL_FRAME_FORMAT_SHIFT,
54
55	I2S_CTRL_MASTER_ENABLE = 1 << 10,
56
57	I2S_LRCK_LEFT_LOW = 0,
58	I2S_LRCK_RIGHT_LOW = 1,
59
60	I2S_CTRL_LRCK_SHIFT = 9,
61	I2S_CTRL_LRCK_MASK = 1 << I2S_CTRL_LRCK_SHIFT,
62	I2S_CTRL_LRCK_L_LOW = I2S_LRCK_LEFT_LOW  << I2S_CTRL_LRCK_SHIFT,
63	I2S_CTRL_LRCK_R_LOW = I2S_LRCK_RIGHT_LOW << I2S_CTRL_LRCK_SHIFT,
64
65	I2S_CTRL_LPBK_ENABLE = 1 << 8,
66
67	I2S_BIT_CODE_LINEAR = 0,
68	I2S_BIT_CODE_ULAW = 1,
69	I2S_BIT_CODE_ALAW = 2,
70
71	I2S_CTRL_BIT_CODE_SHIFT = 4,
72	I2S_CTRL_BIT_CODE_MASK = 3 << I2S_CTRL_BIT_CODE_SHIFT,
73	I2S_CTRL_BIT_CODE_LINEAR = I2S_BIT_CODE_LINEAR <<
74				   I2S_CTRL_BIT_CODE_SHIFT,
75	I2S_CTRL_BIT_CODE_ULAW = I2S_BIT_CODE_ULAW << I2S_CTRL_BIT_CODE_SHIFT,
76	I2S_CTRL_BIT_CODE_ALAW = I2S_BIT_CODE_ALAW << I2S_CTRL_BIT_CODE_SHIFT,
77
78	I2S_BITS_8 = 1,
79	I2S_BITS_12 = 2,
80	I2S_BITS_16 = 3,
81	I2S_BITS_20 = 4,
82	I2S_BITS_24 = 5,
83	I2S_BITS_28 = 6,
84	I2S_BITS_32 = 7,
85
86	/* Sample container size; see {RX,TX}_MASK field in CH_CTRL below */
87	I2S_CTRL_BIT_SIZE_SHIFT = 0,
88	I2S_CTRL_BIT_SIZE_MASK = 7 << I2S_CTRL_BIT_SIZE_SHIFT,
89	I2S_CTRL_BIT_SIZE_8 = I2S_BITS_8  << I2S_CTRL_BIT_SIZE_SHIFT,
90	I2S_CTRL_BIT_SIZE_12 = I2S_BITS_12 << I2S_CTRL_BIT_SIZE_SHIFT,
91	I2S_CTRL_BIT_SIZE_16 = I2S_BITS_16 << I2S_CTRL_BIT_SIZE_SHIFT,
92	I2S_CTRL_BIT_SIZE_20 = I2S_BITS_20 << I2S_CTRL_BIT_SIZE_SHIFT,
93	I2S_CTRL_BIT_SIZE_24 = I2S_BITS_24 << I2S_CTRL_BIT_SIZE_SHIFT,
94	I2S_CTRL_BIT_SIZE_28 = I2S_BITS_28 << I2S_CTRL_BIT_SIZE_SHIFT,
95	I2S_CTRL_BIT_SIZE_32 = I2S_BITS_32 << I2S_CTRL_BIT_SIZE_SHIFT,
96
97	I2S_TIMING_NON_SYM_ENABLE = 1 << 12,
98	I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT = 0,
99	I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US = 0x7ff,
100	I2S_TIMING_CHANNEL_BIT_COUNT_MASK =
101			I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US <<
102			I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT,
103
104	I2S_OFFSET_RX_DATA_OFFSET_SHIFT = 16,
105	I2S_OFFSET_RX_DATA_OFFSET_MASK_US = 0x7ff,
106	I2S_OFFSET_RX_DATA_OFFSET_MASK = I2S_OFFSET_RX_DATA_OFFSET_MASK_US <<
107					 I2S_OFFSET_RX_DATA_OFFSET_SHIFT,
108	I2S_OFFSET_TX_DATA_OFFSET_SHIFT = 0,
109	I2S_OFFSET_TX_DATA_OFFSET_MASK_US = 0x7ff,
110	I2S_OFFSET_TX_DATA_OFFSET_MASK = I2S_OFFSET_TX_DATA_OFFSET_MASK_US <<
111					 I2S_OFFSET_TX_DATA_OFFSET_SHIFT,
112
113	/* FSYNC width - 1 in bit clocks */
114	I2S_CH_CTRL_FSYNC_WIDTH_SHIFT = 24,
115	I2S_CH_CTRL_FSYNC_WIDTH_MASK_US = 0xff,
116	I2S_CH_CTRL_FSYNC_WIDTH_MASK = I2S_CH_CTRL_FSYNC_WIDTH_MASK_US <<
117				       I2S_CH_CTRL_FSYNC_WIDTH_SHIFT,
118
119	I2S_HIGHZ_NO = 0,
120	I2S_HIGHZ_YES = 1,
121	I2S_HIGHZ_ON_HALF_BIT_CLK = 2,
122
123	I2S_CH_CTRL_HIGHZ_CTRL_SHIFT = 12,
124	I2S_CH_CTRL_HIGHZ_CTRL_MASK = 3 << I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
125	I2S_CH_CTRL_HIGHZ_CTRL_NO = I2S_HIGHZ_NO <<
126				    I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
127	I2S_CH_CTRL_HIGHZ_CTRL_YES = I2S_HIGHZ_YES <<
128				     I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
129	I2S_CH_CTRL_HIGHZ_CTRL_ON_HALF_BIT_CLK = I2S_HIGHZ_ON_HALF_BIT_CLK <<
130						 I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
131
132	I2S_MSB_FIRST = 0,
133	I2S_LSB_FIRST = 1,
134
135	I2S_CH_CTRL_RX_BIT_ORDER_SHIFT = 10,
136	I2S_CH_CTRL_RX_BIT_ORDER_MASK = 1 << I2S_CH_CTRL_RX_BIT_ORDER_SHIFT,
137	I2S_CH_CTRL_RX_BIT_ORDER_MSB_FIRST = I2S_MSB_FIRST <<
138					     I2S_CH_CTRL_RX_BIT_ORDER_SHIFT,
139	I2S_CH_CTRL_RX_BIT_ORDER_LSB_FIRST = I2S_LSB_FIRST <<
140					     I2S_CH_CTRL_RX_BIT_ORDER_SHIFT,
141	I2S_CH_CTRL_TX_BIT_ORDER_SHIFT = 9,
142	I2S_CH_CTRL_TX_BIT_ORDER_MASK = 1 << I2S_CH_CTRL_TX_BIT_ORDER_SHIFT,
143	I2S_CH_CTRL_TX_BIT_ORDER_MSB_FIRST = I2S_MSB_FIRST <<
144					     I2S_CH_CTRL_TX_BIT_ORDER_SHIFT,
145	I2S_CH_CTRL_TX_BIT_ORDER_LSB_FIRST = I2S_LSB_FIRST <<
146					     I2S_CH_CTRL_TX_BIT_ORDER_SHIFT,
147
148	I2S_POS_EDGE = 0,
149	I2S_NEG_EDGE = 1,
150
151	I2S_CH_CTRL_EGDE_CTRL_SHIFT = 8,
152	I2S_CH_CTRL_EGDE_CTRL_MASK = 1 << I2S_CH_CTRL_EGDE_CTRL_SHIFT,
153	I2S_CH_CTRL_EGDE_CTRL_POS_EDGE = I2S_POS_EDGE <<
154					 I2S_CH_CTRL_EGDE_CTRL_SHIFT,
155	I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE = I2S_NEG_EDGE <<
156					 I2S_CH_CTRL_EGDE_CTRL_SHIFT,
157
158	/* Sample size is # bits from BIT_SIZE minus this field */
159	I2S_CH_CTRL_RX_MASK_BITS_SHIFT = 4,
160	I2S_CH_CTRL_RX_MASK_BITS_MASK_US = 7,
161	I2S_CH_CTRL_RX_MASK_BITS_MASK = I2S_CH_CTRL_RX_MASK_BITS_MASK_US <<
162					I2S_CH_CTRL_RX_MASK_BITS_SHIFT,
163
164	I2S_CH_CTRL_TX_MASK_BITS_SHIFT = 0,
165	I2S_CH_CTRL_TX_MASK_BITS_MASK_US = 7,
166	I2S_CH_CTRL_TX_MASK_BITS_MASK = I2S_CH_CTRL_TX_MASK_BITS_MASK_US <<
167					I2S_CH_CTRL_TX_MASK_BITS_SHIFT,
168
169	/* Number of slots in frame, minus 1 */
170	I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT = 16,
171	I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US = 7,
172	I2S_SLOT_CTRL_TOTAL_SLOTS_MASK = I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US <<
173					 I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT,
174
175	/* TDM mode slot enable bitmask */
176	I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT = 8,
177	I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK =
178			0xff << I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT,
179
180	I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT = 0,
181	I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK = 0xff <<
182					   I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT,
183
184	I2S_FILTER_LINEAR = 0,
185	I2S_FILTER_QUAD = 1,
186
187	I2S_FLOWCTL_FILTER_SHIFT = 31,
188	I2S_FLOWCTL_FILTER_MASK = 1 << I2S_FLOWCTL_FILTER_SHIFT,
189	I2S_FLOWCTL_FILTER_LINEAR = I2S_FILTER_LINEAR <<
190				    I2S_FLOWCTL_FILTER_SHIFT,
191	I2S_FLOWCTL_FILTER_QUAD = I2S_FILTER_QUAD << I2S_FLOWCTL_FILTER_SHIFT,
192
193	I2S_TX_STEP_SHIFT = 0,
194	I2S_TX_STEP_MASK_US = 0xffff,
195	I2S_TX_STEP_MASK = I2S_TX_STEP_MASK_US << I2S_TX_STEP_SHIFT,
196
197	I2S_FLOW_STATUS_UNDERFLOW = 1 << 31,
198	I2S_FLOW_STATUS_OVERFLOW = 1 << 30,
199	I2S_FLOW_STATUS_MONITOR_INT_EN = 1 << 4,
200	I2S_FLOW_STATUS_COUNTER_CLR = 1 << 3,
201	I2S_FLOW_STATUS_MONITOR_CLR = 1 << 2,
202	I2S_FLOW_STATUS_COUNTER_EN = 1 << 1,
203	I2S_FLOW_STATUS_MONITOR_EN = 1 << 0,
204};
205
206#endif	/* _TEGRA_I2C_H_ */
207