1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd
4 */
5
6#ifndef _ASM_ARCH_SDRAM_RK3399_H
7#define _ASM_ARCH_SDRAM_RK3399_H
8#include <asm/arch-rockchip/sdram_common.h>
9#include <asm/arch-rockchip/sdram_msch.h>
10#ifndef __ASSEMBLY__
11#include <linux/bitops.h>
12#endif
13
14struct rk3399_ddr_pctl_regs {
15	u32 denali_ctl[332];
16};
17
18struct rk3399_ddr_publ_regs {
19	u32 denali_phy[959];
20};
21
22struct rk3399_ddr_pi_regs {
23	u32 denali_pi[200];
24};
25
26struct rk3399_ddr_cic_regs {
27	u32 cic_ctrl0;
28	u32 cic_ctrl1;
29	u32 cic_idle_th;
30	u32 cic_cg_wait_th;
31	u32 cic_status0;
32	u32 cic_status1;
33	u32 cic_ctrl2;
34	u32 cic_ctrl3;
35	u32 cic_ctrl4;
36};
37
38/* DENALI_CTL_00 */
39#define START		1
40
41/* DENALI_CTL_68 */
42#define PWRUP_SREFRESH_EXIT	BIT(16)
43
44/* DENALI_CTL_274 */
45#define MEM_RST_VALID	1
46
47struct msch_regs {
48	u32 coreid;
49	u32 revisionid;
50	u32 ddrconf;
51	u32 ddrsize;
52	union noc_ddrtiminga0 ddrtiminga0;
53	union noc_ddrtimingb0 ddrtimingb0;
54	union noc_ddrtimingc0 ddrtimingc0;
55	union noc_devtodev0 devtodev0;
56	u32 reserved0[(0x110 - 0x20) / 4];
57	union noc_ddrmode ddrmode;
58	u32 reserved1[(0x1000 - 0x114) / 4];
59	u32 agingx0;
60};
61
62struct sdram_msch_timings {
63	union noc_ddrtiminga0 ddrtiminga0;
64	union noc_ddrtimingb0 ddrtimingb0;
65	union noc_ddrtimingc0 ddrtimingc0;
66	union noc_devtodev0 devtodev0;
67	union noc_ddrmode ddrmode;
68	u32 agingx0;
69};
70
71struct rk3399_sdram_channel {
72	struct sdram_cap_info cap_info;
73	struct sdram_msch_timings noc_timings;
74};
75
76struct rk3399_sdram_params {
77	struct rk3399_sdram_channel ch[2];
78	struct sdram_base_params base;
79	struct rk3399_ddr_pctl_regs pctl_regs;
80	struct rk3399_ddr_pi_regs pi_regs;
81	struct rk3399_ddr_publ_regs phy_regs;
82};
83
84#define PI_CA_TRAINING		BIT(0)
85#define PI_WRITE_LEVELING	BIT(1)
86#define PI_READ_GATE_TRAINING	BIT(2)
87#define PI_READ_LEVELING	BIT(3)
88#define PI_WDQ_LEVELING		BIT(4)
89#define PI_FULL_TRAINING	0xff
90
91enum {
92	STRIDE_128B = 0,
93	STRIDE_256B = 1,
94	STRIDE_512B = 2,
95	STRIDE_4KB = 3,
96	UN_STRIDE = 4,
97	PART_STRIDE = 5,
98};
99
100#endif
101