1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2006-2010 4 * Texas Instruments, <www.ti.com> 5 */ 6 7#ifndef _CPU_H 8#define _CPU_H 9 10#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 11#include <asm/types.h> 12#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 13 14#include <asm/arch/hardware.h> 15 16#ifndef __KERNEL_STRICT_NAMES 17#ifndef __ASSEMBLY__ 18struct gptimer { 19 u32 tidr; /* 0x00 r */ 20 u8 res[0xc]; 21 u32 tiocp_cfg; /* 0x10 rw */ 22 u32 tistat; /* 0x14 r */ 23 u32 tisr; /* 0x18 rw */ 24 u32 tier; /* 0x1c rw */ 25 u32 twer; /* 0x20 rw */ 26 u32 tclr; /* 0x24 rw */ 27 u32 tcrr; /* 0x28 rw */ 28 u32 tldr; /* 0x2c rw */ 29 u32 ttgr; /* 0x30 rw */ 30 u32 twpc; /* 0x34 r */ 31 u32 tmar; /* 0x38 rw */ 32 u32 tcar1; /* 0x3c r */ 33 u32 tcicr; /* 0x40 rw */ 34 u32 tcar2; /* 0x44 r */ 35}; 36#endif /* __ASSEMBLY__ */ 37#endif /* __KERNEL_STRICT_NAMES */ 38 39/* enable sys_clk NO-prescale /1 */ 40#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) 41 42/* Watchdog */ 43#ifndef __KERNEL_STRICT_NAMES 44#ifndef __ASSEMBLY__ 45struct watchdog { 46 u8 res1[0x34]; 47 u32 wwps; /* 0x34 r */ 48 u8 res2[0x10]; 49 u32 wspr; /* 0x48 rw */ 50}; 51#endif /* __ASSEMBLY__ */ 52#endif /* __KERNEL_STRICT_NAMES */ 53 54#define WD_UNLOCK1 0xAAAA 55#define WD_UNLOCK2 0x5555 56 57#define TCLR_ST (0x1 << 0) 58#define TCLR_AR (0x1 << 1) 59#define TCLR_PRE (0x1 << 5) 60 61/* I2C base */ 62#define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000) 63#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000) 64#define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000) 65#define I2C_BASE4 (OMAP44XX_L4_PER_BASE + 0x350000) 66 67/* MUSB base */ 68#define MUSB_BASE (OMAP44XX_L4_CORE_BASE + 0xAB000) 69 70/* OMAP4 GPIO registers */ 71#define OMAP_GPIO_REVISION 0x0000 72#define OMAP_GPIO_SYSCONFIG 0x0010 73#define OMAP_GPIO_SYSSTATUS 0x0114 74#define OMAP_GPIO_IRQSTATUS1 0x0118 75#define OMAP_GPIO_IRQSTATUS2 0x0128 76#define OMAP_GPIO_IRQENABLE2 0x012c 77#define OMAP_GPIO_IRQENABLE1 0x011c 78#define OMAP_GPIO_WAKE_EN 0x0120 79#define OMAP_GPIO_CTRL 0x0130 80#define OMAP_GPIO_OE 0x0134 81#define OMAP_GPIO_DATAIN 0x0138 82#define OMAP_GPIO_DATAOUT 0x013c 83#define OMAP_GPIO_LEVELDETECT0 0x0140 84#define OMAP_GPIO_LEVELDETECT1 0x0144 85#define OMAP_GPIO_RISINGDETECT 0x0148 86#define OMAP_GPIO_FALLINGDETECT 0x014c 87#define OMAP_GPIO_DEBOUNCE_EN 0x0150 88#define OMAP_GPIO_DEBOUNCE_VAL 0x0154 89#define OMAP_GPIO_CLEARIRQENABLE1 0x0160 90#define OMAP_GPIO_SETIRQENABLE1 0x0164 91#define OMAP_GPIO_CLEARWKUENA 0x0180 92#define OMAP_GPIO_SETWKUENA 0x0184 93#define OMAP_GPIO_CLEARDATAOUT 0x0190 94#define OMAP_GPIO_SETDATAOUT 0x0194 95 96/* 97 * PRCM 98 */ 99 100/* PRM */ 101#define PRM_BASE 0x4A306000 102#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) 103 104#define PRM_RSTCTRL PRM_DEVICE_BASE 105#define PRM_RSTCTRL_RESET 0x01 106#define PRM_RSTST (PRM_DEVICE_BASE + 0x4) 107#define PRM_RSTST_WARM_RESET_MASK 0x07EA 108 109#endif /* _CPU_H */ 110