1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright (C) 2020 Marvell International Ltd. 4 * 5 * https://spdx.org/licenses 6 */ 7#ifndef __CSRS_MIO_EMM_H__ 8#define __CSRS_MIO_EMM_H__ 9 10/** 11 * @file 12 * 13 * Configuration and status register (CSR) address and type definitions for 14 * MIO_EMM. 15 * 16 * This file is auto generated. Do not edit. 17 * 18 */ 19 20/** 21 * Enumeration mio_emm_bar_e 22 * 23 * eMMC Base Address Register Enumeration Enumerates the base address 24 * registers. 25 */ 26#define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN8 (0x87e009000000ll) 27#define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN8_SIZE 0x800000ull 28#define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN9 (0x87e009000000ll) 29#define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN9_SIZE 0x10000ull 30#define MIO_EMM_BAR_E_MIO_EMM_PF_BAR4 (0x87e009f00000ll) 31#define MIO_EMM_BAR_E_MIO_EMM_PF_BAR4_SIZE 0x100000ull 32 33/** 34 * Enumeration mio_emm_int_vec_e 35 * 36 * eMMC MSI-X Vector Enumeration Enumerates the MSI-X interrupt vectors. 37 */ 38#define MIO_EMM_INT_VEC_E_DMA_INT_DONE (8) 39#define MIO_EMM_INT_VEC_E_DMA_INT_FIFO (7) 40#define MIO_EMM_INT_VEC_E_EMM_BUF_DONE (0) 41#define MIO_EMM_INT_VEC_E_EMM_CMD_DONE (1) 42#define MIO_EMM_INT_VEC_E_EMM_CMD_ERR (3) 43#define MIO_EMM_INT_VEC_E_EMM_DMA_DONE (2) 44#define MIO_EMM_INT_VEC_E_EMM_DMA_ERR (4) 45#define MIO_EMM_INT_VEC_E_EMM_SWITCH_DONE (5) 46#define MIO_EMM_INT_VEC_E_EMM_SWITCH_ERR (6) 47#define MIO_EMM_INT_VEC_E_NCB_FLT (9) 48#define MIO_EMM_INT_VEC_E_NCB_RAS (0xa) 49 50/** 51 * Register (RSL) mio_emm_access_wdog 52 * 53 * eMMC Access Watchdog Register 54 */ 55union mio_emm_access_wdog { 56 u64 u; 57 struct mio_emm_access_wdog_s { 58 u64 clk_cnt : 32; 59 u64 reserved_32_63 : 32; 60 } s; 61 /* struct mio_emm_access_wdog_s cn; */ 62}; 63 64static inline u64 MIO_EMM_ACCESS_WDOG(void) 65 __attribute__ ((pure, always_inline)); 66static inline u64 MIO_EMM_ACCESS_WDOG(void) 67{ 68 return 0x20f0; 69} 70 71/** 72 * Register (RSL) mio_emm_buf_dat 73 * 74 * eMMC Data Buffer Access Register 75 */ 76union mio_emm_buf_dat { 77 u64 u; 78 struct mio_emm_buf_dat_s { 79 u64 dat : 64; 80 } s; 81 /* struct mio_emm_buf_dat_s cn; */ 82}; 83 84static inline u64 MIO_EMM_BUF_DAT(void) 85 __attribute__ ((pure, always_inline)); 86static inline u64 MIO_EMM_BUF_DAT(void) 87{ 88 return 0x20e8; 89} 90 91/** 92 * Register (RSL) mio_emm_buf_idx 93 * 94 * eMMC Data Buffer Address Register 95 */ 96union mio_emm_buf_idx { 97 u64 u; 98 struct mio_emm_buf_idx_s { 99 u64 offset : 6; 100 u64 buf_num : 1; 101 u64 reserved_7_15 : 9; 102 u64 inc : 1; 103 u64 reserved_17_63 : 47; 104 } s; 105 /* struct mio_emm_buf_idx_s cn; */ 106}; 107 108static inline u64 MIO_EMM_BUF_IDX(void) 109 __attribute__ ((pure, always_inline)); 110static inline u64 MIO_EMM_BUF_IDX(void) 111{ 112 return 0x20e0; 113} 114 115/** 116 * Register (RSL) mio_emm_calb 117 * 118 * eMMC Calbration Register This register initiates delay line 119 * characterization. 120 */ 121union mio_emm_calb { 122 u64 u; 123 struct mio_emm_calb_s { 124 u64 start : 1; 125 u64 reserved_1_63 : 63; 126 } s; 127 /* struct mio_emm_calb_s cn; */ 128}; 129 130static inline u64 MIO_EMM_CALB(void) 131 __attribute__ ((pure, always_inline)); 132static inline u64 MIO_EMM_CALB(void) 133{ 134 return 0x20c0; 135} 136 137/** 138 * Register (RSL) mio_emm_cfg 139 * 140 * eMMC Configuration Register 141 */ 142union mio_emm_cfg { 143 u64 u; 144 struct mio_emm_cfg_s { 145 u64 bus_ena : 4; 146 u64 reserved_4_63 : 60; 147 } s; 148 /* struct mio_emm_cfg_s cn; */ 149}; 150 151static inline u64 MIO_EMM_CFG(void) 152 __attribute__ ((pure, always_inline)); 153static inline u64 MIO_EMM_CFG(void) 154{ 155 return 0x2000; 156} 157 158/** 159 * Register (RSL) mio_emm_cmd 160 * 161 * eMMC Command Register 162 */ 163union mio_emm_cmd { 164 u64 u; 165 struct mio_emm_cmd_s { 166 u64 arg : 32; 167 u64 cmd_idx : 6; 168 u64 rtype_xor : 3; 169 u64 ctype_xor : 2; 170 u64 reserved_43_48 : 6; 171 u64 offset : 6; 172 u64 dbuf : 1; 173 u64 reserved_56_58 : 3; 174 u64 cmd_val : 1; 175 u64 bus_id : 2; 176 u64 skip_busy : 1; 177 u64 reserved_63 : 1; 178 } s; 179 /* struct mio_emm_cmd_s cn; */ 180}; 181 182static inline u64 MIO_EMM_CMD(void) 183 __attribute__ ((pure, always_inline)); 184static inline u64 MIO_EMM_CMD(void) 185{ 186 return 0x2058; 187} 188 189/** 190 * Register (RSL) mio_emm_comp 191 * 192 * eMMC Compensation Register 193 */ 194union mio_emm_comp { 195 u64 u; 196 struct mio_emm_comp_s { 197 u64 nctl : 3; 198 u64 reserved_3_7 : 5; 199 u64 pctl : 3; 200 u64 reserved_11_63 : 53; 201 } s; 202 /* struct mio_emm_comp_s cn; */ 203}; 204 205static inline u64 MIO_EMM_COMP(void) 206 __attribute__ ((pure, always_inline)); 207static inline u64 MIO_EMM_COMP(void) 208{ 209 return 0x2040; 210} 211 212/** 213 * Register (RSL) mio_emm_debug 214 * 215 * eMMC Debug Register 216 */ 217union mio_emm_debug { 218 u64 u; 219 struct mio_emm_debug_s { 220 u64 clk_on : 1; 221 u64 reserved_1_7 : 7; 222 u64 cmd_sm : 4; 223 u64 data_sm : 4; 224 u64 dma_sm : 4; 225 u64 emmc_clk_disable : 1; 226 u64 rdsync_rst : 1; 227 u64 reserved_22_63 : 42; 228 } s; 229 struct mio_emm_debug_cn96xxp1 { 230 u64 clk_on : 1; 231 u64 reserved_1_7 : 7; 232 u64 cmd_sm : 4; 233 u64 data_sm : 4; 234 u64 dma_sm : 4; 235 u64 reserved_20_63 : 44; 236 } cn96xxp1; 237 /* struct mio_emm_debug_s cn96xxp3; */ 238 /* struct mio_emm_debug_cn96xxp1 cnf95xx; */ 239}; 240 241static inline u64 MIO_EMM_DEBUG(void) 242 __attribute__ ((pure, always_inline)); 243static inline u64 MIO_EMM_DEBUG(void) 244{ 245 return 0x20f8; 246} 247 248/** 249 * Register (RSL) mio_emm_dma 250 * 251 * eMMC External DMA Configuration Register 252 */ 253union mio_emm_dma { 254 u64 u; 255 struct mio_emm_dma_s { 256 u64 card_addr : 32; 257 u64 block_cnt : 16; 258 u64 multi : 1; 259 u64 rw : 1; 260 u64 rel_wr : 1; 261 u64 thres : 6; 262 u64 dat_null : 1; 263 u64 sector : 1; 264 u64 dma_val : 1; 265 u64 bus_id : 2; 266 u64 skip_busy : 1; 267 u64 extra_args : 1; 268 } s; 269 struct mio_emm_dma_cn8 { 270 u64 card_addr : 32; 271 u64 block_cnt : 16; 272 u64 multi : 1; 273 u64 rw : 1; 274 u64 rel_wr : 1; 275 u64 thres : 6; 276 u64 dat_null : 1; 277 u64 sector : 1; 278 u64 dma_val : 1; 279 u64 bus_id : 2; 280 u64 skip_busy : 1; 281 u64 reserved_63 : 1; 282 } cn8; 283 struct mio_emm_dma_cn9 { 284 u64 card_addr : 32; 285 u64 block_cnt : 16; 286 u64 multi : 1; 287 u64 rw : 1; 288 u64 reserved_50 : 1; 289 u64 thres : 6; 290 u64 dat_null : 1; 291 u64 sector : 1; 292 u64 dma_val : 1; 293 u64 bus_id : 2; 294 u64 skip_busy : 1; 295 u64 extra_args : 1; 296 } cn9; 297}; 298 299static inline u64 MIO_EMM_DMA(void) 300 __attribute__ ((pure, always_inline)); 301static inline u64 MIO_EMM_DMA(void) 302{ 303 return 0x2050; 304} 305 306/** 307 * Register (RSL) mio_emm_dma_adr 308 * 309 * eMMC DMA Address Register This register sets the address for eMMC/SD 310 * flash transfers to/from memory. Sixty-four-bit operations must be used 311 * to access this register. This register is updated by the DMA hardware 312 * and can be reloaded by the values placed in the MIO_EMM_DMA_FIFO_ADR. 313 */ 314union mio_emm_dma_adr { 315 u64 u; 316 struct mio_emm_dma_adr_s { 317 u64 adr : 53; 318 u64 reserved_53_63 : 11; 319 } s; 320 struct mio_emm_dma_adr_cn8 { 321 u64 adr : 49; 322 u64 reserved_49_63 : 15; 323 } cn8; 324 /* struct mio_emm_dma_adr_s cn9; */ 325}; 326 327static inline u64 MIO_EMM_DMA_ADR(void) 328 __attribute__ ((pure, always_inline)); 329static inline u64 MIO_EMM_DMA_ADR(void) 330{ 331 return 0x188; 332} 333 334/** 335 * Register (RSL) mio_emm_dma_arg 336 * 337 * eMMC External DMA Extra Arguments Register 338 */ 339union mio_emm_dma_arg { 340 u64 u; 341 struct mio_emm_dma_arg_s { 342 u64 cmd23_args : 8; 343 u64 force_pgm : 1; 344 u64 context_id : 4; 345 u64 tag_req : 1; 346 u64 pack_cmd : 1; 347 u64 rel_wr : 1; 348 u64 alt_cmd : 6; 349 u64 skip_blk_cmd : 1; 350 u64 reserved_23_31 : 9; 351 u64 alt_cmd_arg : 32; 352 } s; 353 /* struct mio_emm_dma_arg_s cn; */ 354}; 355 356static inline u64 MIO_EMM_DMA_ARG(void) 357 __attribute__ ((pure, always_inline)); 358static inline u64 MIO_EMM_DMA_ARG(void) 359{ 360 return 0x2090; 361} 362 363/** 364 * Register (RSL) mio_emm_dma_cfg 365 * 366 * eMMC DMA Configuration Register This register controls the internal 367 * DMA engine used with the eMMC/SD flash controller. Sixty- four-bit 368 * operations must be used to access this register. This register is 369 * updated by the hardware DMA engine and can also be reloaded by writes 370 * to the MIO_EMM_DMA_FIFO_CMD register. 371 */ 372union mio_emm_dma_cfg { 373 u64 u; 374 struct mio_emm_dma_cfg_s { 375 u64 reserved_0_35 : 36; 376 u64 size : 20; 377 u64 endian : 1; 378 u64 swap8 : 1; 379 u64 swap16 : 1; 380 u64 swap32 : 1; 381 u64 reserved_60 : 1; 382 u64 clr : 1; 383 u64 rw : 1; 384 u64 en : 1; 385 } s; 386 /* struct mio_emm_dma_cfg_s cn; */ 387}; 388 389static inline u64 MIO_EMM_DMA_CFG(void) 390 __attribute__ ((pure, always_inline)); 391static inline u64 MIO_EMM_DMA_CFG(void) 392{ 393 return 0x180; 394} 395 396/** 397 * Register (RSL) mio_emm_dma_fifo_adr 398 * 399 * eMMC Internal DMA FIFO Address Register This register specifies the 400 * internal address that is loaded into the eMMC internal DMA FIFO. The 401 * FIFO is used to queue up operations for the 402 * MIO_EMM_DMA_CFG/MIO_EMM_DMA_ADR when the DMA completes successfully. 403 */ 404union mio_emm_dma_fifo_adr { 405 u64 u; 406 struct mio_emm_dma_fifo_adr_s { 407 u64 reserved_0_2 : 3; 408 u64 adr : 50; 409 u64 reserved_53_63 : 11; 410 } s; 411 struct mio_emm_dma_fifo_adr_cn8 { 412 u64 reserved_0_2 : 3; 413 u64 adr : 46; 414 u64 reserved_49_63 : 15; 415 } cn8; 416 /* struct mio_emm_dma_fifo_adr_s cn9; */ 417}; 418 419static inline u64 MIO_EMM_DMA_FIFO_ADR(void) 420 __attribute__ ((pure, always_inline)); 421static inline u64 MIO_EMM_DMA_FIFO_ADR(void) 422{ 423 return 0x170; 424} 425 426/** 427 * Register (RSL) mio_emm_dma_fifo_cfg 428 * 429 * eMMC Internal DMA FIFO Configuration Register This register controls 430 * DMA FIFO operations. 431 */ 432union mio_emm_dma_fifo_cfg { 433 u64 u; 434 struct mio_emm_dma_fifo_cfg_s { 435 u64 count : 5; 436 u64 reserved_5_7 : 3; 437 u64 int_lvl : 5; 438 u64 reserved_13_15 : 3; 439 u64 clr : 1; 440 u64 reserved_17_63 : 47; 441 } s; 442 /* struct mio_emm_dma_fifo_cfg_s cn; */ 443}; 444 445static inline u64 MIO_EMM_DMA_FIFO_CFG(void) 446 __attribute__ ((pure, always_inline)); 447static inline u64 MIO_EMM_DMA_FIFO_CFG(void) 448{ 449 return 0x160; 450} 451 452/** 453 * Register (RSL) mio_emm_dma_fifo_cmd 454 * 455 * eMMC Internal DMA FIFO Command Register This register specifies a 456 * command that is loaded into the eMMC internal DMA FIFO. The FIFO is 457 * used to queue up operations for the MIO_EMM_DMA_CFG/MIO_EMM_DMA_ADR 458 * when the DMA completes successfully. Writes to this register store 459 * both the MIO_EMM_DMA_FIFO_CMD and the MIO_EMM_DMA_FIFO_ADR contents 460 * into the FIFO and increment the MIO_EMM_DMA_FIFO_CFG[COUNT] field. 461 * Note: This register has a similar format to MIO_EMM_DMA_CFG with the 462 * exception that the EN and CLR fields are absent. These are supported 463 * in MIO_EMM_DMA_FIFO_CFG. 464 */ 465union mio_emm_dma_fifo_cmd { 466 u64 u; 467 struct mio_emm_dma_fifo_cmd_s { 468 u64 reserved_0_35 : 36; 469 u64 size : 20; 470 u64 endian : 1; 471 u64 swap8 : 1; 472 u64 swap16 : 1; 473 u64 swap32 : 1; 474 u64 intdis : 1; 475 u64 reserved_61 : 1; 476 u64 rw : 1; 477 u64 reserved_63 : 1; 478 } s; 479 /* struct mio_emm_dma_fifo_cmd_s cn; */ 480}; 481 482static inline u64 MIO_EMM_DMA_FIFO_CMD(void) 483 __attribute__ ((pure, always_inline)); 484static inline u64 MIO_EMM_DMA_FIFO_CMD(void) 485{ 486 return 0x178; 487} 488 489/** 490 * Register (RSL) mio_emm_dma_int 491 * 492 * eMMC DMA Interrupt Register Sixty-four-bit operations must be used to 493 * access this register. 494 */ 495union mio_emm_dma_int { 496 u64 u; 497 struct mio_emm_dma_int_s { 498 u64 done : 1; 499 u64 fifo : 1; 500 u64 reserved_2_63 : 62; 501 } s; 502 /* struct mio_emm_dma_int_s cn; */ 503}; 504 505static inline u64 MIO_EMM_DMA_INT(void) 506 __attribute__ ((pure, always_inline)); 507static inline u64 MIO_EMM_DMA_INT(void) 508{ 509 return 0x190; 510} 511 512/** 513 * Register (RSL) mio_emm_dma_int_ena_w1c 514 * 515 * eMMC DMA Interrupt Enable Clear Register This register clears 516 * interrupt enable bits. 517 */ 518union mio_emm_dma_int_ena_w1c { 519 u64 u; 520 struct mio_emm_dma_int_ena_w1c_s { 521 u64 done : 1; 522 u64 fifo : 1; 523 u64 reserved_2_63 : 62; 524 } s; 525 /* struct mio_emm_dma_int_ena_w1c_s cn; */ 526}; 527 528static inline u64 MIO_EMM_DMA_INT_ENA_W1C(void) 529 __attribute__ ((pure, always_inline)); 530static inline u64 MIO_EMM_DMA_INT_ENA_W1C(void) 531{ 532 return 0x1a8; 533} 534 535/** 536 * Register (RSL) mio_emm_dma_int_ena_w1s 537 * 538 * eMMC DMA Interrupt Enable Set Register This register sets interrupt 539 * enable bits. 540 */ 541union mio_emm_dma_int_ena_w1s { 542 u64 u; 543 struct mio_emm_dma_int_ena_w1s_s { 544 u64 done : 1; 545 u64 fifo : 1; 546 u64 reserved_2_63 : 62; 547 } s; 548 /* struct mio_emm_dma_int_ena_w1s_s cn; */ 549}; 550 551static inline u64 MIO_EMM_DMA_INT_ENA_W1S(void) 552 __attribute__ ((pure, always_inline)); 553static inline u64 MIO_EMM_DMA_INT_ENA_W1S(void) 554{ 555 return 0x1a0; 556} 557 558/** 559 * Register (RSL) mio_emm_dma_int_w1s 560 * 561 * eMMC DMA Interrupt Set Register This register sets interrupt bits. 562 */ 563union mio_emm_dma_int_w1s { 564 u64 u; 565 struct mio_emm_dma_int_w1s_s { 566 u64 done : 1; 567 u64 fifo : 1; 568 u64 reserved_2_63 : 62; 569 } s; 570 /* struct mio_emm_dma_int_w1s_s cn; */ 571}; 572 573static inline u64 MIO_EMM_DMA_INT_W1S(void) 574 __attribute__ ((pure, always_inline)); 575static inline u64 MIO_EMM_DMA_INT_W1S(void) 576{ 577 return 0x198; 578} 579 580/** 581 * Register (RSL) mio_emm_int 582 * 583 * eMMC Interrupt Register 584 */ 585union mio_emm_int { 586 u64 u; 587 struct mio_emm_int_s { 588 u64 buf_done : 1; 589 u64 cmd_done : 1; 590 u64 dma_done : 1; 591 u64 cmd_err : 1; 592 u64 dma_err : 1; 593 u64 switch_done : 1; 594 u64 switch_err : 1; 595 u64 ncb_flt : 1; 596 u64 ncb_ras : 1; 597 u64 reserved_9_63 : 55; 598 } s; 599 struct mio_emm_int_cn8 { 600 u64 buf_done : 1; 601 u64 cmd_done : 1; 602 u64 dma_done : 1; 603 u64 cmd_err : 1; 604 u64 dma_err : 1; 605 u64 switch_done : 1; 606 u64 switch_err : 1; 607 u64 reserved_7_63 : 57; 608 } cn8; 609 /* struct mio_emm_int_s cn9; */ 610}; 611 612static inline u64 MIO_EMM_INT(void) 613 __attribute__ ((pure, always_inline)); 614static inline u64 MIO_EMM_INT(void) 615{ 616 return 0x2078; 617} 618 619/** 620 * Register (RSL) mio_emm_int_ena_w1c 621 * 622 * eMMC Interrupt Enable Clear Register This register clears interrupt 623 * enable bits. 624 */ 625union mio_emm_int_ena_w1c { 626 u64 u; 627 struct mio_emm_int_ena_w1c_s { 628 u64 buf_done : 1; 629 u64 cmd_done : 1; 630 u64 dma_done : 1; 631 u64 cmd_err : 1; 632 u64 dma_err : 1; 633 u64 switch_done : 1; 634 u64 switch_err : 1; 635 u64 ncb_flt : 1; 636 u64 ncb_ras : 1; 637 u64 reserved_9_63 : 55; 638 } s; 639 struct mio_emm_int_ena_w1c_cn8 { 640 u64 buf_done : 1; 641 u64 cmd_done : 1; 642 u64 dma_done : 1; 643 u64 cmd_err : 1; 644 u64 dma_err : 1; 645 u64 switch_done : 1; 646 u64 switch_err : 1; 647 u64 reserved_7_63 : 57; 648 } cn8; 649 /* struct mio_emm_int_ena_w1c_s cn9; */ 650}; 651 652static inline u64 MIO_EMM_INT_ENA_W1C(void) 653 __attribute__ ((pure, always_inline)); 654static inline u64 MIO_EMM_INT_ENA_W1C(void) 655{ 656 return 0x20b8; 657} 658 659/** 660 * Register (RSL) mio_emm_int_ena_w1s 661 * 662 * eMMC Interrupt Enable Set Register This register sets interrupt enable 663 * bits. 664 */ 665union mio_emm_int_ena_w1s { 666 u64 u; 667 struct mio_emm_int_ena_w1s_s { 668 u64 buf_done : 1; 669 u64 cmd_done : 1; 670 u64 dma_done : 1; 671 u64 cmd_err : 1; 672 u64 dma_err : 1; 673 u64 switch_done : 1; 674 u64 switch_err : 1; 675 u64 ncb_flt : 1; 676 u64 ncb_ras : 1; 677 u64 reserved_9_63 : 55; 678 } s; 679 struct mio_emm_int_ena_w1s_cn8 { 680 u64 buf_done : 1; 681 u64 cmd_done : 1; 682 u64 dma_done : 1; 683 u64 cmd_err : 1; 684 u64 dma_err : 1; 685 u64 switch_done : 1; 686 u64 switch_err : 1; 687 u64 reserved_7_63 : 57; 688 } cn8; 689 /* struct mio_emm_int_ena_w1s_s cn9; */ 690}; 691 692static inline u64 MIO_EMM_INT_ENA_W1S(void) 693 __attribute__ ((pure, always_inline)); 694static inline u64 MIO_EMM_INT_ENA_W1S(void) 695{ 696 return 0x20b0; 697} 698 699/** 700 * Register (RSL) mio_emm_int_w1s 701 * 702 * eMMC Interrupt Set Register This register sets interrupt bits. 703 */ 704union mio_emm_int_w1s { 705 u64 u; 706 struct mio_emm_int_w1s_s { 707 u64 buf_done : 1; 708 u64 cmd_done : 1; 709 u64 dma_done : 1; 710 u64 cmd_err : 1; 711 u64 dma_err : 1; 712 u64 switch_done : 1; 713 u64 switch_err : 1; 714 u64 ncb_flt : 1; 715 u64 ncb_ras : 1; 716 u64 reserved_9_63 : 55; 717 } s; 718 struct mio_emm_int_w1s_cn8 { 719 u64 buf_done : 1; 720 u64 cmd_done : 1; 721 u64 dma_done : 1; 722 u64 cmd_err : 1; 723 u64 dma_err : 1; 724 u64 switch_done : 1; 725 u64 switch_err : 1; 726 u64 reserved_7_63 : 57; 727 } cn8; 728 /* struct mio_emm_int_w1s_s cn9; */ 729}; 730 731static inline u64 MIO_EMM_INT_W1S(void) 732 __attribute__ ((pure, always_inline)); 733static inline u64 MIO_EMM_INT_W1S(void) 734{ 735 return 0x2080; 736} 737 738/** 739 * Register (RSL) mio_emm_io_ctl 740 * 741 * eMMC I/O Control Register 742 */ 743union mio_emm_io_ctl { 744 u64 u; 745 struct mio_emm_io_ctl_s { 746 u64 slew : 1; 747 u64 reserved_1 : 1; 748 u64 drive : 2; 749 u64 reserved_4_63 : 60; 750 } s; 751 /* struct mio_emm_io_ctl_s cn; */ 752}; 753 754static inline u64 MIO_EMM_IO_CTL(void) 755 __attribute__ ((pure, always_inline)); 756static inline u64 MIO_EMM_IO_CTL(void) 757{ 758 return 0x2040; 759} 760 761/** 762 * Register (RSL) mio_emm_mode# 763 * 764 * eMMC Operating Mode Register 765 */ 766union mio_emm_modex { 767 u64 u; 768 struct mio_emm_modex_s { 769 u64 clk_lo : 16; 770 u64 clk_hi : 16; 771 u64 power_class : 4; 772 u64 clk_swap : 1; 773 u64 reserved_37_39 : 3; 774 u64 bus_width : 3; 775 u64 reserved_43_47 : 5; 776 u64 hs_timing : 1; 777 u64 hs200_timing : 1; 778 u64 hs400_timing : 1; 779 u64 reserved_51_63 : 13; 780 } s; 781 struct mio_emm_modex_cn8 { 782 u64 clk_lo : 16; 783 u64 clk_hi : 16; 784 u64 power_class : 4; 785 u64 reserved_36_39 : 4; 786 u64 bus_width : 3; 787 u64 reserved_43_47 : 5; 788 u64 hs_timing : 1; 789 u64 reserved_49_63 : 15; 790 } cn8; 791 struct mio_emm_modex_cn96xxp1 { 792 u64 clk_lo : 16; 793 u64 clk_hi : 16; 794 u64 power_class : 4; 795 u64 reserved_36_39 : 4; 796 u64 bus_width : 3; 797 u64 reserved_43_47 : 5; 798 u64 hs_timing : 1; 799 u64 hs200_timing : 1; 800 u64 hs400_timing : 1; 801 u64 reserved_51_63 : 13; 802 } cn96xxp1; 803 /* struct mio_emm_modex_s cn96xxp3; */ 804 /* struct mio_emm_modex_s cnf95xx; */ 805}; 806 807static inline u64 MIO_EMM_MODEX(u64 a) 808 __attribute__ ((pure, always_inline)); 809static inline u64 MIO_EMM_MODEX(u64 a) 810{ 811 return 0x2008 + 8 * a; 812} 813 814/** 815 * Register (RSL) mio_emm_msix_pba# 816 * 817 * eMMC MSI-X Pending Bit Array Registers This register is the MSI-X PBA 818 * table; the bit number is indexed by the MIO_EMM_INT_VEC_E enumeration. 819 */ 820union mio_emm_msix_pbax { 821 u64 u; 822 struct mio_emm_msix_pbax_s { 823 u64 pend : 64; 824 } s; 825 /* struct mio_emm_msix_pbax_s cn; */ 826}; 827 828static inline u64 MIO_EMM_MSIX_PBAX(u64 a) 829 __attribute__ ((pure, always_inline)); 830static inline u64 MIO_EMM_MSIX_PBAX(u64 a) 831{ 832 return 0xf0000 + 8 * a; 833} 834 835/** 836 * Register (RSL) mio_emm_msix_vec#_addr 837 * 838 * eMMC MSI-X Vector-Table Address Register This register is the MSI-X 839 * vector table, indexed by the MIO_EMM_INT_VEC_E enumeration. 840 */ 841union mio_emm_msix_vecx_addr { 842 u64 u; 843 struct mio_emm_msix_vecx_addr_s { 844 u64 secvec : 1; 845 u64 reserved_1 : 1; 846 u64 addr : 51; 847 u64 reserved_53_63 : 11; 848 } s; 849 struct mio_emm_msix_vecx_addr_cn8 { 850 u64 secvec : 1; 851 u64 reserved_1 : 1; 852 u64 addr : 47; 853 u64 reserved_49_63 : 15; 854 } cn8; 855 /* struct mio_emm_msix_vecx_addr_s cn9; */ 856}; 857 858static inline u64 MIO_EMM_MSIX_VECX_ADDR(u64 a) 859 __attribute__ ((pure, always_inline)); 860static inline u64 MIO_EMM_MSIX_VECX_ADDR(u64 a) 861{ 862 return 0 + 0x10 * a; 863} 864 865/** 866 * Register (RSL) mio_emm_msix_vec#_ctl 867 * 868 * eMMC MSI-X Vector-Table Control and Data Register This register is the 869 * MSI-X vector table, indexed by the MIO_EMM_INT_VEC_E enumeration. 870 */ 871union mio_emm_msix_vecx_ctl { 872 u64 u; 873 struct mio_emm_msix_vecx_ctl_s { 874 u64 data : 32; 875 u64 mask : 1; 876 u64 reserved_33_63 : 31; 877 } s; 878 struct mio_emm_msix_vecx_ctl_cn8 { 879 u64 data : 20; 880 u64 reserved_20_31 : 12; 881 u64 mask : 1; 882 u64 reserved_33_63 : 31; 883 } cn8; 884 /* struct mio_emm_msix_vecx_ctl_s cn9; */ 885}; 886 887static inline u64 MIO_EMM_MSIX_VECX_CTL(u64 a) 888 __attribute__ ((pure, always_inline)); 889static inline u64 MIO_EMM_MSIX_VECX_CTL(u64 a) 890{ 891 return 8 + 0x10 * a; 892} 893 894/** 895 * Register (RSL) mio_emm_rca 896 * 897 * eMMC Relative Card Address Register 898 */ 899union mio_emm_rca { 900 u64 u; 901 struct mio_emm_rca_s { 902 u64 card_rca : 16; 903 u64 reserved_16_63 : 48; 904 } s; 905 /* struct mio_emm_rca_s cn; */ 906}; 907 908static inline u64 MIO_EMM_RCA(void) 909 __attribute__ ((pure, always_inline)); 910static inline u64 MIO_EMM_RCA(void) 911{ 912 return 0x20a0; 913} 914 915/** 916 * Register (RSL) mio_emm_rsp_hi 917 * 918 * eMMC Response Data High Register 919 */ 920union mio_emm_rsp_hi { 921 u64 u; 922 struct mio_emm_rsp_hi_s { 923 u64 dat : 64; 924 } s; 925 /* struct mio_emm_rsp_hi_s cn; */ 926}; 927 928static inline u64 MIO_EMM_RSP_HI(void) 929 __attribute__ ((pure, always_inline)); 930static inline u64 MIO_EMM_RSP_HI(void) 931{ 932 return 0x2070; 933} 934 935/** 936 * Register (RSL) mio_emm_rsp_lo 937 * 938 * eMMC Response Data Low Register 939 */ 940union mio_emm_rsp_lo { 941 u64 u; 942 struct mio_emm_rsp_lo_s { 943 u64 dat : 64; 944 } s; 945 /* struct mio_emm_rsp_lo_s cn; */ 946}; 947 948static inline u64 MIO_EMM_RSP_LO(void) 949 __attribute__ ((pure, always_inline)); 950static inline u64 MIO_EMM_RSP_LO(void) 951{ 952 return 0x2068; 953} 954 955/** 956 * Register (RSL) mio_emm_rsp_sts 957 * 958 * eMMC Response Status Register 959 */ 960union mio_emm_rsp_sts { 961 u64 u; 962 struct mio_emm_rsp_sts_s { 963 u64 cmd_done : 1; 964 u64 cmd_idx : 6; 965 u64 cmd_type : 2; 966 u64 rsp_type : 3; 967 u64 rsp_val : 1; 968 u64 rsp_bad_sts : 1; 969 u64 rsp_crc_err : 1; 970 u64 rsp_timeout : 1; 971 u64 stp_val : 1; 972 u64 stp_bad_sts : 1; 973 u64 stp_crc_err : 1; 974 u64 stp_timeout : 1; 975 u64 rsp_busybit : 1; 976 u64 blk_crc_err : 1; 977 u64 blk_timeout : 1; 978 u64 dbuf : 1; 979 u64 reserved_24_27 : 4; 980 u64 dbuf_err : 1; 981 u64 reserved_29_54 : 26; 982 u64 acc_timeout : 1; 983 u64 dma_pend : 1; 984 u64 dma_val : 1; 985 u64 switch_val : 1; 986 u64 cmd_val : 1; 987 u64 bus_id : 2; 988 u64 reserved_62_63 : 2; 989 } s; 990 /* struct mio_emm_rsp_sts_s cn; */ 991}; 992 993static inline u64 MIO_EMM_RSP_STS(void) 994 __attribute__ ((pure, always_inline)); 995static inline u64 MIO_EMM_RSP_STS(void) 996{ 997 return 0x2060; 998} 999 1000/** 1001 * Register (RSL) mio_emm_sample 1002 * 1003 * eMMC Sampling Register 1004 */ 1005union mio_emm_sample { 1006 u64 u; 1007 struct mio_emm_sample_s { 1008 u64 dat_cnt : 10; 1009 u64 reserved_10_15 : 6; 1010 u64 cmd_cnt : 10; 1011 u64 reserved_26_63 : 38; 1012 } s; 1013 /* struct mio_emm_sample_s cn; */ 1014}; 1015 1016static inline u64 MIO_EMM_SAMPLE(void) 1017 __attribute__ ((pure, always_inline)); 1018static inline u64 MIO_EMM_SAMPLE(void) 1019{ 1020 return 0x2090; 1021} 1022 1023/** 1024 * Register (RSL) mio_emm_sts_mask 1025 * 1026 * eMMC Status Mask Register 1027 */ 1028union mio_emm_sts_mask { 1029 u64 u; 1030 struct mio_emm_sts_mask_s { 1031 u64 sts_msk : 32; 1032 u64 reserved_32_63 : 32; 1033 } s; 1034 /* struct mio_emm_sts_mask_s cn; */ 1035}; 1036 1037static inline u64 MIO_EMM_STS_MASK(void) 1038 __attribute__ ((pure, always_inline)); 1039static inline u64 MIO_EMM_STS_MASK(void) 1040{ 1041 return 0x2098; 1042} 1043 1044/** 1045 * Register (RSL) mio_emm_switch 1046 * 1047 * eMMC Operating Mode Switch Register This register allows software to 1048 * change eMMC related parameters associated with a specific BUS_ID. The 1049 * MIO_EMM_MODE() registers contain the current setting for each BUS. 1050 * This register is also used to switch the [CLK_HI] and [CLK_LO] 1051 * settings associated with the common EMMC_CLK. These settings can only 1052 * be changed when [BUS_ID] = 0. 1053 */ 1054union mio_emm_switch { 1055 u64 u; 1056 struct mio_emm_switch_s { 1057 u64 clk_lo : 16; 1058 u64 clk_hi : 16; 1059 u64 power_class : 4; 1060 u64 clk_swap : 1; 1061 u64 reserved_37_39 : 3; 1062 u64 bus_width : 3; 1063 u64 reserved_43_47 : 5; 1064 u64 hs_timing : 1; 1065 u64 hs200_timing : 1; 1066 u64 hs400_timing : 1; 1067 u64 reserved_51_55 : 5; 1068 u64 switch_err2 : 1; 1069 u64 switch_err1 : 1; 1070 u64 switch_err0 : 1; 1071 u64 switch_exe : 1; 1072 u64 bus_id : 2; 1073 u64 reserved_62_63 : 2; 1074 } s; 1075 struct mio_emm_switch_cn8 { 1076 u64 clk_lo : 16; 1077 u64 clk_hi : 16; 1078 u64 power_class : 4; 1079 u64 reserved_36_39 : 4; 1080 u64 bus_width : 3; 1081 u64 reserved_43_47 : 5; 1082 u64 hs_timing : 1; 1083 u64 reserved_49_55 : 7; 1084 u64 switch_err2 : 1; 1085 u64 switch_err1 : 1; 1086 u64 switch_err0 : 1; 1087 u64 switch_exe : 1; 1088 u64 bus_id : 2; 1089 u64 reserved_62_63 : 2; 1090 } cn8; 1091 struct mio_emm_switch_cn96xxp1 { 1092 u64 clk_lo : 16; 1093 u64 clk_hi : 16; 1094 u64 power_class : 4; 1095 u64 reserved_36_39 : 4; 1096 u64 bus_width : 3; 1097 u64 reserved_43_47 : 5; 1098 u64 hs_timing : 1; 1099 u64 hs200_timing : 1; 1100 u64 hs400_timing : 1; 1101 u64 reserved_51_55 : 5; 1102 u64 switch_err2 : 1; 1103 u64 switch_err1 : 1; 1104 u64 switch_err0 : 1; 1105 u64 switch_exe : 1; 1106 u64 bus_id : 2; 1107 u64 reserved_62_63 : 2; 1108 } cn96xxp1; 1109 /* struct mio_emm_switch_s cn96xxp3; */ 1110 /* struct mio_emm_switch_s cnf95xx; */ 1111}; 1112 1113static inline u64 MIO_EMM_SWITCH(void) 1114 __attribute__ ((pure, always_inline)); 1115static inline u64 MIO_EMM_SWITCH(void) 1116{ 1117 return 0x2048; 1118} 1119 1120/** 1121 * Register (RSL) mio_emm_tap 1122 * 1123 * eMMC TAP Delay Register This register indicates the delay line 1124 * characteristics. 1125 */ 1126union mio_emm_tap { 1127 u64 u; 1128 struct mio_emm_tap_s { 1129 u64 delay : 8; 1130 u64 reserved_8_63 : 56; 1131 } s; 1132 /* struct mio_emm_tap_s cn; */ 1133}; 1134 1135static inline u64 MIO_EMM_TAP(void) 1136 __attribute__ ((pure, always_inline)); 1137static inline u64 MIO_EMM_TAP(void) 1138{ 1139 return 0x20c8; 1140} 1141 1142/** 1143 * Register (RSL) mio_emm_timing 1144 * 1145 * eMMC Timing Register This register determines the number of tap delays 1146 * the EMM_DAT, EMM_DS, and EMM_CMD lines are transmitted or received in 1147 * relation to EMM_CLK. These values should only be changed when the eMMC 1148 * bus is idle. 1149 */ 1150union mio_emm_timing { 1151 u64 u; 1152 struct mio_emm_timing_s { 1153 u64 data_out_tap : 6; 1154 u64 reserved_6_15 : 10; 1155 u64 data_in_tap : 6; 1156 u64 reserved_22_31 : 10; 1157 u64 cmd_out_tap : 6; 1158 u64 reserved_38_47 : 10; 1159 u64 cmd_in_tap : 6; 1160 u64 reserved_54_63 : 10; 1161 } s; 1162 /* struct mio_emm_timing_s cn; */ 1163}; 1164 1165static inline u64 MIO_EMM_TIMING(void) 1166 __attribute__ ((pure, always_inline)); 1167static inline u64 MIO_EMM_TIMING(void) 1168{ 1169 return 0x20d0; 1170} 1171 1172/** 1173 * Register (RSL) mio_emm_wdog 1174 * 1175 * eMMC Watchdog Register 1176 */ 1177union mio_emm_wdog { 1178 u64 u; 1179 struct mio_emm_wdog_s { 1180 u64 clk_cnt : 26; 1181 u64 reserved_26_63 : 38; 1182 } s; 1183 /* struct mio_emm_wdog_s cn; */ 1184}; 1185 1186static inline u64 MIO_EMM_WDOG(void) 1187 __attribute__ ((pure, always_inline)); 1188static inline u64 MIO_EMM_WDOG(void) 1189{ 1190 return 0x2088; 1191} 1192 1193#endif /* __CSRS_MIO_EMM_H__ */ 1194