1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Freescale i.MX28 OCOTP Register Definitions 4 * 5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 6 * on behalf of DENX Software Engineering GmbH 7 * 8 * Based on code from LTIB: 9 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. 10 */ 11 12#ifndef __MX28_REGS_OCOTP_H__ 13#define __MX28_REGS_OCOTP_H__ 14 15#include <asm/mach-imx/regs-common.h> 16 17#ifndef __ASSEMBLY__ 18struct mxs_ocotp_regs { 19 mxs_reg_32(hw_ocotp_ctrl) /* 0x0 */ 20 mxs_reg_32(hw_ocotp_data) /* 0x10 */ 21 mxs_reg_32(hw_ocotp_cust0) /* 0x20 */ 22 mxs_reg_32(hw_ocotp_cust1) /* 0x30 */ 23 mxs_reg_32(hw_ocotp_cust2) /* 0x40 */ 24 mxs_reg_32(hw_ocotp_cust3) /* 0x50 */ 25 mxs_reg_32(hw_ocotp_crypto0) /* 0x60 */ 26 mxs_reg_32(hw_ocotp_crypto1) /* 0x70 */ 27 mxs_reg_32(hw_ocotp_crypto2) /* 0x80 */ 28 mxs_reg_32(hw_ocotp_crypto3) /* 0x90 */ 29 mxs_reg_32(hw_ocotp_hwcap0) /* 0xa0 */ 30 mxs_reg_32(hw_ocotp_hwcap1) /* 0xb0 */ 31 mxs_reg_32(hw_ocotp_hwcap2) /* 0xc0 */ 32 mxs_reg_32(hw_ocotp_hwcap3) /* 0xd0 */ 33 mxs_reg_32(hw_ocotp_hwcap4) /* 0xe0 */ 34 mxs_reg_32(hw_ocotp_hwcap5) /* 0xf0 */ 35 mxs_reg_32(hw_ocotp_swcap) /* 0x100 */ 36 mxs_reg_32(hw_ocotp_custcap) /* 0x110 */ 37 mxs_reg_32(hw_ocotp_lock) /* 0x120 */ 38 mxs_reg_32(hw_ocotp_ops0) /* 0x130 */ 39 mxs_reg_32(hw_ocotp_ops1) /* 0x140 */ 40 mxs_reg_32(hw_ocotp_ops2) /* 0x150 */ 41 mxs_reg_32(hw_ocotp_ops3) /* 0x160 */ 42 mxs_reg_32(hw_ocotp_un0) /* 0x170 */ 43 mxs_reg_32(hw_ocotp_un1) /* 0x180 */ 44 mxs_reg_32(hw_ocotp_un2) /* 0x190 */ 45 mxs_reg_32(hw_ocotp_rom0) /* 0x1a0 */ 46 mxs_reg_32(hw_ocotp_rom1) /* 0x1b0 */ 47 mxs_reg_32(hw_ocotp_rom2) /* 0x1c0 */ 48 mxs_reg_32(hw_ocotp_rom3) /* 0x1d0 */ 49 mxs_reg_32(hw_ocotp_rom4) /* 0x1e0 */ 50 mxs_reg_32(hw_ocotp_rom5) /* 0x1f0 */ 51 mxs_reg_32(hw_ocotp_rom6) /* 0x200 */ 52 mxs_reg_32(hw_ocotp_rom7) /* 0x210 */ 53 mxs_reg_32(hw_ocotp_srk0) /* 0x220 */ 54 mxs_reg_32(hw_ocotp_srk1) /* 0x230 */ 55 mxs_reg_32(hw_ocotp_srk2) /* 0x240 */ 56 mxs_reg_32(hw_ocotp_srk3) /* 0x250 */ 57 mxs_reg_32(hw_ocotp_srk4) /* 0x260 */ 58 mxs_reg_32(hw_ocotp_srk5) /* 0x270 */ 59 mxs_reg_32(hw_ocotp_srk6) /* 0x280 */ 60 mxs_reg_32(hw_ocotp_srk7) /* 0x290 */ 61 mxs_reg_32(hw_ocotp_version) /* 0x2a0 */ 62}; 63#endif 64 65#define OCOTP_CTRL_WR_UNLOCK_MASK (0xffff << 16) 66#define OCOTP_CTRL_WR_UNLOCK_OFFSET 16 67#define OCOTP_CTRL_WR_UNLOCK_KEY (0x3e77 << 16) 68#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 13) 69#define OCOTP_CTRL_RD_BANK_OPEN (1 << 12) 70#define OCOTP_CTRL_ERROR (1 << 9) 71#define OCOTP_CTRL_BUSY (1 << 8) 72#define OCOTP_CTRL_ADDR_MASK 0x3f 73#define OCOTP_CTRL_ADDR_OFFSET 0 74 75#define OCOTP_DATA_DATA_MASK 0xffffffff 76#define OCOTP_DATA_DATA_OFFSET 0 77 78#define OCOTP_CUST_BITS_MASK 0xffffffff 79#define OCOTP_CUST_BITS_OFFSET 0 80 81#define OCOTP_CRYPTO_BITS_MASK 0xffffffff 82#define OCOTP_CRYPTO_BITS_OFFSET 0 83 84#define OCOTP_HWCAP_BITS_MASK 0xffffffff 85#define OCOTP_HWCAP_BITS_OFFSET 0 86 87#define OCOTP_SWCAP_BITS_MASK 0xffffffff 88#define OCOTP_SWCAP_BITS_OFFSET 0 89 90#define OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT (1 << 2) 91#define OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT (1 << 1) 92 93#define OCOTP_LOCK_ROM7 (1 << 31) 94#define OCOTP_LOCK_ROM6 (1 << 30) 95#define OCOTP_LOCK_ROM5 (1 << 29) 96#define OCOTP_LOCK_ROM4 (1 << 28) 97#define OCOTP_LOCK_ROM3 (1 << 27) 98#define OCOTP_LOCK_ROM2 (1 << 26) 99#define OCOTP_LOCK_ROM1 (1 << 25) 100#define OCOTP_LOCK_ROM0 (1 << 24) 101#define OCOTP_LOCK_HWSW_SHADOW_ALT (1 << 23) 102#define OCOTP_LOCK_CRYPTODCP_ALT (1 << 22) 103#define OCOTP_LOCK_CRYPTOKEY_ALT (1 << 21) 104#define OCOTP_LOCK_PIN (1 << 20) 105#define OCOTP_LOCK_OPS (1 << 19) 106#define OCOTP_LOCK_UN2 (1 << 18) 107#define OCOTP_LOCK_UN1 (1 << 17) 108#define OCOTP_LOCK_UN0 (1 << 16) 109#define OCOTP_LOCK_SRK (1 << 15) 110#define OCOTP_LOCK_UNALLOCATED_MASK (0x7 << 12) 111#define OCOTP_LOCK_UNALLOCATED_OFFSET 12 112#define OCOTP_LOCK_SRK_SHADOW (1 << 11) 113#define OCOTP_LOCK_ROM_SHADOW (1 << 10) 114#define OCOTP_LOCK_CUSTCAP (1 << 9) 115#define OCOTP_LOCK_HWSW (1 << 8) 116#define OCOTP_LOCK_CUSTCAP_SHADOW (1 << 7) 117#define OCOTP_LOCK_HWSW_SHADOW (1 << 6) 118#define OCOTP_LOCK_CRYPTODCP (1 << 5) 119#define OCOTP_LOCK_CRYPTOKEY (1 << 4) 120#define OCOTP_LOCK_CUST3 (1 << 3) 121#define OCOTP_LOCK_CUST2 (1 << 2) 122#define OCOTP_LOCK_CUST1 (1 << 1) 123#define OCOTP_LOCK_CUST0 (1 << 0) 124 125#define OCOTP_OPS_BITS_MASK 0xffffffff 126#define OCOTP_OPS_BITS_OFFSET 0 127 128#define OCOTP_UN_BITS_MASK 0xffffffff 129#define OCOTP_UN_BITS_OFFSET 0 130 131#define OCOTP_ROM_BOOT_MODE_MASK (0xff << 24) 132#define OCOTP_ROM_BOOT_MODE_OFFSET 24 133#define OCOTP_ROM_SD_MMC_MODE_MASK (0x3 << 22) 134#define OCOTP_ROM_SD_MMC_MODE_OFFSET 22 135#define OCOTP_ROM_SD_POWER_GATE_GPIO_MASK (0x3 << 20) 136#define OCOTP_ROM_SD_POWER_GATE_GPIO_OFFSET 20 137#define OCOTP_ROM_SD_POWER_UP_DELAY_MASK (0x3f << 14) 138#define OCOTP_ROM_SD_POWER_UP_DELAY_OFFSET 14 139#define OCOTP_ROM_SD_BUS_WIDTH_MASK (0x3 << 12) 140#define OCOTP_ROM_SD_BUS_WIDTH_OFFSET 12 141#define OCOTP_ROM_SSP_SCK_INDEX_MASK (0xf << 8) 142#define OCOTP_ROM_SSP_SCK_INDEX_OFFSET 8 143#define OCOTP_ROM_EMMC_USE_DDR (1 << 7) 144#define OCOTP_ROM_DISABLE_SPI_NOR_FAST_READ (1 << 6) 145#define OCOTP_ROM_ENABLE_USB_BOOT_SERIAL_NUM (1 << 5) 146#define OCOTP_ROM_ENABLE_UNENCRYPTED_BOOT (1 << 4) 147#define OCOTP_ROM_SD_MBR_BOOT (1 << 3) 148 149#define OCOTP_SRK_BITS_MASK 0xffffffff 150#define OCOTP_SRK_BITS_OFFSET 0 151 152#define OCOTP_VERSION_MAJOR_MASK (0xff << 24) 153#define OCOTP_VERSION_MAJOR_OFFSET 24 154#define OCOTP_VERSION_MINOR_MASK (0xff << 16) 155#define OCOTP_VERSION_MINOR_OFFSET 16 156#define OCOTP_VERSION_STEP_MASK 0xffff 157#define OCOTP_VERSION_STEP_OFFSET 0 158 159#endif /* __MX28_REGS_OCOTP_H__ */ 160