1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2016 - AmLogic, Inc. 4 * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com> 5 * Copyright 2018 - BayLibre, SAS 6 * Author: Neil Armstrong <narmstrong@baylibre.com> 7 */ 8#ifndef _ARCH_MESON_CLOCK_G12A_H_ 9#define _ARCH_MESON_CLOCK_G12A_H_ 10 11/* 12 * Clock controller register offsets 13 * 14 * Register offsets from the data sheet are listed in comment blocks below. 15 * Those offsets must be multiplied by 4 before adding them to the base address 16 * to get the right value 17 */ 18 19#define HHI_MIPI_CNTL0 0x000 20#define HHI_MIPI_CNTL1 0x004 21#define HHI_MIPI_CNTL2 0x008 22#define HHI_MIPI_STS 0x00C 23#define HHI_GP0_PLL_CNTL0 0x040 24#define HHI_GP0_PLL_CNTL1 0x044 25#define HHI_GP0_PLL_CNTL2 0x048 26#define HHI_GP0_PLL_CNTL3 0x04C 27#define HHI_GP0_PLL_CNTL4 0x050 28#define HHI_GP0_PLL_CNTL5 0x054 29#define HHI_GP0_PLL_CNTL6 0x058 30#define HHI_GP0_PLL_STS 0x05C 31#define HHI_PCIE_PLL_CNTL0 0x098 32#define HHI_PCIE_PLL_CNTL1 0x09C 33#define HHI_PCIE_PLL_CNTL2 0x0A0 34#define HHI_PCIE_PLL_CNTL3 0x0A4 35#define HHI_PCIE_PLL_CNTL4 0x0A8 36#define HHI_PCIE_PLL_CNTL5 0x0AC 37#define HHI_PCIE_PLL_STS 0x0B8 38#define HHI_HIFI_PLL_CNTL0 0x0D8 39#define HHI_HIFI_PLL_CNTL1 0x0DC 40#define HHI_HIFI_PLL_CNTL2 0x0E0 41#define HHI_HIFI_PLL_CNTL3 0x0E4 42#define HHI_HIFI_PLL_CNTL4 0x0E8 43#define HHI_HIFI_PLL_CNTL5 0x0EC 44#define HHI_HIFI_PLL_CNTL6 0x0F0 45#define HHI_VIID_CLK_DIV 0x128 46#define HHI_VIID_CLK_CNTL 0x12C 47#define HHI_GCLK_MPEG0 0x140 48#define HHI_GCLK_MPEG1 0x144 49#define HHI_GCLK_MPEG2 0x148 50#define HHI_GCLK_OTHER 0x150 51#define HHI_GCLK_OTHER2 0x154 52#define HHI_VID_CLK_DIV 0x164 53#define HHI_MPEG_CLK_CNTL 0x174 54#define HHI_AUD_CLK_CNTL 0x178 55#define HHI_VID_CLK_CNTL 0x17c 56#define HHI_TS_CLK_CNTL 0x190 57#define HHI_VID_CLK_CNTL2 0x194 58#define HHI_SYS_CPU_CLK_CNTL0 0x19c 59#define HHI_VID_PLL_CLK_DIV 0x1A0 60#define HHI_MALI_CLK_CNTL 0x1b0 61#define HHI_VPU_CLKC_CNTL 0x1b4 62#define HHI_VPU_CLK_CNTL 0x1bC 63#define HHI_HDMI_CLK_CNTL 0x1CC 64#define HHI_VDEC_CLK_CNTL 0x1E0 65#define HHI_VDEC2_CLK_CNTL 0x1E4 66#define HHI_VDEC3_CLK_CNTL 0x1E8 67#define HHI_VDEC4_CLK_CNTL 0x1EC 68#define HHI_HDCP22_CLK_CNTL 0x1F0 69#define HHI_VAPBCLK_CNTL 0x1F4 70#define HHI_VPU_CLKB_CNTL 0x20C 71#define HHI_GEN_CLK_CNTL 0x228 72#define HHI_VDIN_MEAS_CLK_CNTL 0x250 73#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254 74#define HHI_NAND_CLK_CNTL 0x25C 75#define HHI_SD_EMMC_CLK_CNTL 0x264 76#define HHI_MPLL_CNTL0 0x278 77#define HHI_MPLL_CNTL1 0x27C 78#define HHI_MPLL_CNTL2 0x280 79#define HHI_MPLL_CNTL3 0x284 80#define HHI_MPLL_CNTL4 0x288 81#define HHI_MPLL_CNTL5 0x28c 82#define HHI_MPLL_CNTL6 0x290 83#define HHI_MPLL_CNTL7 0x294 84#define HHI_MPLL_CNTL8 0x298 85#define HHI_FIX_PLL_CNTL0 0x2A0 86#define HHI_FIX_PLL_CNTL1 0x2A4 87#define HHI_FIX_PLL_CNTL3 0x2AC 88#define HHI_SYS_PLL_CNTL0 0x2f4 89#define HHI_SYS_PLL_CNTL1 0x2f8 90#define HHI_SYS_PLL_CNTL2 0x2fc 91#define HHI_SYS_PLL_CNTL3 0x300 92#define HHI_SYS_PLL_CNTL4 0x304 93#define HHI_SYS_PLL_CNTL5 0x308 94#define HHI_SYS_PLL_CNTL6 0x30c 95#define HHI_HDMI_PLL_CNTL0 0x320 96#define HHI_HDMI_PLL_CNTL1 0x324 97#define HHI_HDMI_PLL_CNTL2 0x328 98#define HHI_HDMI_PLL_CNTL3 0x32c 99#define HHI_HDMI_PLL_CNTL4 0x330 100#define HHI_HDMI_PLL_CNTL5 0x334 101#define HHI_HDMI_PLL_CNTL6 0x338 102#define HHI_SPICC_CLK_CNTL 0x3dc 103 104#endif 105