1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 * Copyright 2019 NXP Semiconductors
5 *
6 */
7
8#ifndef __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
9#define __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
10
11enum mxc_clock {
12	MXC_ARM_CLK = 0,
13	MXC_BUS_CLK,
14	MXC_UART_CLK,
15	MXC_I2C_CLK,
16	MXC_DSPI_CLK,
17};
18
19unsigned int mxc_get_clock(enum mxc_clock clk);
20ulong get_ddr_freq(ulong);
21uint get_svr(void);
22
23#endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */
24