1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2016 Nexell
4 * Hyunseok, Jung <hsjung@nexell.co.kr>
5 */
6
7#include <common.h>
8#include <command.h>
9#include <asm/system.h>
10#include <asm/cache.h>
11#include <asm/global_data.h>
12#include <asm/sections.h>
13#include <asm/io.h>
14#include <asm/arch/nexell.h>
15#include <asm/arch/clk.h>
16#include <asm/arch/tieoff.h>
17#include <cpu_func.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21#ifndef	CONFIG_ARCH_CPU_INIT
22#error must be define the macro "CONFIG_ARCH_CPU_INIT"
23#endif
24
25void s_init(void)
26{
27}
28
29static void cpu_soc_init(void)
30{
31	/*
32	 * NOTE> ALIVE Power Gate must enable for Alive register access.
33	 *	     must be clear wfi jump address
34	 */
35	writel(1, ALIVEPWRGATEREG);
36	writel(0xFFFFFFFF, SCR_ARM_SECOND_BOOT);
37
38	/* write 0xf0 on alive scratchpad reg for boot success check */
39	writel(readl(SCR_SIGNAGURE_READ) | 0xF0, (SCR_SIGNAGURE_SET));
40
41	/* set l2 cache tieoff */
42	nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_0, 1);
43	nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1);
44}
45
46int arch_cpu_init(void)
47{
48	flush_dcache_all();
49	cpu_soc_init();
50	clk_init();
51
52	return 0;
53}
54
55#if defined(CONFIG_DISPLAY_CPUINFO)
56int print_cpuinfo(void)
57{
58	return 0;
59}
60#endif
61
62void reset_cpu(void)
63{
64	void *clkpwr_reg = (void *)PHY_BASEADDR_CLKPWR;
65	const u32 sw_rst_enb_bitpos = 3;
66	const u32 sw_rst_enb_mask = 1 << sw_rst_enb_bitpos;
67	const u32 sw_rst_bitpos = 12;
68	const u32 sw_rst_mask = 1 << sw_rst_bitpos;
69	int pwrcont = 0x224;
70	int pwrmode = 0x228;
71	u32 read_value;
72
73	read_value = readl((void *)(clkpwr_reg + pwrcont));
74
75	read_value &= ~sw_rst_enb_mask;
76	read_value |= 1 << sw_rst_enb_bitpos;
77
78	writel(read_value, (void *)(clkpwr_reg + pwrcont));
79	writel(sw_rst_mask, (void *)(clkpwr_reg + pwrmode));
80}
81
82void enable_caches(void)
83{
84	/* Enable D-cache. I-cache is already enabled in start.S */
85	dcache_enable();
86}
87