1menu "Functionality shared between NXP SoCs"
2
3config FSL_TRUST_ARCH_v1
4	bool
5
6config NXP_ESBC
7	bool "NXP ESBC (secure boot) functionality"
8	select FSL_TRUST_ARCH_v1 if ARCH_P3041 || ARCH_P4080 || \
9		ARCH_P5040 || ARCH_P2041
10	help
11	  Enable Freescale Secure Boot feature. Normally selected by defconfig.
12	  If unsure, do not change.
13
14menu "Chain of trust / secure boot options"
15	depends on !FIT_SIGNATURE && NXP_ESBC
16
17config CHAIN_OF_TRUST
18	select FSL_CAAM
19	select ARCH_MISC_INIT
20	select FSL_ISBC_KEY_EXT if (ARM || FSL_CORENET) && !SYS_RAMBOOT
21	select FSL_SEC_MON
22	select SPL_BOARD_INIT if (ARM && SPL)
23	select SPL_HASH if (ARM && SPL)
24	select SHA_HW_ACCEL
25	select SHA_PROG_HW_ACCEL
26	select ENV_IS_NOWHERE
27	select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
28	select CMD_EXT4 if ARM
29	select CMD_EXT4_WRITE if ARM
30	imply CMD_BLOB
31	imply CMD_HASH if ARM
32	def_bool y
33
34config CMD_ESBC_VALIDATE
35	bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
36	default y
37	help
38	  This option enables two commands used for secure booting:
39
40	    esbc_validate - validate signature using RSA verification
41	    esbc_halt - put the core in spin loop (Secure Boot Only)
42
43config ESBC_HDR_LS
44	bool
45
46config ESBC_ADDR_64BIT
47	def_bool y
48	depends on FSL_LAYERSCAPE
49	help
50	  For Layerscape based platforms, ESBC image Address in Header is 64bit.
51
52config FSL_ISBC_KEY_EXT
53	bool
54	help
55	  The key used for verification of next level images is picked up from
56	  an Extension Table which has been verified by the ISBC (Internal
57	  Secure boot Code) in boot ROM of the SoC.  The feature is only
58	  applicable in case of NOR boot and is not applicable in case of
59	  RAMBOOT (NAND, SD, SPI).  For Layerscape, this feature is available
60	  for all device if IE Table is copied to XIP memory Also, for
61	  Layerscape, ISBC doesn't verify this table.
62
63config SYS_FSL_SFP_BE
64	def_bool y
65	depends on PPC || FSL_LSCH2 || ARCH_LS1021A
66
67config SYS_FSL_SFP_LE
68	def_bool y
69	depends on !SYS_FSL_SFP_BE
70
71choice
72	prompt "SFP IP revision"
73	default SYS_FSL_SFP_VER_3_0 if PPC
74	default SYS_FSL_SFP_VER_3_4
75
76config SYS_FSL_SFP_VER_3_0
77	bool "SFP version 3.0"
78
79config SYS_FSL_SFP_VER_3_2
80	bool "SFP version 3.2"
81
82config SYS_FSL_SFP_VER_3_4
83	bool "SFP version 3.4"
84
85endchoice
86
87config SPL_UBOOT_KEY_HASH
88	string "Non-SRK key hash for U-Boot public/private key pair"
89	depends on SPL
90	default ""
91	help
92	  Set the key hash for U-Boot here if public/private key pair used to
93	  sign U-Boot are different from the SRK hash put in the fuse.  Example
94	  of a key hash is
95	  41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
96	  Otherwise leave this empty.
97
98if PPC
99
100config BOOTSCRIPT_COPY_RAM
101	bool "Secure boot copies boot script to RAM"
102	help
103	  On systems that support chain of trust booting, a number of addresses
104	  are required to set variables that are used in the copying and then
105	  verification of different parts of the system.  If enabled, the subsequent
106	  options are for what location to use in each step.
107
108config BS_ADDR_DEVICE
109	hex "Address in RAM for bs_device"
110	depends on BOOTSCRIPT_COPY_RAM
111
112config BS_SIZE
113	hex "The size of bs_size which is the amount read from bs_device"
114	depends on BOOTSCRIPT_COPY_RAM
115
116config BS_ADDR_RAM
117	hex "Address in RAM for bs_ram"
118	depends on BOOTSCRIPT_COPY_RAM
119
120config BS_HDR_ADDR_DEVICE
121	hex "Address in RAM for bs_hdr_device"
122	depends on BOOTSCRIPT_COPY_RAM
123
124config BS_HDR_SIZE
125	hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
126	depends on BOOTSCRIPT_COPY_RAM
127
128config BS_HDR_ADDR_RAM
129	hex "Address in RAM for bs_hdr_ram"
130	depends on BOOTSCRIPT_COPY_RAM
131
132config BOOTSCRIPT_HDR_ADDR
133	hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
134	default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM
135
136endif
137
138config SYS_FSL_SRK_LE
139	def_bool y
140	depends on ARM
141
142config KEY_REVOCATION
143	def_bool y
144
145endmenu
146
147config DEEP_SLEEP
148	bool "Enable SoC deep sleep feature"
149	depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
150	default y
151	help
152	  Indicates this SoC supports deep sleep feature. If deep sleep is
153	  supported, core will start to execute uboot when wakes up.
154
155config LAYERSCAPE_NS_ACCESS
156	bool "Layerscape non-secure access support"
157	depends on ARCH_LS1021A || FSL_LSCH2
158
159config PCIE1
160	bool "PCIe controller #1"
161	depends on LAYERSCAPE_NS_ACCESS || PPC
162
163config PCIE2
164	bool "PCIe controller #2"
165	depends on LAYERSCAPE_NS_ACCESS || PPC
166
167config PCIE3
168	bool "PCIe controller #3"
169	depends on LAYERSCAPE_NS_ACCESS || PPC
170
171config PCIE4
172	bool "PCIe controller #4"
173	depends on LAYERSCAPE_NS_ACCESS || PPC
174
175config FSL_USE_PCA9547_MUX
176	bool "Enable PCA9547 I2C Mux on Freescale boards"
177	depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
178	help
179	 This option enables the PCA9547 I2C mux on Freescale boards.
180
181config VID
182	bool "Enable Freescale VID"
183	depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (I2C || DM_I2C)
184	help
185	 This option enables setting core voltage based on individual
186	 values saved in SoC fuses.
187
188config SPL_VID
189	bool "Enable Freescale VID in SPL"
190	depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (SPL_I2C || DM_SPL_I2C)
191	help
192	 This option enables setting core voltage based on individual
193	 values saved in SoC fuses, in SPL.
194
195if VID || SPL_VID
196
197config VID_FLS_ENV
198	string "Environment variable for overriding VDD"
199	help
200	  This option allows for specifying the environment variable
201	  to check to override VDD information.
202
203config VOL_MONITOR_INA220
204	bool "Enable the INA220 voltage monitor read"
205	help
206	  This option enables INA220 voltage monitor read
207	  functionality. It is used by the common VID driver.
208
209config VOL_MONITOR_IR36021_READ
210	bool "Enable the IR36021 voltage monitor read"
211	help
212	 This option enables IR36021 voltage monitor read
213	 functionality. It is used by the common VID driver.
214
215config VOL_MONITOR_IR36021_SET
216	bool "Enable the IR36021 voltage monitor set"
217	help
218	 This option enables IR36021 voltage monitor set
219	 functionality. It is used by the common VID driver.
220
221config VOL_MONITOR_LTC3882_READ
222	bool "Enable the LTC3882 voltage monitor read"
223	help
224	 This option enables LTC3882 voltage monitor read
225	 functionality. It is used by the common VID driver.
226
227config VOL_MONITOR_LTC3882_SET
228	bool "Enable the LTC3882 voltage monitor set"
229	help
230	 This option enables LTC3882 voltage monitor set
231	 functionality. It is used by the common VID driver.
232
233config VOL_MONITOR_ISL68233_READ
234	bool "Enable the ISL68233 voltage monitor read"
235	help
236	 This option enables ISL68233 voltage monitor read
237	 functionality. It is used by the common VID driver.
238
239config VOL_MONITOR_ISL68233_SET
240	bool "Enable the ISL68233 voltage monitor set"
241	help
242	 This option enables ISL68233 voltage monitor set
243	 functionality. It is used by the common VID driver.
244
245endif
246
247config SYS_FSL_NUM_CC_PLLS
248	int "Number of clock control PLLs"
249	depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A
250	default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2
251	default 6 if FSL_LSCH3 || MPC85xx
252
253config SYS_FSL_ESDHC_BE
254	bool
255
256config SYS_FSL_IFC_BE
257	bool
258
259config SYS_FSL_IFC_BANK_COUNT
260	int "Maximum banks of Integrated flash controller"
261	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || \
262		ARCH_LS1088A || ARCH_LS1021A || ARCH_B4860 || ARCH_B4420 || \
263		ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || \
264		ARCH_T2080 || ARCH_C29X || ARCH_P1010 || ARCH_BSC9131 || \
265		ARCH_BSC9132
266	default 3 if ARCH_BSC9131 || ARCH_BSC9132
267	default 4 if ARCH_LS1043A || ARCH_LS1046A || ARCH_B4860 || \
268			ARCH_B4420 || ARCH_P1010
269	default 8 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LS1021A || \
270			ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || \
271			ARCH_T1024 || ARCH_T2080 || ARCH_C29X
272
273config FSL_QIXIS
274	bool "Enable QIXIS support"
275	depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
276
277config QIXIS_I2C_ACCESS
278	bool "Access to QIXIS is over i2c"
279	depends on FSL_QIXIS
280	default y
281
282config HAS_FSL_DR_USB
283	def_bool y
284	depends on USB_EHCI_HCD && PPC
285
286config SYS_DPAA_FMAN
287	bool
288
289config SYS_FSL_SRDS_1
290	bool
291
292config SYS_FSL_SRDS_2
293	bool
294
295config SYS_HAS_SERDES
296	bool
297
298endmenu
299