1// See LICENSE for license details. 2 3#ifndef RISCV_CSR_ENCODING_H 4#define RISCV_CSR_ENCODING_H 5 6#define MSTATUS_UIE 0x00000001 7#define MSTATUS_SIE 0x00000002 8#define MSTATUS_HIE 0x00000004 9#define MSTATUS_MIE 0x00000008 10#define MSTATUS_UPIE 0x00000010 11#define MSTATUS_SPIE 0x00000020 12#define MSTATUS_HPIE 0x00000040 13#define MSTATUS_MPIE 0x00000080 14#define MSTATUS_SPP 0x00000100 15#define MSTATUS_HPP 0x00000600 16#define MSTATUS_MPP 0x00001800 17#define MSTATUS_FS 0x00006000 18#define MSTATUS_XS 0x00018000 19#define MSTATUS_MPRV 0x00020000 20#define MSTATUS_SUM 0x00040000 21#define MSTATUS_MXR 0x00080000 22#define MSTATUS_TVM 0x00100000 23#define MSTATUS_TW 0x00200000 24#define MSTATUS_TSR 0x00400000 25#define MSTATUS32_SD 0x80000000 26#define MSTATUS_UXL 0x0000000300000000 27#define MSTATUS_SXL 0x0000000C00000000 28#define MSTATUS64_SD 0x8000000000000000 29 30/* hypervisr extension bits in mstatus */ 31#define MSTATUS_MTL 0x4000000000ULL 32#define MSTATUS_MPV 0x8000000000ULL 33 34/* hstatus */ 35#define HSTATUS_SP2P 0x100 36#define HSTATUS_SP2V 0x200 37#define HSTATUS_SPV 0x80 38#define HSTATUS_STL 0x40 39 40 41#define SSTATUS_UIE 0x00000001 42#define SSTATUS_SIE 0x00000002 43#define SSTATUS_UPIE 0x00000010 44#define SSTATUS_SPIE 0x00000020 45#define SSTATUS_SPP 0x00000100 46#define SSTATUS_FS 0x00006000 47#define SSTATUS_XS 0x00018000 48#define SSTATUS_SUM 0x00040000 49#define SSTATUS_MXR 0x00080000 50#define SSTATUS32_SD 0x80000000 51#define SSTATUS_UXL 0x0000000300000000 52#define SSTATUS64_SD 0x8000000000000000 53 54#define DCSR_XDEBUGVER (3U<<30) 55#define DCSR_NDRESET (1<<29) 56#define DCSR_FULLRESET (1<<28) 57#define DCSR_EBREAKM (1<<15) 58#define DCSR_EBREAKH (1<<14) 59#define DCSR_EBREAKS (1<<13) 60#define DCSR_EBREAKU (1<<12) 61#define DCSR_STOPCYCLE (1<<10) 62#define DCSR_STOPTIME (1<<9) 63#define DCSR_CAUSE (7<<6) 64#define DCSR_DEBUGINT (1<<5) 65#define DCSR_HALT (1<<3) 66#define DCSR_STEP (1<<2) 67#define DCSR_PRV (3<<0) 68 69#define DCSR_CAUSE_NONE 0 70#define DCSR_CAUSE_SWBP 1 71#define DCSR_CAUSE_HWBP 2 72#define DCSR_CAUSE_DEBUGINT 3 73#define DCSR_CAUSE_STEP 4 74#define DCSR_CAUSE_HALT 5 75 76#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) 77#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) 78#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) 79 80#define MCONTROL_SELECT (1<<19) 81#define MCONTROL_TIMING (1<<18) 82#define MCONTROL_ACTION (0x3f<<12) 83#define MCONTROL_CHAIN (1<<11) 84#define MCONTROL_MATCH (0xf<<7) 85#define MCONTROL_M (1<<6) 86#define MCONTROL_H (1<<5) 87#define MCONTROL_S (1<<4) 88#define MCONTROL_U (1<<3) 89#define MCONTROL_EXECUTE (1<<2) 90#define MCONTROL_STORE (1<<1) 91#define MCONTROL_LOAD (1<<0) 92 93#define MCONTROL_TYPE_NONE 0 94#define MCONTROL_TYPE_MATCH 2 95 96#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 97#define MCONTROL_ACTION_DEBUG_MODE 1 98#define MCONTROL_ACTION_TRACE_START 2 99#define MCONTROL_ACTION_TRACE_STOP 3 100#define MCONTROL_ACTION_TRACE_EMIT 4 101 102#define MCONTROL_MATCH_EQUAL 0 103#define MCONTROL_MATCH_NAPOT 1 104#define MCONTROL_MATCH_GE 2 105#define MCONTROL_MATCH_LT 3 106#define MCONTROL_MATCH_MASK_LOW 4 107#define MCONTROL_MATCH_MASK_HIGH 5 108 109#define MIP_SSIP (1 << IRQ_S_SOFT) 110#define MIP_HSIP (1 << IRQ_H_SOFT) 111#define MIP_MSIP (1 << IRQ_M_SOFT) 112#define MIP_STIP (1 << IRQ_S_TIMER) 113#define MIP_HTIP (1 << IRQ_H_TIMER) 114#define MIP_MTIP (1 << IRQ_M_TIMER) 115#define MIP_SEIP (1 << IRQ_S_EXT) 116#define MIP_HEIP (1 << IRQ_H_EXT) 117#define MIP_MEIP (1 << IRQ_M_EXT) 118 119#define SIP_SSIP MIP_SSIP 120#define SIP_STIP MIP_STIP 121 122#define PRV_U 0 123#define PRV_S 1 124#define PRV_H 2 125#define PRV_M 3 126 127#define SATP32_MODE 0x80000000 128#define SATP32_ASID 0x7FC00000 129#define SATP32_PPN 0x003FFFFF 130#define SATP64_MODE 0xF000000000000000 131#define SATP64_ASID 0x0FFFF00000000000 132#define SATP64_PPN 0x00000FFFFFFFFFFF 133 134#define SATP_MODE_OFF 0 135#define SATP_MODE_SV32 1 136#define SATP_MODE_SV39 8 137#define SATP_MODE_SV48 9 138#define SATP_MODE_SV57 10 139#define SATP_MODE_SV64 11 140 141#define PMP_R 0x01 142#define PMP_W 0x02 143#define PMP_X 0x04 144#define PMP_A 0x18 145#define PMP_L 0x80 146#define PMP_SHIFT 2 147 148#define PMP_TOR 0x08 149#define PMP_NA4 0x10 150#define PMP_NAPOT 0x18 151 152#define IRQ_S_SOFT 1 153#define IRQ_H_SOFT 2 154#define IRQ_M_SOFT 3 155#define IRQ_S_TIMER 5 156#define IRQ_H_TIMER 6 157#define IRQ_M_TIMER 7 158#define IRQ_S_EXT 9 159#define IRQ_H_EXT 10 160#define IRQ_M_EXT 11 161#define IRQ_COP 12 162#define IRQ_HOST 13 163 164#define DEFAULT_RSTVEC 0x00001000 165#define CLINT_BASE 0x02000000 166#define CLINT_SIZE 0x000c0000 167#define EXT_IO_BASE 0x40000000 168#define DRAM_BASE 0x80000000 169 170// page table entry (PTE) fields 171#define PTE_V 0x001 // Valid 172#define PTE_R 0x002 // Read 173#define PTE_W 0x004 // Write 174#define PTE_X 0x008 // Execute 175#define PTE_U 0x010 // User 176#define PTE_G 0x020 // Global 177#define PTE_A 0x040 // Accessed 178#define PTE_D 0x080 // Dirty 179#define PTE_SOFT 0x300 // Reserved for Software 180 181#define PTE_PPN_SHIFT 10 182 183#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) 184 185#ifdef __riscv 186 187#if __riscv_xlen == 64 188# define MSTATUS_SD MSTATUS64_SD 189# define SSTATUS_SD SSTATUS64_SD 190# define RISCV_PGLEVEL_BITS 9 191# define SATP_MODE SATP64_MODE 192#else 193# define MSTATUS_SD MSTATUS32_SD 194# define SSTATUS_SD SSTATUS32_SD 195# define RISCV_PGLEVEL_BITS 10 196# define SATP_MODE SATP32_MODE 197#endif 198#define RISCV_PGSHIFT 12 199#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) 200 201#ifndef __ASSEMBLER__ 202 203#ifdef __GNUC__ 204 205#define read_csr(reg) ({ unsigned long __tmp; \ 206 asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 207 __tmp; }) 208 209#define write_csr(reg, val) ({ \ 210 asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) 211 212#define swap_csr(reg, val) ({ unsigned long __tmp; \ 213 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ 214 __tmp; }) 215 216#define set_csr(reg, bit) ({ unsigned long __tmp; \ 217 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ 218 __tmp; }) 219 220#define clear_csr(reg, bit) ({ unsigned long __tmp; \ 221 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ 222 __tmp; }) 223 224#define rdtime() read_csr(time) 225#define rdcycle() read_csr(cycle) 226#define rdinstret() read_csr(instret) 227 228#endif 229 230#endif 231 232#endif 233 234#endif 235/* Automatically generated by parse-opcodes. */ 236#ifndef RISCV_ENCODING_H 237#define RISCV_ENCODING_H 238#define MATCH_BEQ 0x63 239#define MASK_BEQ 0x707f 240#define MATCH_BNE 0x1063 241#define MASK_BNE 0x707f 242#define MATCH_BLT 0x4063 243#define MASK_BLT 0x707f 244#define MATCH_BGE 0x5063 245#define MASK_BGE 0x707f 246#define MATCH_BLTU 0x6063 247#define MASK_BLTU 0x707f 248#define MATCH_BGEU 0x7063 249#define MASK_BGEU 0x707f 250#define MATCH_JALR 0x67 251#define MASK_JALR 0x707f 252#define MATCH_JAL 0x6f 253#define MASK_JAL 0x7f 254#define MATCH_LUI 0x37 255#define MASK_LUI 0x7f 256#define MATCH_AUIPC 0x17 257#define MASK_AUIPC 0x7f 258#define MATCH_ADDI 0x13 259#define MASK_ADDI 0x707f 260#define MATCH_SLLI 0x1013 261#define MASK_SLLI 0xfc00707f 262#define MATCH_SLTI 0x2013 263#define MASK_SLTI 0x707f 264#define MATCH_SLTIU 0x3013 265#define MASK_SLTIU 0x707f 266#define MATCH_XORI 0x4013 267#define MASK_XORI 0x707f 268#define MATCH_SRLI 0x5013 269#define MASK_SRLI 0xfc00707f 270#define MATCH_SRAI 0x40005013 271#define MASK_SRAI 0xfc00707f 272#define MATCH_ORI 0x6013 273#define MASK_ORI 0x707f 274#define MATCH_ANDI 0x7013 275#define MASK_ANDI 0x707f 276#define MATCH_ADD 0x33 277#define MASK_ADD 0xfe00707f 278#define MATCH_SUB 0x40000033 279#define MASK_SUB 0xfe00707f 280#define MATCH_SLL 0x1033 281#define MASK_SLL 0xfe00707f 282#define MATCH_SLT 0x2033 283#define MASK_SLT 0xfe00707f 284#define MATCH_SLTU 0x3033 285#define MASK_SLTU 0xfe00707f 286#define MATCH_XOR 0x4033 287#define MASK_XOR 0xfe00707f 288#define MATCH_SRL 0x5033 289#define MASK_SRL 0xfe00707f 290#define MATCH_SRA 0x40005033 291#define MASK_SRA 0xfe00707f 292#define MATCH_OR 0x6033 293#define MASK_OR 0xfe00707f 294#define MATCH_AND 0x7033 295#define MASK_AND 0xfe00707f 296#define MATCH_ADDIW 0x1b 297#define MASK_ADDIW 0x707f 298#define MATCH_SLLIW 0x101b 299#define MASK_SLLIW 0xfe00707f 300#define MATCH_SRLIW 0x501b 301#define MASK_SRLIW 0xfe00707f 302#define MATCH_SRAIW 0x4000501b 303#define MASK_SRAIW 0xfe00707f 304#define MATCH_ADDW 0x3b 305#define MASK_ADDW 0xfe00707f 306#define MATCH_SUBW 0x4000003b 307#define MASK_SUBW 0xfe00707f 308#define MATCH_SLLW 0x103b 309#define MASK_SLLW 0xfe00707f 310#define MATCH_SRLW 0x503b 311#define MASK_SRLW 0xfe00707f 312#define MATCH_SRAW 0x4000503b 313#define MASK_SRAW 0xfe00707f 314#define MATCH_LB 0x3 315#define MASK_LB 0x707f 316#define MATCH_LH 0x1003 317#define MASK_LH 0x707f 318#define MATCH_LW 0x2003 319#define MASK_LW 0x707f 320#define MATCH_LD 0x3003 321#define MASK_LD 0x707f 322#define MATCH_LBU 0x4003 323#define MASK_LBU 0x707f 324#define MATCH_LHU 0x5003 325#define MASK_LHU 0x707f 326#define MATCH_LWU 0x6003 327#define MASK_LWU 0x707f 328#define MATCH_SB 0x23 329#define MASK_SB 0x707f 330#define MATCH_SH 0x1023 331#define MASK_SH 0x707f 332#define MATCH_SW 0x2023 333#define MASK_SW 0x707f 334#define MATCH_SD 0x3023 335#define MASK_SD 0x707f 336#define MATCH_FENCE 0xf 337#define MASK_FENCE 0x707f 338#define MATCH_FENCE_I 0x100f 339#define MASK_FENCE_I 0x707f 340#define MATCH_MUL 0x2000033 341#define MASK_MUL 0xfe00707f 342#define MATCH_MULH 0x2001033 343#define MASK_MULH 0xfe00707f 344#define MATCH_MULHSU 0x2002033 345#define MASK_MULHSU 0xfe00707f 346#define MATCH_MULHU 0x2003033 347#define MASK_MULHU 0xfe00707f 348#define MATCH_DIV 0x2004033 349#define MASK_DIV 0xfe00707f 350#define MATCH_DIVU 0x2005033 351#define MASK_DIVU 0xfe00707f 352#define MATCH_REM 0x2006033 353#define MASK_REM 0xfe00707f 354#define MATCH_REMU 0x2007033 355#define MASK_REMU 0xfe00707f 356#define MATCH_MULW 0x200003b 357#define MASK_MULW 0xfe00707f 358#define MATCH_DIVW 0x200403b 359#define MASK_DIVW 0xfe00707f 360#define MATCH_DIVUW 0x200503b 361#define MASK_DIVUW 0xfe00707f 362#define MATCH_REMW 0x200603b 363#define MASK_REMW 0xfe00707f 364#define MATCH_REMUW 0x200703b 365#define MASK_REMUW 0xfe00707f 366#define MATCH_AMOADD_W 0x202f 367#define MASK_AMOADD_W 0xf800707f 368#define MATCH_AMOXOR_W 0x2000202f 369#define MASK_AMOXOR_W 0xf800707f 370#define MATCH_AMOOR_W 0x4000202f 371#define MASK_AMOOR_W 0xf800707f 372#define MATCH_AMOAND_W 0x6000202f 373#define MASK_AMOAND_W 0xf800707f 374#define MATCH_AMOMIN_W 0x8000202f 375#define MASK_AMOMIN_W 0xf800707f 376#define MATCH_AMOMAX_W 0xa000202f 377#define MASK_AMOMAX_W 0xf800707f 378#define MATCH_AMOMINU_W 0xc000202f 379#define MASK_AMOMINU_W 0xf800707f 380#define MATCH_AMOMAXU_W 0xe000202f 381#define MASK_AMOMAXU_W 0xf800707f 382#define MATCH_AMOSWAP_W 0x800202f 383#define MASK_AMOSWAP_W 0xf800707f 384#define MATCH_LR_W 0x1000202f 385#define MASK_LR_W 0xf9f0707f 386#define MATCH_SC_W 0x1800202f 387#define MASK_SC_W 0xf800707f 388#define MATCH_AMOADD_D 0x302f 389#define MASK_AMOADD_D 0xf800707f 390#define MATCH_AMOXOR_D 0x2000302f 391#define MASK_AMOXOR_D 0xf800707f 392#define MATCH_AMOOR_D 0x4000302f 393#define MASK_AMOOR_D 0xf800707f 394#define MATCH_AMOAND_D 0x6000302f 395#define MASK_AMOAND_D 0xf800707f 396#define MATCH_AMOMIN_D 0x8000302f 397#define MASK_AMOMIN_D 0xf800707f 398#define MATCH_AMOMAX_D 0xa000302f 399#define MASK_AMOMAX_D 0xf800707f 400#define MATCH_AMOMINU_D 0xc000302f 401#define MASK_AMOMINU_D 0xf800707f 402#define MATCH_AMOMAXU_D 0xe000302f 403#define MASK_AMOMAXU_D 0xf800707f 404#define MATCH_AMOSWAP_D 0x800302f 405#define MASK_AMOSWAP_D 0xf800707f 406#define MATCH_LR_D 0x1000302f 407#define MASK_LR_D 0xf9f0707f 408#define MATCH_SC_D 0x1800302f 409#define MASK_SC_D 0xf800707f 410#define MATCH_ECALL 0x73 411#define MASK_ECALL 0xffffffff 412#define MATCH_EBREAK 0x100073 413#define MASK_EBREAK 0xffffffff 414#define MATCH_URET 0x200073 415#define MASK_URET 0xffffffff 416#define MATCH_SRET 0x10200073 417#define MASK_SRET 0xffffffff 418#define MATCH_MRET 0x30200073 419#define MASK_MRET 0xffffffff 420#define MATCH_DRET 0x7b200073 421#define MASK_DRET 0xffffffff 422#define MATCH_SFENCE_VMA 0x12000073 423#define MASK_SFENCE_VMA 0xfe007fff 424#define MATCH_WFI 0x10500073 425#define MASK_WFI 0xffffffff 426#define MATCH_CSRRW 0x1073 427#define MASK_CSRRW 0x707f 428#define MATCH_CSRRS 0x2073 429#define MASK_CSRRS 0x707f 430#define MATCH_CSRRC 0x3073 431#define MASK_CSRRC 0x707f 432#define MATCH_CSRRWI 0x5073 433#define MASK_CSRRWI 0x707f 434#define MATCH_CSRRSI 0x6073 435#define MASK_CSRRSI 0x707f 436#define MATCH_CSRRCI 0x7073 437#define MASK_CSRRCI 0x707f 438#define MATCH_FADD_S 0x53 439#define MASK_FADD_S 0xfe00007f 440#define MATCH_FSUB_S 0x8000053 441#define MASK_FSUB_S 0xfe00007f 442#define MATCH_FMUL_S 0x10000053 443#define MASK_FMUL_S 0xfe00007f 444#define MATCH_FDIV_S 0x18000053 445#define MASK_FDIV_S 0xfe00007f 446#define MATCH_FSGNJ_S 0x20000053 447#define MASK_FSGNJ_S 0xfe00707f 448#define MATCH_FSGNJN_S 0x20001053 449#define MASK_FSGNJN_S 0xfe00707f 450#define MATCH_FSGNJX_S 0x20002053 451#define MASK_FSGNJX_S 0xfe00707f 452#define MATCH_FMIN_S 0x28000053 453#define MASK_FMIN_S 0xfe00707f 454#define MATCH_FMAX_S 0x28001053 455#define MASK_FMAX_S 0xfe00707f 456#define MATCH_FSQRT_S 0x58000053 457#define MASK_FSQRT_S 0xfff0007f 458#define MATCH_FADD_D 0x2000053 459#define MASK_FADD_D 0xfe00007f 460#define MATCH_FSUB_D 0xa000053 461#define MASK_FSUB_D 0xfe00007f 462#define MATCH_FMUL_D 0x12000053 463#define MASK_FMUL_D 0xfe00007f 464#define MATCH_FDIV_D 0x1a000053 465#define MASK_FDIV_D 0xfe00007f 466#define MATCH_FSGNJ_D 0x22000053 467#define MASK_FSGNJ_D 0xfe00707f 468#define MATCH_FSGNJN_D 0x22001053 469#define MASK_FSGNJN_D 0xfe00707f 470#define MATCH_FSGNJX_D 0x22002053 471#define MASK_FSGNJX_D 0xfe00707f 472#define MATCH_FMIN_D 0x2a000053 473#define MASK_FMIN_D 0xfe00707f 474#define MATCH_FMAX_D 0x2a001053 475#define MASK_FMAX_D 0xfe00707f 476#define MATCH_FCVT_S_D 0x40100053 477#define MASK_FCVT_S_D 0xfff0007f 478#define MATCH_FCVT_D_S 0x42000053 479#define MASK_FCVT_D_S 0xfff0007f 480#define MATCH_FSQRT_D 0x5a000053 481#define MASK_FSQRT_D 0xfff0007f 482#define MATCH_FADD_Q 0x6000053 483#define MASK_FADD_Q 0xfe00007f 484#define MATCH_FSUB_Q 0xe000053 485#define MASK_FSUB_Q 0xfe00007f 486#define MATCH_FMUL_Q 0x16000053 487#define MASK_FMUL_Q 0xfe00007f 488#define MATCH_FDIV_Q 0x1e000053 489#define MASK_FDIV_Q 0xfe00007f 490#define MATCH_FSGNJ_Q 0x26000053 491#define MASK_FSGNJ_Q 0xfe00707f 492#define MATCH_FSGNJN_Q 0x26001053 493#define MASK_FSGNJN_Q 0xfe00707f 494#define MATCH_FSGNJX_Q 0x26002053 495#define MASK_FSGNJX_Q 0xfe00707f 496#define MATCH_FMIN_Q 0x2e000053 497#define MASK_FMIN_Q 0xfe00707f 498#define MATCH_FMAX_Q 0x2e001053 499#define MASK_FMAX_Q 0xfe00707f 500#define MATCH_FCVT_S_Q 0x40300053 501#define MASK_FCVT_S_Q 0xfff0007f 502#define MATCH_FCVT_Q_S 0x46000053 503#define MASK_FCVT_Q_S 0xfff0007f 504#define MATCH_FCVT_D_Q 0x42300053 505#define MASK_FCVT_D_Q 0xfff0007f 506#define MATCH_FCVT_Q_D 0x46100053 507#define MASK_FCVT_Q_D 0xfff0007f 508#define MATCH_FSQRT_Q 0x5e000053 509#define MASK_FSQRT_Q 0xfff0007f 510#define MATCH_FLE_S 0xa0000053 511#define MASK_FLE_S 0xfe00707f 512#define MATCH_FLT_S 0xa0001053 513#define MASK_FLT_S 0xfe00707f 514#define MATCH_FEQ_S 0xa0002053 515#define MASK_FEQ_S 0xfe00707f 516#define MATCH_FLE_D 0xa2000053 517#define MASK_FLE_D 0xfe00707f 518#define MATCH_FLT_D 0xa2001053 519#define MASK_FLT_D 0xfe00707f 520#define MATCH_FEQ_D 0xa2002053 521#define MASK_FEQ_D 0xfe00707f 522#define MATCH_FLE_Q 0xa6000053 523#define MASK_FLE_Q 0xfe00707f 524#define MATCH_FLT_Q 0xa6001053 525#define MASK_FLT_Q 0xfe00707f 526#define MATCH_FEQ_Q 0xa6002053 527#define MASK_FEQ_Q 0xfe00707f 528#define MATCH_FCVT_W_S 0xc0000053 529#define MASK_FCVT_W_S 0xfff0007f 530#define MATCH_FCVT_WU_S 0xc0100053 531#define MASK_FCVT_WU_S 0xfff0007f 532#define MATCH_FCVT_L_S 0xc0200053 533#define MASK_FCVT_L_S 0xfff0007f 534#define MATCH_FCVT_LU_S 0xc0300053 535#define MASK_FCVT_LU_S 0xfff0007f 536#define MATCH_FMV_X_W 0xe0000053 537#define MASK_FMV_X_W 0xfff0707f 538#define MATCH_FCLASS_S 0xe0001053 539#define MASK_FCLASS_S 0xfff0707f 540#define MATCH_FCVT_W_D 0xc2000053 541#define MASK_FCVT_W_D 0xfff0007f 542#define MATCH_FCVT_WU_D 0xc2100053 543#define MASK_FCVT_WU_D 0xfff0007f 544#define MATCH_FCVT_L_D 0xc2200053 545#define MASK_FCVT_L_D 0xfff0007f 546#define MATCH_FCVT_LU_D 0xc2300053 547#define MASK_FCVT_LU_D 0xfff0007f 548#define MATCH_FMV_X_D 0xe2000053 549#define MASK_FMV_X_D 0xfff0707f 550#define MATCH_FCLASS_D 0xe2001053 551#define MASK_FCLASS_D 0xfff0707f 552#define MATCH_FCVT_W_Q 0xc6000053 553#define MASK_FCVT_W_Q 0xfff0007f 554#define MATCH_FCVT_WU_Q 0xc6100053 555#define MASK_FCVT_WU_Q 0xfff0007f 556#define MATCH_FCVT_L_Q 0xc6200053 557#define MASK_FCVT_L_Q 0xfff0007f 558#define MATCH_FCVT_LU_Q 0xc6300053 559#define MASK_FCVT_LU_Q 0xfff0007f 560#define MATCH_FMV_X_Q 0xe6000053 561#define MASK_FMV_X_Q 0xfff0707f 562#define MATCH_FCLASS_Q 0xe6001053 563#define MASK_FCLASS_Q 0xfff0707f 564#define MATCH_FCVT_S_W 0xd0000053 565#define MASK_FCVT_S_W 0xfff0007f 566#define MATCH_FCVT_S_WU 0xd0100053 567#define MASK_FCVT_S_WU 0xfff0007f 568#define MATCH_FCVT_S_L 0xd0200053 569#define MASK_FCVT_S_L 0xfff0007f 570#define MATCH_FCVT_S_LU 0xd0300053 571#define MASK_FCVT_S_LU 0xfff0007f 572#define MATCH_FMV_W_X 0xf0000053 573#define MASK_FMV_W_X 0xfff0707f 574#define MATCH_FCVT_D_W 0xd2000053 575#define MASK_FCVT_D_W 0xfff0007f 576#define MATCH_FCVT_D_WU 0xd2100053 577#define MASK_FCVT_D_WU 0xfff0007f 578#define MATCH_FCVT_D_L 0xd2200053 579#define MASK_FCVT_D_L 0xfff0007f 580#define MATCH_FCVT_D_LU 0xd2300053 581#define MASK_FCVT_D_LU 0xfff0007f 582#define MATCH_FMV_D_X 0xf2000053 583#define MASK_FMV_D_X 0xfff0707f 584#define MATCH_FCVT_Q_W 0xd6000053 585#define MASK_FCVT_Q_W 0xfff0007f 586#define MATCH_FCVT_Q_WU 0xd6100053 587#define MASK_FCVT_Q_WU 0xfff0007f 588#define MATCH_FCVT_Q_L 0xd6200053 589#define MASK_FCVT_Q_L 0xfff0007f 590#define MATCH_FCVT_Q_LU 0xd6300053 591#define MASK_FCVT_Q_LU 0xfff0007f 592#define MATCH_FMV_Q_X 0xf6000053 593#define MASK_FMV_Q_X 0xfff0707f 594#define MATCH_FLW 0x2007 595#define MASK_FLW 0x707f 596#define MATCH_FLD 0x3007 597#define MASK_FLD 0x707f 598#define MATCH_FLQ 0x4007 599#define MASK_FLQ 0x707f 600#define MATCH_FSW 0x2027 601#define MASK_FSW 0x707f 602#define MATCH_FSD 0x3027 603#define MASK_FSD 0x707f 604#define MATCH_FSQ 0x4027 605#define MASK_FSQ 0x707f 606#define MATCH_FMADD_S 0x43 607#define MASK_FMADD_S 0x600007f 608#define MATCH_FMSUB_S 0x47 609#define MASK_FMSUB_S 0x600007f 610#define MATCH_FNMSUB_S 0x4b 611#define MASK_FNMSUB_S 0x600007f 612#define MATCH_FNMADD_S 0x4f 613#define MASK_FNMADD_S 0x600007f 614#define MATCH_FMADD_D 0x2000043 615#define MASK_FMADD_D 0x600007f 616#define MATCH_FMSUB_D 0x2000047 617#define MASK_FMSUB_D 0x600007f 618#define MATCH_FNMSUB_D 0x200004b 619#define MASK_FNMSUB_D 0x600007f 620#define MATCH_FNMADD_D 0x200004f 621#define MASK_FNMADD_D 0x600007f 622#define MATCH_FMADD_Q 0x6000043 623#define MASK_FMADD_Q 0x600007f 624#define MATCH_FMSUB_Q 0x6000047 625#define MASK_FMSUB_Q 0x600007f 626#define MATCH_FNMSUB_Q 0x600004b 627#define MASK_FNMSUB_Q 0x600007f 628#define MATCH_FNMADD_Q 0x600004f 629#define MASK_FNMADD_Q 0x600007f 630#define MATCH_C_NOP 0x1 631#define MASK_C_NOP 0xffff 632#define MATCH_C_ADDI16SP 0x6101 633#define MASK_C_ADDI16SP 0xef83 634#define MATCH_C_JR 0x8002 635#define MASK_C_JR 0xf07f 636#define MATCH_C_JALR 0x9002 637#define MASK_C_JALR 0xf07f 638#define MATCH_C_EBREAK 0x9002 639#define MASK_C_EBREAK 0xffff 640#define MATCH_C_LD 0x6000 641#define MASK_C_LD 0xe003 642#define MATCH_C_SD 0xe000 643#define MASK_C_SD 0xe003 644#define MATCH_C_ADDIW 0x2001 645#define MASK_C_ADDIW 0xe003 646#define MATCH_C_LDSP 0x6002 647#define MASK_C_LDSP 0xe003 648#define MATCH_C_SDSP 0xe002 649#define MASK_C_SDSP 0xe003 650#define MATCH_C_ADDI4SPN 0x0 651#define MASK_C_ADDI4SPN 0xe003 652#define MATCH_C_FLD 0x2000 653#define MASK_C_FLD 0xe003 654#define MATCH_C_LW 0x4000 655#define MASK_C_LW 0xe003 656#define MATCH_C_FLW 0x6000 657#define MASK_C_FLW 0xe003 658#define MATCH_C_FSD 0xa000 659#define MASK_C_FSD 0xe003 660#define MATCH_C_SW 0xc000 661#define MASK_C_SW 0xe003 662#define MATCH_C_FSW 0xe000 663#define MASK_C_FSW 0xe003 664#define MATCH_C_ADDI 0x1 665#define MASK_C_ADDI 0xe003 666#define MATCH_C_JAL 0x2001 667#define MASK_C_JAL 0xe003 668#define MATCH_C_LI 0x4001 669#define MASK_C_LI 0xe003 670#define MATCH_C_LUI 0x6001 671#define MASK_C_LUI 0xe003 672#define MATCH_C_SRLI 0x8001 673#define MASK_C_SRLI 0xec03 674#define MATCH_C_SRAI 0x8401 675#define MASK_C_SRAI 0xec03 676#define MATCH_C_ANDI 0x8801 677#define MASK_C_ANDI 0xec03 678#define MATCH_C_SUB 0x8c01 679#define MASK_C_SUB 0xfc63 680#define MATCH_C_XOR 0x8c21 681#define MASK_C_XOR 0xfc63 682#define MATCH_C_OR 0x8c41 683#define MASK_C_OR 0xfc63 684#define MATCH_C_AND 0x8c61 685#define MASK_C_AND 0xfc63 686#define MATCH_C_SUBW 0x9c01 687#define MASK_C_SUBW 0xfc63 688#define MATCH_C_ADDW 0x9c21 689#define MASK_C_ADDW 0xfc63 690#define MATCH_C_J 0xa001 691#define MASK_C_J 0xe003 692#define MATCH_C_BEQZ 0xc001 693#define MASK_C_BEQZ 0xe003 694#define MATCH_C_BNEZ 0xe001 695#define MASK_C_BNEZ 0xe003 696#define MATCH_C_SLLI 0x2 697#define MASK_C_SLLI 0xe003 698#define MATCH_C_FLDSP 0x2002 699#define MASK_C_FLDSP 0xe003 700#define MATCH_C_LWSP 0x4002 701#define MASK_C_LWSP 0xe003 702#define MATCH_C_FLWSP 0x6002 703#define MASK_C_FLWSP 0xe003 704#define MATCH_C_MV 0x8002 705#define MASK_C_MV 0xf003 706#define MATCH_C_ADD 0x9002 707#define MASK_C_ADD 0xf003 708#define MATCH_C_FSDSP 0xa002 709#define MASK_C_FSDSP 0xe003 710#define MATCH_C_SWSP 0xc002 711#define MASK_C_SWSP 0xe003 712#define MATCH_C_FSWSP 0xe002 713#define MASK_C_FSWSP 0xe003 714#define MATCH_CUSTOM0 0xb 715#define MASK_CUSTOM0 0x707f 716#define MATCH_CUSTOM0_RS1 0x200b 717#define MASK_CUSTOM0_RS1 0x707f 718#define MATCH_CUSTOM0_RS1_RS2 0x300b 719#define MASK_CUSTOM0_RS1_RS2 0x707f 720#define MATCH_CUSTOM0_RD 0x400b 721#define MASK_CUSTOM0_RD 0x707f 722#define MATCH_CUSTOM0_RD_RS1 0x600b 723#define MASK_CUSTOM0_RD_RS1 0x707f 724#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b 725#define MASK_CUSTOM0_RD_RS1_RS2 0x707f 726#define MATCH_CUSTOM1 0x2b 727#define MASK_CUSTOM1 0x707f 728#define MATCH_CUSTOM1_RS1 0x202b 729#define MASK_CUSTOM1_RS1 0x707f 730#define MATCH_CUSTOM1_RS1_RS2 0x302b 731#define MASK_CUSTOM1_RS1_RS2 0x707f 732#define MATCH_CUSTOM1_RD 0x402b 733#define MASK_CUSTOM1_RD 0x707f 734#define MATCH_CUSTOM1_RD_RS1 0x602b 735#define MASK_CUSTOM1_RD_RS1 0x707f 736#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b 737#define MASK_CUSTOM1_RD_RS1_RS2 0x707f 738#define MATCH_CUSTOM2 0x5b 739#define MASK_CUSTOM2 0x707f 740#define MATCH_CUSTOM2_RS1 0x205b 741#define MASK_CUSTOM2_RS1 0x707f 742#define MATCH_CUSTOM2_RS1_RS2 0x305b 743#define MASK_CUSTOM2_RS1_RS2 0x707f 744#define MATCH_CUSTOM2_RD 0x405b 745#define MASK_CUSTOM2_RD 0x707f 746#define MATCH_CUSTOM2_RD_RS1 0x605b 747#define MASK_CUSTOM2_RD_RS1 0x707f 748#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b 749#define MASK_CUSTOM2_RD_RS1_RS2 0x707f 750#define MATCH_CUSTOM3 0x7b 751#define MASK_CUSTOM3 0x707f 752#define MATCH_CUSTOM3_RS1 0x207b 753#define MASK_CUSTOM3_RS1 0x707f 754#define MATCH_CUSTOM3_RS1_RS2 0x307b 755#define MASK_CUSTOM3_RS1_RS2 0x707f 756#define MATCH_CUSTOM3_RD 0x407b 757#define MASK_CUSTOM3_RD 0x707f 758#define MATCH_CUSTOM3_RD_RS1 0x607b 759#define MASK_CUSTOM3_RD_RS1 0x707f 760#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b 761#define MASK_CUSTOM3_RD_RS1_RS2 0x707f 762#define CSR_FFLAGS 0x1 763#define CSR_FRM 0x2 764#define CSR_FCSR 0x3 765#define CSR_CYCLE 0xc00 766#define CSR_TIME 0xc01 767#define CSR_INSTRET 0xc02 768#define CSR_HPMCOUNTER3 0xc03 769#define CSR_HPMCOUNTER4 0xc04 770#define CSR_HPMCOUNTER5 0xc05 771#define CSR_HPMCOUNTER6 0xc06 772#define CSR_HPMCOUNTER7 0xc07 773#define CSR_HPMCOUNTER8 0xc08 774#define CSR_HPMCOUNTER9 0xc09 775#define CSR_HPMCOUNTER10 0xc0a 776#define CSR_HPMCOUNTER11 0xc0b 777#define CSR_HPMCOUNTER12 0xc0c 778#define CSR_HPMCOUNTER13 0xc0d 779#define CSR_HPMCOUNTER14 0xc0e 780#define CSR_HPMCOUNTER15 0xc0f 781#define CSR_HPMCOUNTER16 0xc10 782#define CSR_HPMCOUNTER17 0xc11 783#define CSR_HPMCOUNTER18 0xc12 784#define CSR_HPMCOUNTER19 0xc13 785#define CSR_HPMCOUNTER20 0xc14 786#define CSR_HPMCOUNTER21 0xc15 787#define CSR_HPMCOUNTER22 0xc16 788#define CSR_HPMCOUNTER23 0xc17 789#define CSR_HPMCOUNTER24 0xc18 790#define CSR_HPMCOUNTER25 0xc19 791#define CSR_HPMCOUNTER26 0xc1a 792#define CSR_HPMCOUNTER27 0xc1b 793#define CSR_HPMCOUNTER28 0xc1c 794#define CSR_HPMCOUNTER29 0xc1d 795#define CSR_HPMCOUNTER30 0xc1e 796#define CSR_HPMCOUNTER31 0xc1f 797#define CSR_SSTATUS 0x100 798#define CSR_SIE 0x104 799#define CSR_STVEC 0x105 800#define CSR_SCOUNTEREN 0x106 801#define CSR_SSCRATCH 0x140 802#define CSR_SEPC 0x141 803#define CSR_SCAUSE 0x142 804#define CSR_STVAL 0x143 805#define CSR_SIP 0x144 806#define CSR_SATP 0x180 807#define CSR_MSTATUS 0x300 808#define CSR_MISA 0x301 809#define CSR_MEDELEG 0x302 810#define CSR_MIDELEG 0x303 811#define CSR_MIE 0x304 812#define CSR_MTVEC 0x305 813#define CSR_MCOUNTEREN 0x306 814#define CSR_MSCRATCH 0x340 815#define CSR_MEPC 0x341 816#define CSR_MCAUSE 0x342 817#define CSR_MTVAL 0x343 818#define CSR_MIP 0x344 819#define CSR_PMPCFG0 0x3a0 820#define CSR_PMPCFG1 0x3a1 821#define CSR_PMPCFG2 0x3a2 822#define CSR_PMPCFG3 0x3a3 823#define CSR_PMPADDR0 0x3b0 824#define CSR_PMPADDR1 0x3b1 825#define CSR_PMPADDR2 0x3b2 826#define CSR_PMPADDR3 0x3b3 827#define CSR_PMPADDR4 0x3b4 828#define CSR_PMPADDR5 0x3b5 829#define CSR_PMPADDR6 0x3b6 830#define CSR_PMPADDR7 0x3b7 831#define CSR_PMPADDR8 0x3b8 832#define CSR_PMPADDR9 0x3b9 833#define CSR_PMPADDR10 0x3ba 834#define CSR_PMPADDR11 0x3bb 835#define CSR_PMPADDR12 0x3bc 836#define CSR_PMPADDR13 0x3bd 837#define CSR_PMPADDR14 0x3be 838#define CSR_PMPADDR15 0x3bf 839#define CSR_TSELECT 0x7a0 840#define CSR_TDATA1 0x7a1 841#define CSR_TDATA2 0x7a2 842#define CSR_TDATA3 0x7a3 843#define CSR_DCSR 0x7b0 844#define CSR_DPC 0x7b1 845#define CSR_DSCRATCH 0x7b2 846#define CSR_MCYCLE 0xb00 847#define CSR_MINSTRET 0xb02 848#define CSR_MHPMCOUNTER3 0xb03 849#define CSR_MHPMCOUNTER4 0xb04 850#define CSR_MHPMCOUNTER5 0xb05 851#define CSR_MHPMCOUNTER6 0xb06 852#define CSR_MHPMCOUNTER7 0xb07 853#define CSR_MHPMCOUNTER8 0xb08 854#define CSR_MHPMCOUNTER9 0xb09 855#define CSR_MHPMCOUNTER10 0xb0a 856#define CSR_MHPMCOUNTER11 0xb0b 857#define CSR_MHPMCOUNTER12 0xb0c 858#define CSR_MHPMCOUNTER13 0xb0d 859#define CSR_MHPMCOUNTER14 0xb0e 860#define CSR_MHPMCOUNTER15 0xb0f 861#define CSR_MHPMCOUNTER16 0xb10 862#define CSR_MHPMCOUNTER17 0xb11 863#define CSR_MHPMCOUNTER18 0xb12 864#define CSR_MHPMCOUNTER19 0xb13 865#define CSR_MHPMCOUNTER20 0xb14 866#define CSR_MHPMCOUNTER21 0xb15 867#define CSR_MHPMCOUNTER22 0xb16 868#define CSR_MHPMCOUNTER23 0xb17 869#define CSR_MHPMCOUNTER24 0xb18 870#define CSR_MHPMCOUNTER25 0xb19 871#define CSR_MHPMCOUNTER26 0xb1a 872#define CSR_MHPMCOUNTER27 0xb1b 873#define CSR_MHPMCOUNTER28 0xb1c 874#define CSR_MHPMCOUNTER29 0xb1d 875#define CSR_MHPMCOUNTER30 0xb1e 876#define CSR_MHPMCOUNTER31 0xb1f 877#define CSR_MHPMEVENT3 0x323 878#define CSR_MHPMEVENT4 0x324 879#define CSR_MHPMEVENT5 0x325 880#define CSR_MHPMEVENT6 0x326 881#define CSR_MHPMEVENT7 0x327 882#define CSR_MHPMEVENT8 0x328 883#define CSR_MHPMEVENT9 0x329 884#define CSR_MHPMEVENT10 0x32a 885#define CSR_MHPMEVENT11 0x32b 886#define CSR_MHPMEVENT12 0x32c 887#define CSR_MHPMEVENT13 0x32d 888#define CSR_MHPMEVENT14 0x32e 889#define CSR_MHPMEVENT15 0x32f 890#define CSR_MHPMEVENT16 0x330 891#define CSR_MHPMEVENT17 0x331 892#define CSR_MHPMEVENT18 0x332 893#define CSR_MHPMEVENT19 0x333 894#define CSR_MHPMEVENT20 0x334 895#define CSR_MHPMEVENT21 0x335 896#define CSR_MHPMEVENT22 0x336 897#define CSR_MHPMEVENT23 0x337 898#define CSR_MHPMEVENT24 0x338 899#define CSR_MHPMEVENT25 0x339 900#define CSR_MHPMEVENT26 0x33a 901#define CSR_MHPMEVENT27 0x33b 902#define CSR_MHPMEVENT28 0x33c 903#define CSR_MHPMEVENT29 0x33d 904#define CSR_MHPMEVENT30 0x33e 905#define CSR_MHPMEVENT31 0x33f 906#define CSR_MVENDORID 0xf11 907#define CSR_MARCHID 0xf12 908#define CSR_MIMPID 0xf13 909#define CSR_MHARTID 0xf14 910#define CSR_CYCLEH 0xc80 911#define CSR_TIMEH 0xc81 912#define CSR_INSTRETH 0xc82 913#define CSR_HPMCOUNTER3H 0xc83 914#define CSR_HPMCOUNTER4H 0xc84 915#define CSR_HPMCOUNTER5H 0xc85 916#define CSR_HPMCOUNTER6H 0xc86 917#define CSR_HPMCOUNTER7H 0xc87 918#define CSR_HPMCOUNTER8H 0xc88 919#define CSR_HPMCOUNTER9H 0xc89 920#define CSR_HPMCOUNTER10H 0xc8a 921#define CSR_HPMCOUNTER11H 0xc8b 922#define CSR_HPMCOUNTER12H 0xc8c 923#define CSR_HPMCOUNTER13H 0xc8d 924#define CSR_HPMCOUNTER14H 0xc8e 925#define CSR_HPMCOUNTER15H 0xc8f 926#define CSR_HPMCOUNTER16H 0xc90 927#define CSR_HPMCOUNTER17H 0xc91 928#define CSR_HPMCOUNTER18H 0xc92 929#define CSR_HPMCOUNTER19H 0xc93 930#define CSR_HPMCOUNTER20H 0xc94 931#define CSR_HPMCOUNTER21H 0xc95 932#define CSR_HPMCOUNTER22H 0xc96 933#define CSR_HPMCOUNTER23H 0xc97 934#define CSR_HPMCOUNTER24H 0xc98 935#define CSR_HPMCOUNTER25H 0xc99 936#define CSR_HPMCOUNTER26H 0xc9a 937#define CSR_HPMCOUNTER27H 0xc9b 938#define CSR_HPMCOUNTER28H 0xc9c 939#define CSR_HPMCOUNTER29H 0xc9d 940#define CSR_HPMCOUNTER30H 0xc9e 941#define CSR_HPMCOUNTER31H 0xc9f 942#define CSR_MCYCLEH 0xb80 943#define CSR_MINSTRETH 0xb82 944#define CSR_MHPMCOUNTER3H 0xb83 945#define CSR_MHPMCOUNTER4H 0xb84 946#define CSR_MHPMCOUNTER5H 0xb85 947#define CSR_MHPMCOUNTER6H 0xb86 948#define CSR_MHPMCOUNTER7H 0xb87 949#define CSR_MHPMCOUNTER8H 0xb88 950#define CSR_MHPMCOUNTER9H 0xb89 951#define CSR_MHPMCOUNTER10H 0xb8a 952#define CSR_MHPMCOUNTER11H 0xb8b 953#define CSR_MHPMCOUNTER12H 0xb8c 954#define CSR_MHPMCOUNTER13H 0xb8d 955#define CSR_MHPMCOUNTER14H 0xb8e 956#define CSR_MHPMCOUNTER15H 0xb8f 957#define CSR_MHPMCOUNTER16H 0xb90 958#define CSR_MHPMCOUNTER17H 0xb91 959#define CSR_MHPMCOUNTER18H 0xb92 960#define CSR_MHPMCOUNTER19H 0xb93 961#define CSR_MHPMCOUNTER20H 0xb94 962#define CSR_MHPMCOUNTER21H 0xb95 963#define CSR_MHPMCOUNTER22H 0xb96 964#define CSR_MHPMCOUNTER23H 0xb97 965#define CSR_MHPMCOUNTER24H 0xb98 966#define CSR_MHPMCOUNTER25H 0xb99 967#define CSR_MHPMCOUNTER26H 0xb9a 968#define CSR_MHPMCOUNTER27H 0xb9b 969#define CSR_MHPMCOUNTER28H 0xb9c 970#define CSR_MHPMCOUNTER29H 0xb9d 971#define CSR_MHPMCOUNTER30H 0xb9e 972#define CSR_MHPMCOUNTER31H 0xb9f 973#define CAUSE_MISALIGNED_FETCH 0x0 974#define CAUSE_FETCH_ACCESS 0x1 975#define CAUSE_ILLEGAL_INSTRUCTION 0x2 976#define CAUSE_BREAKPOINT 0x3 977#define CAUSE_MISALIGNED_LOAD 0x4 978#define CAUSE_LOAD_ACCESS 0x5 979#define CAUSE_MISALIGNED_STORE 0x6 980#define CAUSE_STORE_ACCESS 0x7 981#define CAUSE_USER_ECALL 0x8 982#define CAUSE_SUPERVISOR_ECALL 0x9 983#define CAUSE_HYPERVISOR_ECALL 0xa 984#define CAUSE_MACHINE_ECALL 0xb 985#define CAUSE_FETCH_PAGE_FAULT 0xc 986#define CAUSE_LOAD_PAGE_FAULT 0xd 987#define CAUSE_STORE_PAGE_FAULT 0xf 988#endif 989#ifdef DECLARE_INSN 990DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) 991DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) 992DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) 993DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) 994DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) 995DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) 996DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) 997DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) 998DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) 999DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) 1000DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) 1001DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) 1002DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) 1003DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) 1004DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) 1005DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) 1006DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) 1007DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) 1008DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) 1009DECLARE_INSN(add, MATCH_ADD, MASK_ADD) 1010DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) 1011DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) 1012DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) 1013DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) 1014DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) 1015DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) 1016DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) 1017DECLARE_INSN(or, MATCH_OR, MASK_OR) 1018DECLARE_INSN(and, MATCH_AND, MASK_AND) 1019DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) 1020DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) 1021DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) 1022DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) 1023DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) 1024DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) 1025DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) 1026DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) 1027DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) 1028DECLARE_INSN(lb, MATCH_LB, MASK_LB) 1029DECLARE_INSN(lh, MATCH_LH, MASK_LH) 1030DECLARE_INSN(lw, MATCH_LW, MASK_LW) 1031DECLARE_INSN(ld, MATCH_LD, MASK_LD) 1032DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) 1033DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) 1034DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) 1035DECLARE_INSN(sb, MATCH_SB, MASK_SB) 1036DECLARE_INSN(sh, MATCH_SH, MASK_SH) 1037DECLARE_INSN(sw, MATCH_SW, MASK_SW) 1038DECLARE_INSN(sd, MATCH_SD, MASK_SD) 1039DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) 1040DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) 1041DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) 1042DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) 1043DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) 1044DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) 1045DECLARE_INSN(div, MATCH_DIV, MASK_DIV) 1046DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) 1047DECLARE_INSN(rem, MATCH_REM, MASK_REM) 1048DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) 1049DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) 1050DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) 1051DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) 1052DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) 1053DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) 1054DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) 1055DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) 1056DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) 1057DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) 1058DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) 1059DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) 1060DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) 1061DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) 1062DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) 1063DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) 1064DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) 1065DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) 1066DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) 1067DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) 1068DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) 1069DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) 1070DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) 1071DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) 1072DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) 1073DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) 1074DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) 1075DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) 1076DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) 1077DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) 1078DECLARE_INSN(uret, MATCH_URET, MASK_URET) 1079DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) 1080DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) 1081DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) 1082DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) 1083DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) 1084DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) 1085DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) 1086DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) 1087DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) 1088DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) 1089DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) 1090DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) 1091DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) 1092DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) 1093DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) 1094DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) 1095DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) 1096DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) 1097DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) 1098DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) 1099DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) 1100DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) 1101DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) 1102DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) 1103DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) 1104DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) 1105DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) 1106DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) 1107DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) 1108DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) 1109DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) 1110DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) 1111DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) 1112DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) 1113DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) 1114DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) 1115DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) 1116DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) 1117DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) 1118DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) 1119DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) 1120DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) 1121DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) 1122DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) 1123DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) 1124DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) 1125DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) 1126DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) 1127DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) 1128DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) 1129DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) 1130DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) 1131DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) 1132DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) 1133DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) 1134DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) 1135DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) 1136DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) 1137DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) 1138DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) 1139DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) 1140DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) 1141DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) 1142DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) 1143DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) 1144DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) 1145DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) 1146DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) 1147DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) 1148DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) 1149DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) 1150DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) 1151DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) 1152DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) 1153DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) 1154DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) 1155DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) 1156DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) 1157DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) 1158DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) 1159DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) 1160DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) 1161DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) 1162DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) 1163DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) 1164DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) 1165DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) 1166DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) 1167DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) 1168DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) 1169DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) 1170DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) 1171DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) 1172DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) 1173DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) 1174DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) 1175DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) 1176DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) 1177DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) 1178DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) 1179DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) 1180DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) 1181DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) 1182DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) 1183DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) 1184DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) 1185DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) 1186DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) 1187DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) 1188DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) 1189DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) 1190DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) 1191DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) 1192DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) 1193DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) 1194DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) 1195DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) 1196DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) 1197DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) 1198DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) 1199DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) 1200DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) 1201DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) 1202DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) 1203DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) 1204DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) 1205DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) 1206DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) 1207DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) 1208DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) 1209DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) 1210DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) 1211DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) 1212DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) 1213DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) 1214DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) 1215DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) 1216DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) 1217DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) 1218DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) 1219DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) 1220DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) 1221DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) 1222DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) 1223DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) 1224DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) 1225DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) 1226DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) 1227DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) 1228DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) 1229DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) 1230DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) 1231DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) 1232DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) 1233DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) 1234DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) 1235DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) 1236DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) 1237DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) 1238DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) 1239DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) 1240DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) 1241DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) 1242DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) 1243DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) 1244DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) 1245DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) 1246DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) 1247DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) 1248DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) 1249DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) 1250DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) 1251DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) 1252#endif 1253#ifdef DECLARE_CSR 1254DECLARE_CSR(fflags, CSR_FFLAGS) 1255DECLARE_CSR(frm, CSR_FRM) 1256DECLARE_CSR(fcsr, CSR_FCSR) 1257DECLARE_CSR(cycle, CSR_CYCLE) 1258DECLARE_CSR(time, CSR_TIME) 1259DECLARE_CSR(instret, CSR_INSTRET) 1260DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) 1261DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) 1262DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) 1263DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) 1264DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) 1265DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) 1266DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) 1267DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) 1268DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) 1269DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) 1270DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) 1271DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) 1272DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) 1273DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) 1274DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) 1275DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) 1276DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) 1277DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) 1278DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) 1279DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) 1280DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) 1281DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) 1282DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) 1283DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) 1284DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) 1285DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) 1286DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) 1287DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) 1288DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) 1289DECLARE_CSR(sstatus, CSR_SSTATUS) 1290DECLARE_CSR(sie, CSR_SIE) 1291DECLARE_CSR(stvec, CSR_STVEC) 1292DECLARE_CSR(scounteren, CSR_SCOUNTEREN) 1293DECLARE_CSR(sscratch, CSR_SSCRATCH) 1294DECLARE_CSR(sepc, CSR_SEPC) 1295DECLARE_CSR(scause, CSR_SCAUSE) 1296DECLARE_CSR(stval, CSR_STVAL) 1297DECLARE_CSR(sip, CSR_SIP) 1298DECLARE_CSR(satp, CSR_SATP) 1299DECLARE_CSR(mstatus, CSR_MSTATUS) 1300DECLARE_CSR(misa, CSR_MISA) 1301DECLARE_CSR(medeleg, CSR_MEDELEG) 1302DECLARE_CSR(mideleg, CSR_MIDELEG) 1303DECLARE_CSR(mie, CSR_MIE) 1304DECLARE_CSR(mtvec, CSR_MTVEC) 1305DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) 1306DECLARE_CSR(mscratch, CSR_MSCRATCH) 1307DECLARE_CSR(mepc, CSR_MEPC) 1308DECLARE_CSR(mcause, CSR_MCAUSE) 1309DECLARE_CSR(mtval, CSR_MTVAL) 1310DECLARE_CSR(mip, CSR_MIP) 1311DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) 1312DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) 1313DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) 1314DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) 1315DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) 1316DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) 1317DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) 1318DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) 1319DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) 1320DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) 1321DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) 1322DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) 1323DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) 1324DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) 1325DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) 1326DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) 1327DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) 1328DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) 1329DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) 1330DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) 1331DECLARE_CSR(tselect, CSR_TSELECT) 1332DECLARE_CSR(tdata1, CSR_TDATA1) 1333DECLARE_CSR(tdata2, CSR_TDATA2) 1334DECLARE_CSR(tdata3, CSR_TDATA3) 1335DECLARE_CSR(dcsr, CSR_DCSR) 1336DECLARE_CSR(dpc, CSR_DPC) 1337DECLARE_CSR(dscratch, CSR_DSCRATCH) 1338DECLARE_CSR(mcycle, CSR_MCYCLE) 1339DECLARE_CSR(minstret, CSR_MINSTRET) 1340DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) 1341DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) 1342DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) 1343DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) 1344DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) 1345DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) 1346DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) 1347DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) 1348DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) 1349DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) 1350DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) 1351DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) 1352DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) 1353DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) 1354DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) 1355DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) 1356DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) 1357DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) 1358DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) 1359DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) 1360DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) 1361DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) 1362DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) 1363DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) 1364DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) 1365DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) 1366DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) 1367DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) 1368DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) 1369DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) 1370DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) 1371DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) 1372DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) 1373DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) 1374DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) 1375DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) 1376DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) 1377DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) 1378DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) 1379DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) 1380DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) 1381DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) 1382DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) 1383DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) 1384DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) 1385DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) 1386DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) 1387DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) 1388DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) 1389DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) 1390DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) 1391DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) 1392DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) 1393DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) 1394DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) 1395DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) 1396DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) 1397DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) 1398DECLARE_CSR(mvendorid, CSR_MVENDORID) 1399DECLARE_CSR(marchid, CSR_MARCHID) 1400DECLARE_CSR(mimpid, CSR_MIMPID) 1401DECLARE_CSR(mhartid, CSR_MHARTID) 1402DECLARE_CSR(cycleh, CSR_CYCLEH) 1403DECLARE_CSR(timeh, CSR_TIMEH) 1404DECLARE_CSR(instreth, CSR_INSTRETH) 1405DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) 1406DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) 1407DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) 1408DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) 1409DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) 1410DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) 1411DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) 1412DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) 1413DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) 1414DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) 1415DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) 1416DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) 1417DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) 1418DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) 1419DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) 1420DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) 1421DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) 1422DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) 1423DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) 1424DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) 1425DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) 1426DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) 1427DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) 1428DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) 1429DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) 1430DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) 1431DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) 1432DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) 1433DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) 1434DECLARE_CSR(mcycleh, CSR_MCYCLEH) 1435DECLARE_CSR(minstreth, CSR_MINSTRETH) 1436DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) 1437DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) 1438DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) 1439DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) 1440DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) 1441DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) 1442DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) 1443DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) 1444DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) 1445DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) 1446DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) 1447DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) 1448DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) 1449DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) 1450DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) 1451DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) 1452DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) 1453DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) 1454DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) 1455DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) 1456DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) 1457DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) 1458DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) 1459DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) 1460DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) 1461DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) 1462DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) 1463DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) 1464DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) 1465#endif 1466#ifdef DECLARE_CAUSE 1467DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) 1468DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) 1469DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) 1470DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) 1471DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) 1472DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) 1473DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) 1474DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) 1475DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) 1476DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) 1477DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) 1478DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) 1479DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) 1480DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) 1481DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) 1482#endif 1483