1/*
2 * Copyright 2017, Data61
3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
4 * ABN 41 687 119 230.
5 *
6 * This software may be distributed and modified according to the terms of
7 * the BSD 2-Clause license. Note that NO WARRANTY is provided.
8 * See "LICENSE_BSD2.txt" for details.
9 *
10 * @TAG(DATA61_BSD)
11 */
12
13#pragma once
14
15/* Prevent the compiler from re-ordering any read or write across the fence. */
16#define COMPILER_MEMORY_FENCE() __atomic_signal_fence(__ATOMIC_ACQ_REL)
17
18/* Prevent the compiler from re-ordering any write which follows the fence
19 * in program order with any read or write which preceeds the fence in
20 * program order. */
21#define COMPILER_MEMORY_RELEASE() __atomic_signal_fence(__ATOMIC_RELEASE)
22
23/* Prevent the compiler from re-ordering any read which preceeds the fence
24 * in program order with any read or write which follows the fence in
25 * program order. */
26#define COMPILER_MEMORY_ACQUIRE() __atomic_signal_fence(__ATOMIC_ACQUIRE)
27
28/* THREAD_MEMORY_FENCE: Implements a full processor memory barrier.
29 * All stores before this point are completed, and all loads after this
30 * point are delayed until after it.
31 */
32#define THREAD_MEMORY_FENCE() __atomic_thread_fence(__ATOMIC_ACQ_REL)
33
34/* THREAD_MEMORY_RELEASE: Implements a fence which has the effect of
35 * forcing all stores before this point to complete.
36 */
37#define THREAD_MEMORY_RELEASE() __atomic_thread_fence(__ATOMIC_RELEASE)
38
39/* THREAD_MEMORY_ACQUIRE: Implements a fence which has the effect of
40 * forcing all loads beyond this point to occur after this point.
41 */
42#define THREAD_MEMORY_ACQUIRE() __atomic_thread_fence(__ATOMIC_ACQUIRE)
43