1/* 2 * @TAG(OTHER_GPL) 3 */ 4 5/* 6 * linux/mdio.h: definitions for MDIO (clause 45) transceivers 7 * Copyright 2006-2009 Solarflare Communications Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published 11 * by the Free Software Foundation, incorporated herein by reference. 12 */ 13 14#pragma once 15 16#include "mii.h" 17 18/* MDIO Manageable Devices (MMDs). */ 19#define MDIO_MMD_PMAPMD 1 /* Physical Medium Attachment/ 20 * Physical Medium Dependent */ 21#define MDIO_MMD_WIS 2 /* WAN Interface Sublayer */ 22#define MDIO_MMD_PCS 3 /* Physical Coding Sublayer */ 23#define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */ 24#define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */ 25#define MDIO_MMD_TC 6 /* Transmission Convergence */ 26#define MDIO_MMD_AN 7 /* Auto-Negotiation */ 27#define MDIO_MMD_C22EXT 29 /* Clause 22 extension */ 28#define MDIO_MMD_VEND1 30 /* Vendor specific 1 */ 29#define MDIO_MMD_VEND2 31 /* Vendor specific 2 */ 30 31/* Generic MDIO registers. */ 32#define MDIO_CTRL1 MII_BMCR 33#define MDIO_STAT1 MII_BMSR 34#define MDIO_DEVID1 MII_PHYSID1 35#define MDIO_DEVID2 MII_PHYSID2 36#define MDIO_SPEED 4 /* Speed ability */ 37#define MDIO_DEVS1 5 /* Devices in package */ 38#define MDIO_DEVS2 6 39#define MDIO_CTRL2 7 /* 10G control 2 */ 40#define MDIO_STAT2 8 /* 10G status 2 */ 41#define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */ 42#define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */ 43#define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */ 44#define MDIO_PKGID1 14 /* Package identifier */ 45#define MDIO_PKGID2 15 46#define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */ 47#define MDIO_AN_LPA 19 /* AN LP abilities (base page) */ 48#define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */ 49 50/* Media-dependent registers. */ 51#define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */ 52#define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */ 53#define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A. 54 * Lanes B-D are numbered 134-136. */ 55#define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */ 56#define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */ 57#define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */ 58#define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */ 59#define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */ 60#define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */ 61#define MDIO_AN_EEE_ADV 60 /* EEE advertisement */ 62 63/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */ 64#define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */ 65#define MDIO_PMA_LASI_TXCTRL 0x9001 /* TX_ALARM control */ 66#define MDIO_PMA_LASI_CTRL 0x9002 /* LASI control */ 67#define MDIO_PMA_LASI_RXSTAT 0x9003 /* RX_ALARM status */ 68#define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */ 69#define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */ 70 71/* Control register 1. */ 72/* Enable extended speed selection */ 73#define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100) 74/* All speed selection bits */ 75#define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c) 76#define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX 77#define MDIO_CTRL1_LPOWER BMCR_PDOWN 78#define MDIO_CTRL1_RESET BMCR_RESET 79#define MDIO_PMA_CTRL1_LOOPBACK 0x0001 80#define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000 81#define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100 82#define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK 83#define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK 84#define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART 85#define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE 86#define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */ 87 88/* 10 Gb/s */ 89#define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00) 90/* 10PASS-TS/2BASE-TL */ 91#define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04) 92 93/* Status register 1. */ 94#define MDIO_STAT1_LPOWERABLE 0x0002 /* Low-power ability */ 95#define MDIO_STAT1_LSTATUS BMSR_LSTATUS 96#define MDIO_STAT1_FAULT 0x0080 /* Fault */ 97#define MDIO_AN_STAT1_LPABLE 0x0001 /* Link partner AN ability */ 98#define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE 99#define MDIO_AN_STAT1_RFAULT BMSR_RFAULT 100#define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE 101#define MDIO_AN_STAT1_PAGE 0x0040 /* Page received */ 102#define MDIO_AN_STAT1_XNP 0x0080 /* Extended next page status */ 103 104/* Speed register. */ 105#define MDIO_SPEED_10G 0x0001 /* 10G capable */ 106#define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */ 107#define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */ 108#define MDIO_PMA_SPEED_1000 0x0010 /* 1000M capable */ 109#define MDIO_PMA_SPEED_100 0x0020 /* 100M capable */ 110#define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */ 111#define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */ 112 113/* Device present registers. */ 114#define MDIO_DEVS_PRESENT(devad) (BIT((devad))) 115#define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD) 116#define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS) 117#define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS) 118#define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS) 119#define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS) 120#define MDIO_DEVS_TC MDIO_DEVS_PRESENT(MDIO_MMD_TC) 121#define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN) 122#define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT) 123#define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1) 124#define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2) 125 126#define MDIO_DEVS_LINK (MDIO_DEVS_PMAPMD | \ 127 MDIO_DEVS_WIS | \ 128 MDIO_DEVS_PCS | \ 129 MDIO_DEVS_PHYXS | \ 130 MDIO_DEVS_DTEXS | \ 131 MDIO_DEVS_AN) 132 133/* Control register 2. */ 134#define MDIO_PMA_CTRL2_TYPE 0x000f /* PMA/PMD type selection */ 135#define MDIO_PMA_CTRL2_10GBCX4 0x0000 /* 10GBASE-CX4 type */ 136#define MDIO_PMA_CTRL2_10GBEW 0x0001 /* 10GBASE-EW type */ 137#define MDIO_PMA_CTRL2_10GBLW 0x0002 /* 10GBASE-LW type */ 138#define MDIO_PMA_CTRL2_10GBSW 0x0003 /* 10GBASE-SW type */ 139#define MDIO_PMA_CTRL2_10GBLX4 0x0004 /* 10GBASE-LX4 type */ 140#define MDIO_PMA_CTRL2_10GBER 0x0005 /* 10GBASE-ER type */ 141#define MDIO_PMA_CTRL2_10GBLR 0x0006 /* 10GBASE-LR type */ 142#define MDIO_PMA_CTRL2_10GBSR 0x0007 /* 10GBASE-SR type */ 143#define MDIO_PMA_CTRL2_10GBLRM 0x0008 /* 10GBASE-LRM type */ 144#define MDIO_PMA_CTRL2_10GBT 0x0009 /* 10GBASE-T type */ 145#define MDIO_PMA_CTRL2_10GBKX4 0x000a /* 10GBASE-KX4 type */ 146#define MDIO_PMA_CTRL2_10GBKR 0x000b /* 10GBASE-KR type */ 147#define MDIO_PMA_CTRL2_1000BT 0x000c /* 1000BASE-T type */ 148#define MDIO_PMA_CTRL2_1000BKX 0x000d /* 1000BASE-KX type */ 149#define MDIO_PMA_CTRL2_100BTX 0x000e /* 100BASE-TX type */ 150#define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */ 151#define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */ 152#define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */ 153#define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */ 154#define MDIO_PCS_CTRL2_10GBW 0x0002 /* 10GBASE-W type */ 155#define MDIO_PCS_CTRL2_10GBT 0x0003 /* 10GBASE-T type */ 156 157/* Status register 2. */ 158#define MDIO_STAT2_RXFAULT 0x0400 /* Receive fault */ 159#define MDIO_STAT2_TXFAULT 0x0800 /* Transmit fault */ 160#define MDIO_STAT2_DEVPRST 0xc000 /* Device present */ 161#define MDIO_STAT2_DEVPRST_VAL 0x8000 /* Device present value */ 162#define MDIO_PMA_STAT2_LBABLE 0x0001 /* PMA loopback ability */ 163#define MDIO_PMA_STAT2_10GBEW 0x0002 /* 10GBASE-EW ability */ 164#define MDIO_PMA_STAT2_10GBLW 0x0004 /* 10GBASE-LW ability */ 165#define MDIO_PMA_STAT2_10GBSW 0x0008 /* 10GBASE-SW ability */ 166#define MDIO_PMA_STAT2_10GBLX4 0x0010 /* 10GBASE-LX4 ability */ 167#define MDIO_PMA_STAT2_10GBER 0x0020 /* 10GBASE-ER ability */ 168#define MDIO_PMA_STAT2_10GBLR 0x0040 /* 10GBASE-LR ability */ 169#define MDIO_PMA_STAT2_10GBSR 0x0080 /* 10GBASE-SR ability */ 170#define MDIO_PMD_STAT2_TXDISAB 0x0100 /* PMD TX disable ability */ 171#define MDIO_PMA_STAT2_EXTABLE 0x0200 /* Extended abilities */ 172#define MDIO_PMA_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */ 173#define MDIO_PMA_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */ 174#define MDIO_PCS_STAT2_10GBR 0x0001 /* 10GBASE-R capable */ 175#define MDIO_PCS_STAT2_10GBX 0x0002 /* 10GBASE-X capable */ 176#define MDIO_PCS_STAT2_10GBW 0x0004 /* 10GBASE-W capable */ 177#define MDIO_PCS_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */ 178#define MDIO_PCS_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */ 179 180/* Transmit disable register. */ 181#define MDIO_PMD_TXDIS_GLOBAL 0x0001 /* Global PMD TX disable */ 182#define MDIO_PMD_TXDIS_0 0x0002 /* PMD TX disable 0 */ 183#define MDIO_PMD_TXDIS_1 0x0004 /* PMD TX disable 1 */ 184#define MDIO_PMD_TXDIS_2 0x0008 /* PMD TX disable 2 */ 185#define MDIO_PMD_TXDIS_3 0x0010 /* PMD TX disable 3 */ 186 187/* Receive signal detect register. */ 188#define MDIO_PMD_RXDET_GLOBAL 0x0001 /* Global PMD RX signal detect */ 189#define MDIO_PMD_RXDET_0 0x0002 /* PMD RX signal detect 0 */ 190#define MDIO_PMD_RXDET_1 0x0004 /* PMD RX signal detect 1 */ 191#define MDIO_PMD_RXDET_2 0x0008 /* PMD RX signal detect 2 */ 192#define MDIO_PMD_RXDET_3 0x0010 /* PMD RX signal detect 3 */ 193 194/* Extended abilities register. */ 195#define MDIO_PMA_EXTABLE_10GCX4 0x0001 /* 10GBASE-CX4 ability */ 196#define MDIO_PMA_EXTABLE_10GBLRM 0x0002 /* 10GBASE-LRM ability */ 197#define MDIO_PMA_EXTABLE_10GBT 0x0004 /* 10GBASE-T ability */ 198#define MDIO_PMA_EXTABLE_10GBKX4 0x0008 /* 10GBASE-KX4 ability */ 199#define MDIO_PMA_EXTABLE_10GBKR 0x0010 /* 10GBASE-KR ability */ 200#define MDIO_PMA_EXTABLE_1000BT 0x0020 /* 1000BASE-T ability */ 201#define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */ 202#define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */ 203#define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */ 204 205/* PHY XGXS lane state register. */ 206#define MDIO_PHYXS_LNSTAT_SYNC0 0x0001 207#define MDIO_PHYXS_LNSTAT_SYNC1 0x0002 208#define MDIO_PHYXS_LNSTAT_SYNC2 0x0004 209#define MDIO_PHYXS_LNSTAT_SYNC3 0x0008 210#define MDIO_PHYXS_LNSTAT_ALIGN 0x1000 211 212/* PMA 10GBASE-T pair swap & polarity */ 213#define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001 /* Pair A/B uncrossed */ 214#define MDIO_PMA_10GBT_SWAPPOL_CDNX 0x0002 /* Pair C/D uncrossed */ 215#define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100 /* Pair A polarity reversed */ 216#define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200 /* Pair B polarity reversed */ 217#define MDIO_PMA_10GBT_SWAPPOL_CREV 0x0400 /* Pair C polarity reversed */ 218#define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800 /* Pair D polarity reversed */ 219 220/* PMA 10GBASE-T TX power register. */ 221#define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 /* Short-reach mode */ 222 223/* PMA 10GBASE-T SNR registers. */ 224/* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */ 225#define MDIO_PMA_10GBT_SNR_BIAS 0x8000 226#define MDIO_PMA_10GBT_SNR_MAX 127 227 228/* PMA 10GBASE-R FEC ability register. */ 229#define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */ 230#define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability */ 231 232/* PCS 10GBASE-R/-T status register 1. */ 233#define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001 /* Block lock attained */ 234 235/* PCS 10GBASE-R/-T status register 2. */ 236#define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff 237#define MDIO_PCS_10GBRT_STAT2_BER 0x3f00 238 239/* AN 10GBASE-T control register. */ 240#define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */ 241 242/* AN 10GBASE-T status register. */ 243#define MDIO_AN_10GBT_STAT_LPTRR 0x0200 /* LP training reset req. */ 244#define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400 /* LP loop timing ability */ 245#define MDIO_AN_10GBT_STAT_LP10G 0x0800 /* LP is 10GBT capable */ 246#define MDIO_AN_10GBT_STAT_REMOK 0x1000 /* Remote OK */ 247#define MDIO_AN_10GBT_STAT_LOCOK 0x2000 /* Local OK */ 248#define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */ 249#define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */ 250 251/* AN EEE Advertisement register. */ 252#define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */ 253#define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */ 254 255/* LASI RX_ALARM control/status registers. */ 256#define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */ 257#define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */ 258#define MDIO_PMA_LASI_RX_PMALFLT 0x0010 /* PMA/PMD RX local fault */ 259#define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020 /* RX optical power fault */ 260#define MDIO_PMA_LASI_RX_WISLFLT 0x0200 /* WIS local fault */ 261 262/* LASI TX_ALARM control/status registers. */ 263#define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001 /* PHY XS TX local fault */ 264#define MDIO_PMA_LASI_TX_PCSLFLT 0x0008 /* PCS TX local fault */ 265#define MDIO_PMA_LASI_TX_PMALFLT 0x0010 /* PMA/PMD TX local fault */ 266#define MDIO_PMA_LASI_TX_LASERPOWERFLT 0x0080 /* Laser output power fault */ 267#define MDIO_PMA_LASI_TX_LASERTEMPFLT 0x0100 /* Laser temperature fault */ 268#define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200 /* Laser bias current fault */ 269 270/* LASI control/status registers. */ 271#define MDIO_PMA_LASI_LSALARM 0x0001 /* LS_ALARM enable/status */ 272#define MDIO_PMA_LASI_TXALARM 0x0002 /* TX_ALARM enable/status */ 273#define MDIO_PMA_LASI_RXALARM 0x0004 /* RX_ALARM enable/status */ 274 275/* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */ 276 277#define MDIO_PHY_ID_C45 0x8000 278#define MDIO_PHY_ID_PRTAD 0x03e0 279#define MDIO_PHY_ID_DEVAD 0x001f 280#define MDIO_PHY_ID_C45_MASK \ 281 (MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD) 282 283#define MDIO_PRTAD_NONE (-1) 284#define MDIO_DEVAD_NONE (-1) 285#define MDIO_EMULATE_C22 4 286 287