1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 8 * See "LICENSE_BSD2.txt" for details. 9 * 10 * @TAG(DATA61_BSD) 11 */ 12 13#include "../../event_counters.h" 14 15const char* const sel4bench_cpu_event_counter_data[] = { 16 NAME_EVENT(JAVA_BYTECODE_EXECUTE , "Java bytecode executed"), 17 NAME_EVENT(SW_JAVA_BYTECODE_EXECUTE, "Software Java bytecode executed"), 18 NAME_EVENT(JAZELLE_BW_BRANCHES , "Jazelle backward branches executed"), 19 NAME_EVENT(LINEFILL_MISS , "Coherent linefill miss"), 20 NAME_EVENT(LINEFILL_HIT , "Coherent linefill hit"), 21 NAME_EVENT(ICACHE_STALL , "Instruction cache dependent stall cycles"), 22 NAME_EVENT(DCACHE_STALL , "Data cache dependent stall cycles"), 23 NAME_EVENT(TLBMISS_STALL , "Main TLB miss stall cycles"), 24 NAME_EVENT(STREX_PASSED , "STREX passed"), 25 NAME_EVENT(STREX_FAILED , "STREX failed"), 26 NAME_EVENT(DATA_EVICT , "Data eviction"), 27 NAME_EVENT(ISSUE_NO_DISPATCH , "Issue does not dispatch any instruction"), 28 NAME_EVENT(ISSUE_EMPTY , "Issue is empty"), 29 NAME_EVENT(RENAME_INST , "Instructions coming out of the core renaming stage"), 30 NAME_EVENT(PREDICTABLE_FUNCTION_RET, "Predictable function returns"), 31 NAME_EVENT(MAIN_EXEC_INST , "Main execution unit instructions"), 32 NAME_EVENT(SECOND_EXEC_INST , "Second execution unit instructions"), 33 NAME_EVENT(LOADSTORE_INST , "Load/Store Instructions"), 34 NAME_EVENT(FLOAT_INST , "Floating-point instructions"), 35 NAME_EVENT(NEON_INST , "NEON instructions"), 36 NAME_EVENT(PLD_STALL , "Processor stall - PLDs"), 37 NAME_EVENT(WRITE_STALL , "Processor stall - a write to memory"), 38 NAME_EVENT(ITLBMISS_STALL , "Processor stall - instruction side main TLB miss"), 39 NAME_EVENT(DTLBMISS_STALL , "Processor stall - data side main TLB miss"), 40 NAME_EVENT(IUTLBMISS_STALL , "Processor stall - instruction micro TLB miss"), 41 NAME_EVENT(DUTLBMISS_STALL , "Processor stall - data micro TLB miss"), 42 NAME_EVENT(DMB_STALL , "Processor stall - DMB"), 43 NAME_EVENT(INTEGER_CLOCK_ENABLED , "Integer clock enabled"), 44 NAME_EVENT(DATA_CLOCK_ENABLED , "Data Engine clock enabled"), 45 NAME_EVENT(ISB_INST , "ISB instructions"), 46 NAME_EVENT(DSB_INST , "DSB instructions"), 47 NAME_EVENT(DMB_INST , "DMB instructions"), 48 NAME_EVENT(EXT_IRQ , "External interrupts"), 49 NAME_EVENT(PLE_CACHELINE_COMPLETED , "PLE cache line request completed"), 50 NAME_EVENT(PLE_CACHELINE_SKIPPED , "PLE cache line request skipped"), 51 NAME_EVENT(PLE_FIFO_FLUSH , "PLE FIFO flush"), 52 NAME_EVENT(PLE_COMPLETED , "PLE request completed"), 53 NAME_EVENT(PLE_FIFO_OVERFLOW , "PLE FIFO overflow"), 54 NAME_EVENT(PLE_REQUESTS , "PLE request programmed") 55}; 56 57int 58sel4bench_cpu_get_num_counters(void) 59{ 60 return ARRAY_SIZE(sel4bench_cpu_event_counter_data); 61} 62