1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 8 * See "LICENSE_BSD2.txt" for details. 9 * 10 * @TAG(DATA61_BSD) 11 */ 12 13#include <utils/util.h> 14 15#include "../../event_counters.h" 16 17const char* const sel4bench_arch_event_counter_data[] = { 18 NAME_EVENT(SOFTWARE_INCREMENT , "Instruction architecturally executed, condition code check pass, software increment"), 19 NAME_EVENT(CACHE_L1I_MISS , "Level 1 instruction cache refill"), 20 NAME_EVENT(TLB_L1I_MISS , "Level 1 instruction TLB refill"), 21 NAME_EVENT(CACHE_L1D_MISS , "Level 1 data cache refill"), 22 NAME_EVENT(CACHE_L1D_HIT , "Level 1 data cache access"), 23 NAME_EVENT(TLB_L1D_MISS , "Level 1 data TLB refill"), 24 NAME_EVENT(MEMORY_READ , "Instruction architecturally executed, condition code check pass, load"), 25 NAME_EVENT(MEMORY_WRITE , "Instruction architecturally executed, condition code check pass, store"), 26#ifndef CONFIG_ARM_CORTEX_A9 27 NAME_EVENT(EXECUTE_INSTRUCTION , "Instruction architecturally executed"), 28#endif 29 NAME_EVENT(EXCEPTION , "Exception taken"), 30 NAME_EVENT(EXCEPTION_RETURN , "Instruction architecturally executed, condition code check pass, exception return"), 31 NAME_EVENT(CONTEXTIDR_WRITE , "Instruction architecturally executed, condition code check pass, write to CONTEXTIDR"), 32 NAME_EVENT(SOFTWARE_PC_CHANGE , "Instruction architecturally executed, condition code check pass, software change of the PC"), 33 NAME_EVENT(EXECUTE_BRANCH_IMM , "Instruction architecturally executed, immediate branch"), 34#ifndef CONFIG_ARM_CORTEX_A9 35 NAME_EVENT(FUNCTION_RETURN , "Instruction architecturally executed, condition code check pass, procedure return"), 36#endif 37 NAME_EVENT(MEMORY_ACCESS_UNALIGNED , "Instruction architecturally executed, condition code check pass, unaligned load or store"), 38 NAME_EVENT(BRANCH_MISPREDICT , "Mispredicted or not predicted branch speculatively executed"), 39 NAME_EVENT(CCNT , "Cycle"), 40 NAME_EVENT(EXECUTE_BRANCH_PREDICTABLE, "Predictable branch speculatively executed"), 41 NAME_EVENT(MEMORY_ACCESS , "Data memory access"), 42 NAME_EVENT(L1I_CACHE , "Level 1 instruction cache access"), 43 NAME_EVENT(L1D_CACHE_WB , "Level 1 data cache write-back"), 44 NAME_EVENT(L2D_CACHE , "Level 2 data cache access"), 45 NAME_EVENT(L2D_CACHE_REFILL , "Level 2 data cache refill"), 46 NAME_EVENT(L2D_CACHE_WB , "Level 2 data cache write-back"), 47 NAME_EVENT(BUS_ACCESS , "Bus access"), 48 NAME_EVENT(MEMORY_ERROR , "Local memory error"), 49 NAME_EVENT(INST_SPEC , "Instruction speculatively executed"), 50 NAME_EVENT(TTBR_WRITE_RETIRED , "Instruction architecturally executed, condition code check pass, write to TTBR"), 51 NAME_EVENT(BUS_CYCLES , "Bus cycle") 52}; 53 54int 55sel4bench_arch_get_num_counters(void) 56{ 57 return ARRAY_SIZE(sel4bench_arch_event_counter_data); 58} 59