1/*
2 * Copyright 2017, Data61
3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
4 * ABN 41 687 119 230.
5 *
6 * This software may be distributed and modified according to the terms of
7 * the BSD 2-Clause license. Note that NO WARRANTY is provided.
8 * See "LICENSE_BSD2.txt" for details.
9 *
10 * @TAG(DATA61_BSD)
11 */
12
13//event definitions
14//events common to all ARMV7A CPUs
15#pragma once
16#include <autoconf.h>
17
18#define SEL4BENCH_EVENT_SOFTWARE_INCREMENT          0x00
19
20/* generic events */
21#define SEL4BENCH_EVENT_CACHE_L1I_MISS              0x01
22#define SEL4BENCH_EVENT_CACHE_L1D_MISS              0x03
23#define SEL4BENCH_EVENT_TLB_L1I_MISS                0x02
24#define SEL4BENCH_EVENT_TLB_L1D_MISS                0x05
25
26#ifndef CONFIG_ARM_CORTEX_A9
27#define SEL4BENCH_EVENT_EXECUTE_INSTRUCTION         0x08
28#endif /* CONFIG_ARM_CORTEX_A9 */
29
30#define SEL4BENCH_EVENT_BRANCH_MISPREDICT           0x10
31
32#define SEL4BENCH_EVENT_CACHE_L1D_HIT               0x04
33
34#define SEL4BENCH_EVENT_MEMORY_READ                 0x06
35#define SEL4BENCH_EVENT_MEMORY_WRITE                0x07
36#define SEL4BENCH_EVENT_EXCEPTION                   0x09
37#define SEL4BENCH_EVENT_EXCEPTION_RETURN            0x0A
38#define SEL4BENCH_EVENT_CONTEXTIDR_WRITE            0x0B
39#define SEL4BENCH_EVENT_SOFTWARE_PC_CHANGE          0x0C
40#define SEL4BENCH_EVENT_EXECUTE_BRANCH_IMM          0x0D
41#ifndef CONFIG_ARM_CORTEX_A9
42#define SEL4BENCH_EVENT_FUNCTION_RETURN             0x0E
43#endif /* CONFIG_ARM_CORTEX_A9 */
44#define SEL4BENCH_EVENT_MEMORY_ACCESS_UNALIGNED     0x0F
45#define SEL4BENCH_EVENT_CCNT                        0x11
46#define SEL4BENCH_EVENT_EXECUTE_BRANCH_PREDICTABLE  0x12
47/* Data memory access */
48#define SEL4BENCH_EVENT_MEMORY_ACCESS                  0x13
49/* Level 1 instruction cache access */
50#define SEL4BENCH_EVENT_L1I_CACHE                   0x14
51/* Level 1 data cache write-back */
52#define SEL4BENCH_EVENT_L1D_CACHE_WB                0x15
53/* Level 2 data cache access */
54#define SEL4BENCH_EVENT_L2D_CACHE                   0x16
55/* Level 2 data cache refill */
56#define SEL4BENCH_EVENT_L2D_CACHE_REFILL            0x17
57/* Level 2 data cache write-back */
58#define SEL4BENCH_EVENT_L2D_CACHE_WB                0x18
59/* Bus access */
60#define SEL4BENCH_EVENT_BUS_ACCESS                  0x19
61/* Local memory error */
62#define SEL4BENCH_EVENT_MEMORY_ERROR                0x1A
63/* Instruction speculatively executed */
64#define SEL4BENCH_EVENT_INST_SPEC                   0x1B
65/* Instruction architecturally executed, condition code check pass, write to TTBR */
66#define SEL4BENCH_EVENT_TTBR_WRITE_RETIRED          0x1C
67/* Bus cycle */
68#define SEL4BENCH_EVENT_BUS_CYCLES                  0x1D
69
70#include <sel4bench/cpu/events.h>
71