1/* 2 * Copyright Linux Kernel Team 3 * 4 * SPDX-License-Identifier: GPL-2.0-only 5 * 6 * This file is derived from an intermediate build stage of the 7 * Linux kernel. The licenses of all input files to this process 8 * are compatible with GPL-2.0-only. 9 */ 10 11/dts-v1/; 12 13/ { 14 compatible = "xlnx,zynqmp-zcu102-rev1.0\0xlnx,zynqmp-zcu102\0xlnx,zynqmp"; 15 #address-cells = < 0x02 >; 16 #size-cells = < 0x02 >; 17 model = "ZynqMP ZCU102 Rev1.0"; 18 19 cpus { 20 #address-cells = < 0x01 >; 21 #size-cells = < 0x00 >; 22 23 cpu@0 { 24 compatible = "arm,cortex-a53\0arm,armv8"; 25 device_type = "cpu"; 26 enable-method = "psci"; 27 operating-points-v2 = < 0x01 >; 28 reg = < 0x00 >; 29 cpu-idle-states = < 0x02 >; 30 }; 31 32 cpu@1 { 33 compatible = "arm,cortex-a53\0arm,armv8"; 34 device_type = "cpu"; 35 enable-method = "psci"; 36 reg = < 0x01 >; 37 operating-points-v2 = < 0x01 >; 38 cpu-idle-states = < 0x02 >; 39 }; 40 41 cpu@2 { 42 compatible = "arm,cortex-a53\0arm,armv8"; 43 device_type = "cpu"; 44 enable-method = "psci"; 45 reg = < 0x02 >; 46 operating-points-v2 = < 0x01 >; 47 cpu-idle-states = < 0x02 >; 48 }; 49 50 cpu@3 { 51 compatible = "arm,cortex-a53\0arm,armv8"; 52 device_type = "cpu"; 53 enable-method = "psci"; 54 reg = < 0x03 >; 55 operating-points-v2 = < 0x01 >; 56 cpu-idle-states = < 0x02 >; 57 }; 58 59 idle-states { 60 entry-method = "psci"; 61 62 cpu-sleep-0 { 63 compatible = "arm,idle-state"; 64 arm,psci-suspend-param = < 0x40000000 >; 65 local-timer-stop; 66 entry-latency-us = < 0x12c >; 67 exit-latency-us = < 0x258 >; 68 min-residency-us = < 0x2710 >; 69 phandle = < 0x02 >; 70 }; 71 }; 72 }; 73 74 cpu_opp_table { 75 compatible = "operating-points-v2"; 76 opp-shared; 77 phandle = < 0x01 >; 78 79 opp00 { 80 opp-hz = < 0x00 0x47868bf4 >; 81 opp-microvolt = < 0xf4240 >; 82 clock-latency-ns = < 0x7a120 >; 83 }; 84 85 opp01 { 86 opp-hz = < 0x00 0x23c345fa >; 87 opp-microvolt = < 0xf4240 >; 88 clock-latency-ns = < 0x7a120 >; 89 }; 90 91 opp02 { 92 opp-hz = < 0x00 0x17d783fc >; 93 opp-microvolt = < 0xf4240 >; 94 clock-latency-ns = < 0x7a120 >; 95 }; 96 97 opp03 { 98 opp-hz = < 0x00 0x11e1a2fd >; 99 opp-microvolt = < 0xf4240 >; 100 clock-latency-ns = < 0x7a120 >; 101 }; 102 }; 103 104 dcc { 105 compatible = "arm,dcc"; 106 status = "okay"; 107 }; 108 109 pmu { 110 compatible = "arm,armv8-pmuv3"; 111 interrupt-parent = < 0x03 >; 112 interrupts = < 0x00 0x8f 0x04 0x00 0x90 0x04 0x00 0x91 0x04 0x00 0x92 0x04 >; 113 }; 114 115 psci { 116 compatible = "arm,psci-0.2"; 117 method = "smc"; 118 }; 119 120 timer { 121 compatible = "arm,armv8-timer"; 122 interrupt-parent = < 0x03 >; 123 interrupts = < 0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08 0x01 0x0a 0xf08 >; 124 }; 125 126 amba_apu@0 { 127 compatible = "simple-bus"; 128 #address-cells = < 0x02 >; 129 #size-cells = < 0x01 >; 130 ranges = < 0x00 0x00 0x00 0x00 0xffffffff >; 131 132 interrupt-controller@f9010000 { 133 compatible = "arm,gic-400\0arm,cortex-a15-gic"; 134 #interrupt-cells = < 0x03 >; 135 reg = < 0x00 0xf9010000 0x10000 0x00 0xf9020000 0x20000 0x00 0xf9040000 0x20000 0x00 0xf9060000 0x20000 >; 136 interrupt-controller; 137 interrupt-parent = < 0x03 >; 138 interrupts = < 0x01 0x09 0xf04 >; 139 phandle = < 0x03 >; 140 }; 141 }; 142 143 amba { 144 compatible = "simple-bus"; 145 #address-cells = < 0x02 >; 146 #size-cells = < 0x02 >; 147 ranges; 148 149 can@ff060000 { 150 compatible = "xlnx,zynq-can-1.0"; 151 status = "disabled"; 152 clock-names = "can_clk\0pclk"; 153 reg = < 0x00 0xff060000 0x00 0x1000 >; 154 interrupts = < 0x00 0x17 0x04 >; 155 interrupt-parent = < 0x03 >; 156 tx-fifo-depth = < 0x40 >; 157 rx-fifo-depth = < 0x40 >; 158 clocks = < 0x04 0x04 >; 159 }; 160 161 can@ff070000 { 162 compatible = "xlnx,zynq-can-1.0"; 163 status = "okay"; 164 clock-names = "can_clk\0pclk"; 165 reg = < 0x00 0xff070000 0x00 0x1000 >; 166 interrupts = < 0x00 0x18 0x04 >; 167 interrupt-parent = < 0x03 >; 168 tx-fifo-depth = < 0x40 >; 169 rx-fifo-depth = < 0x40 >; 170 clocks = < 0x04 0x04 >; 171 }; 172 173 cci@fd6e0000 { 174 compatible = "arm,cci-400"; 175 reg = < 0x00 0xfd6e0000 0x00 0x9000 >; 176 ranges = < 0x00 0x00 0xfd6e0000 0x10000 >; 177 #address-cells = < 0x01 >; 178 #size-cells = < 0x01 >; 179 180 pmu@9000 { 181 compatible = "arm,cci-400-pmu,r1"; 182 reg = < 0x9000 0x5000 >; 183 interrupt-parent = < 0x03 >; 184 interrupts = < 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04 >; 185 }; 186 }; 187 188 dma@fd500000 { 189 status = "okay"; 190 compatible = "xlnx,zynqmp-dma-1.0"; 191 reg = < 0x00 0xfd500000 0x00 0x1000 >; 192 interrupt-parent = < 0x03 >; 193 interrupts = < 0x00 0x7c 0x04 >; 194 clock-names = "clk_main\0clk_apb"; 195 xlnx,bus-width = < 0x80 >; 196 clocks = < 0x05 0x04 >; 197 }; 198 199 dma@fd510000 { 200 status = "okay"; 201 compatible = "xlnx,zynqmp-dma-1.0"; 202 reg = < 0x00 0xfd510000 0x00 0x1000 >; 203 interrupt-parent = < 0x03 >; 204 interrupts = < 0x00 0x7d 0x04 >; 205 clock-names = "clk_main\0clk_apb"; 206 xlnx,bus-width = < 0x80 >; 207 clocks = < 0x05 0x04 >; 208 }; 209 210 dma@fd520000 { 211 status = "okay"; 212 compatible = "xlnx,zynqmp-dma-1.0"; 213 reg = < 0x00 0xfd520000 0x00 0x1000 >; 214 interrupt-parent = < 0x03 >; 215 interrupts = < 0x00 0x7e 0x04 >; 216 clock-names = "clk_main\0clk_apb"; 217 xlnx,bus-width = < 0x80 >; 218 clocks = < 0x05 0x04 >; 219 }; 220 221 dma@fd530000 { 222 status = "okay"; 223 compatible = "xlnx,zynqmp-dma-1.0"; 224 reg = < 0x00 0xfd530000 0x00 0x1000 >; 225 interrupt-parent = < 0x03 >; 226 interrupts = < 0x00 0x7f 0x04 >; 227 clock-names = "clk_main\0clk_apb"; 228 xlnx,bus-width = < 0x80 >; 229 clocks = < 0x05 0x04 >; 230 }; 231 232 dma@fd540000 { 233 status = "okay"; 234 compatible = "xlnx,zynqmp-dma-1.0"; 235 reg = < 0x00 0xfd540000 0x00 0x1000 >; 236 interrupt-parent = < 0x03 >; 237 interrupts = < 0x00 0x80 0x04 >; 238 clock-names = "clk_main\0clk_apb"; 239 xlnx,bus-width = < 0x80 >; 240 clocks = < 0x05 0x04 >; 241 }; 242 243 dma@fd550000 { 244 status = "okay"; 245 compatible = "xlnx,zynqmp-dma-1.0"; 246 reg = < 0x00 0xfd550000 0x00 0x1000 >; 247 interrupt-parent = < 0x03 >; 248 interrupts = < 0x00 0x81 0x04 >; 249 clock-names = "clk_main\0clk_apb"; 250 xlnx,bus-width = < 0x80 >; 251 clocks = < 0x05 0x04 >; 252 }; 253 254 dma@fd560000 { 255 status = "okay"; 256 compatible = "xlnx,zynqmp-dma-1.0"; 257 reg = < 0x00 0xfd560000 0x00 0x1000 >; 258 interrupt-parent = < 0x03 >; 259 interrupts = < 0x00 0x82 0x04 >; 260 clock-names = "clk_main\0clk_apb"; 261 xlnx,bus-width = < 0x80 >; 262 clocks = < 0x05 0x04 >; 263 }; 264 265 dma@fd570000 { 266 status = "okay"; 267 compatible = "xlnx,zynqmp-dma-1.0"; 268 reg = < 0x00 0xfd570000 0x00 0x1000 >; 269 interrupt-parent = < 0x03 >; 270 interrupts = < 0x00 0x83 0x04 >; 271 clock-names = "clk_main\0clk_apb"; 272 xlnx,bus-width = < 0x80 >; 273 clocks = < 0x05 0x04 >; 274 }; 275 276 dma@ffa80000 { 277 status = "disabled"; 278 compatible = "xlnx,zynqmp-dma-1.0"; 279 reg = < 0x00 0xffa80000 0x00 0x1000 >; 280 interrupt-parent = < 0x03 >; 281 interrupts = < 0x00 0x4d 0x04 >; 282 clock-names = "clk_main\0clk_apb"; 283 xlnx,bus-width = < 0x40 >; 284 clocks = < 0x05 0x04 >; 285 }; 286 287 dma@ffa90000 { 288 status = "disabled"; 289 compatible = "xlnx,zynqmp-dma-1.0"; 290 reg = < 0x00 0xffa90000 0x00 0x1000 >; 291 interrupt-parent = < 0x03 >; 292 interrupts = < 0x00 0x4e 0x04 >; 293 clock-names = "clk_main\0clk_apb"; 294 xlnx,bus-width = < 0x40 >; 295 clocks = < 0x05 0x04 >; 296 }; 297 298 dma@ffaa0000 { 299 status = "disabled"; 300 compatible = "xlnx,zynqmp-dma-1.0"; 301 reg = < 0x00 0xffaa0000 0x00 0x1000 >; 302 interrupt-parent = < 0x03 >; 303 interrupts = < 0x00 0x4f 0x04 >; 304 clock-names = "clk_main\0clk_apb"; 305 xlnx,bus-width = < 0x40 >; 306 clocks = < 0x05 0x04 >; 307 }; 308 309 dma@ffab0000 { 310 status = "disabled"; 311 compatible = "xlnx,zynqmp-dma-1.0"; 312 reg = < 0x00 0xffab0000 0x00 0x1000 >; 313 interrupt-parent = < 0x03 >; 314 interrupts = < 0x00 0x50 0x04 >; 315 clock-names = "clk_main\0clk_apb"; 316 xlnx,bus-width = < 0x40 >; 317 clocks = < 0x05 0x04 >; 318 }; 319 320 dma@ffac0000 { 321 status = "disabled"; 322 compatible = "xlnx,zynqmp-dma-1.0"; 323 reg = < 0x00 0xffac0000 0x00 0x1000 >; 324 interrupt-parent = < 0x03 >; 325 interrupts = < 0x00 0x51 0x04 >; 326 clock-names = "clk_main\0clk_apb"; 327 xlnx,bus-width = < 0x40 >; 328 clocks = < 0x05 0x04 >; 329 }; 330 331 dma@ffad0000 { 332 status = "disabled"; 333 compatible = "xlnx,zynqmp-dma-1.0"; 334 reg = < 0x00 0xffad0000 0x00 0x1000 >; 335 interrupt-parent = < 0x03 >; 336 interrupts = < 0x00 0x52 0x04 >; 337 clock-names = "clk_main\0clk_apb"; 338 xlnx,bus-width = < 0x40 >; 339 clocks = < 0x05 0x04 >; 340 }; 341 342 dma@ffae0000 { 343 status = "disabled"; 344 compatible = "xlnx,zynqmp-dma-1.0"; 345 reg = < 0x00 0xffae0000 0x00 0x1000 >; 346 interrupt-parent = < 0x03 >; 347 interrupts = < 0x00 0x53 0x04 >; 348 clock-names = "clk_main\0clk_apb"; 349 xlnx,bus-width = < 0x40 >; 350 clocks = < 0x05 0x04 >; 351 }; 352 353 dma@ffaf0000 { 354 status = "disabled"; 355 compatible = "xlnx,zynqmp-dma-1.0"; 356 reg = < 0x00 0xffaf0000 0x00 0x1000 >; 357 interrupt-parent = < 0x03 >; 358 interrupts = < 0x00 0x54 0x04 >; 359 clock-names = "clk_main\0clk_apb"; 360 xlnx,bus-width = < 0x40 >; 361 clocks = < 0x05 0x04 >; 362 }; 363 364 ethernet@ff0b0000 { 365 compatible = "cdns,zynqmp-gem\0cdns,gem"; 366 status = "disabled"; 367 interrupt-parent = < 0x03 >; 368 interrupts = < 0x00 0x39 0x04 0x00 0x39 0x04 >; 369 reg = < 0x00 0xff0b0000 0x00 0x1000 >; 370 clock-names = "pclk\0hclk\0tx_clk"; 371 #address-cells = < 0x01 >; 372 #size-cells = < 0x00 >; 373 clocks = < 0x06 0x06 0x06 >; 374 }; 375 376 ethernet@ff0c0000 { 377 compatible = "cdns,zynqmp-gem\0cdns,gem"; 378 status = "disabled"; 379 interrupt-parent = < 0x03 >; 380 interrupts = < 0x00 0x3b 0x04 0x00 0x3b 0x04 >; 381 reg = < 0x00 0xff0c0000 0x00 0x1000 >; 382 clock-names = "pclk\0hclk\0tx_clk"; 383 #address-cells = < 0x01 >; 384 #size-cells = < 0x00 >; 385 clocks = < 0x06 0x06 0x06 >; 386 }; 387 388 ethernet@ff0d0000 { 389 compatible = "cdns,zynqmp-gem\0cdns,gem"; 390 status = "disabled"; 391 interrupt-parent = < 0x03 >; 392 interrupts = < 0x00 0x3d 0x04 0x00 0x3d 0x04 >; 393 reg = < 0x00 0xff0d0000 0x00 0x1000 >; 394 clock-names = "pclk\0hclk\0tx_clk"; 395 #address-cells = < 0x01 >; 396 #size-cells = < 0x00 >; 397 clocks = < 0x06 0x06 0x06 >; 398 }; 399 400 ethernet@ff0e0000 { 401 compatible = "cdns,zynqmp-gem\0cdns,gem"; 402 status = "okay"; 403 interrupt-parent = < 0x03 >; 404 interrupts = < 0x00 0x3f 0x04 0x00 0x3f 0x04 >; 405 reg = < 0x00 0xff0e0000 0x00 0x1000 >; 406 clock-names = "pclk\0hclk\0tx_clk"; 407 #address-cells = < 0x01 >; 408 #size-cells = < 0x00 >; 409 clocks = < 0x06 0x06 0x06 >; 410 phy-handle = < 0x07 >; 411 phy-mode = "rgmii-id"; 412 413 phy@c { 414 reg = < 0x0c >; 415 ti,rx-internal-delay = < 0x08 >; 416 ti,tx-internal-delay = < 0x0a >; 417 ti,fifo-depth = < 0x01 >; 418 phandle = < 0x07 >; 419 }; 420 }; 421 422 gpio@ff0a0000 { 423 compatible = "xlnx,zynqmp-gpio-1.0"; 424 status = "okay"; 425 #gpio-cells = < 0x02 >; 426 interrupt-parent = < 0x03 >; 427 interrupts = < 0x00 0x10 0x04 >; 428 interrupt-controller; 429 #interrupt-cells = < 0x02 >; 430 reg = < 0x00 0xff0a0000 0x00 0x1000 >; 431 clocks = < 0x04 >; 432 phandle = < 0x0c >; 433 }; 434 435 i2c@ff020000 { 436 compatible = "cdns,i2c-r1p14\0cdns,i2c-r1p10"; 437 status = "okay"; 438 interrupt-parent = < 0x03 >; 439 interrupts = < 0x00 0x11 0x04 >; 440 reg = < 0x00 0xff020000 0x00 0x1000 >; 441 #address-cells = < 0x01 >; 442 #size-cells = < 0x00 >; 443 clocks = < 0x04 >; 444 clock-frequency = < 0x61a80 >; 445 446 gpio@20 { 447 compatible = "ti,tca6416"; 448 reg = < 0x20 >; 449 gpio-controller; 450 #gpio-cells = < 0x02 >; 451 452 gtr_sel0 { 453 gpio-hog; 454 gpios = < 0x00 0x00 >; 455 output-low; 456 line-name = "sel0"; 457 }; 458 459 gtr_sel1 { 460 gpio-hog; 461 gpios = < 0x01 0x00 >; 462 output-high; 463 line-name = "sel1"; 464 }; 465 466 gtr_sel2 { 467 gpio-hog; 468 gpios = < 0x02 0x00 >; 469 output-high; 470 line-name = "sel2"; 471 }; 472 473 gtr_sel3 { 474 gpio-hog; 475 gpios = < 0x03 0x00 >; 476 output-high; 477 line-name = "sel3"; 478 }; 479 }; 480 481 gpio@21 { 482 compatible = "ti,tca6416"; 483 reg = < 0x21 >; 484 gpio-controller; 485 #gpio-cells = < 0x02 >; 486 }; 487 488 i2c-mux@75 { 489 compatible = "nxp,pca9544"; 490 #address-cells = < 0x01 >; 491 #size-cells = < 0x00 >; 492 reg = < 0x75 >; 493 494 i2c@0 { 495 #address-cells = < 0x01 >; 496 #size-cells = < 0x00 >; 497 reg = < 0x00 >; 498 499 ina226@40 { 500 compatible = "ti,ina226"; 501 reg = < 0x40 >; 502 shunt-resistor = < 0x1388 >; 503 }; 504 505 ina226@41 { 506 compatible = "ti,ina226"; 507 reg = < 0x41 >; 508 shunt-resistor = < 0x1388 >; 509 }; 510 511 ina226@42 { 512 compatible = "ti,ina226"; 513 reg = < 0x42 >; 514 shunt-resistor = < 0x1388 >; 515 }; 516 517 ina226@43 { 518 compatible = "ti,ina226"; 519 reg = < 0x43 >; 520 shunt-resistor = < 0x1388 >; 521 }; 522 523 ina226@44 { 524 compatible = "ti,ina226"; 525 reg = < 0x44 >; 526 shunt-resistor = < 0x1388 >; 527 }; 528 529 ina226@45 { 530 compatible = "ti,ina226"; 531 reg = < 0x45 >; 532 shunt-resistor = < 0x1388 >; 533 }; 534 535 ina226@46 { 536 compatible = "ti,ina226"; 537 reg = < 0x46 >; 538 shunt-resistor = < 0x1388 >; 539 }; 540 541 ina226@47 { 542 compatible = "ti,ina226"; 543 reg = < 0x47 >; 544 shunt-resistor = < 0x1388 >; 545 }; 546 547 ina226@4a { 548 compatible = "ti,ina226"; 549 reg = < 0x4a >; 550 shunt-resistor = < 0x1388 >; 551 }; 552 553 ina226@4b { 554 compatible = "ti,ina226"; 555 reg = < 0x4b >; 556 shunt-resistor = < 0x1388 >; 557 }; 558 }; 559 560 i2c@1 { 561 #address-cells = < 0x01 >; 562 #size-cells = < 0x00 >; 563 reg = < 0x01 >; 564 565 ina226@40 { 566 compatible = "ti,ina226"; 567 reg = < 0x40 >; 568 shunt-resistor = < 0x7d0 >; 569 }; 570 571 ina226@41 { 572 compatible = "ti,ina226"; 573 reg = < 0x41 >; 574 shunt-resistor = < 0x1388 >; 575 }; 576 577 ina226@42 { 578 compatible = "ti,ina226"; 579 reg = < 0x42 >; 580 shunt-resistor = < 0x1388 >; 581 }; 582 583 ina226@43 { 584 compatible = "ti,ina226"; 585 reg = < 0x43 >; 586 shunt-resistor = < 0x1388 >; 587 }; 588 589 ina226@44 { 590 compatible = "ti,ina226"; 591 reg = < 0x44 >; 592 shunt-resistor = < 0x1388 >; 593 }; 594 595 ina226@45 { 596 compatible = "ti,ina226"; 597 reg = < 0x45 >; 598 shunt-resistor = < 0x1388 >; 599 }; 600 601 ina226@46 { 602 compatible = "ti,ina226"; 603 reg = < 0x46 >; 604 shunt-resistor = < 0x1388 >; 605 }; 606 607 ina226@47 { 608 compatible = "ti,ina226"; 609 reg = < 0x47 >; 610 shunt-resistor = < 0x1388 >; 611 }; 612 }; 613 614 i2c@2 { 615 #address-cells = < 0x01 >; 616 #size-cells = < 0x00 >; 617 reg = < 0x02 >; 618 619 max15301@a { 620 compatible = "maxim,max15301"; 621 reg = < 0x0a >; 622 }; 623 624 max15303@b { 625 compatible = "maxim,max15303"; 626 reg = < 0x0b >; 627 }; 628 629 max15303@10 { 630 compatible = "maxim,max15303"; 631 reg = < 0x10 >; 632 }; 633 634 max15301@13 { 635 compatible = "maxim,max15301"; 636 reg = < 0x13 >; 637 }; 638 639 max15303@14 { 640 compatible = "maxim,max15303"; 641 reg = < 0x14 >; 642 }; 643 644 max15303@15 { 645 compatible = "maxim,max15303"; 646 reg = < 0x15 >; 647 }; 648 649 max15303@16 { 650 compatible = "maxim,max15303"; 651 reg = < 0x16 >; 652 }; 653 654 max15303@17 { 655 compatible = "maxim,max15303"; 656 reg = < 0x17 >; 657 }; 658 659 max15301@18 { 660 compatible = "maxim,max15301"; 661 reg = < 0x18 >; 662 }; 663 664 max15303@1a { 665 compatible = "maxim,max15303"; 666 reg = < 0x1a >; 667 }; 668 669 max15303@1d { 670 compatible = "maxim,max15303"; 671 reg = < 0x1d >; 672 }; 673 674 max20751@72 { 675 compatible = "maxim,max20751"; 676 reg = < 0x72 >; 677 }; 678 679 max20751@73 { 680 compatible = "maxim,max20751"; 681 reg = < 0x73 >; 682 }; 683 684 max15303@1b { 685 compatible = "maxim,max15303"; 686 reg = < 0x1b >; 687 }; 688 }; 689 }; 690 }; 691 692 i2c@ff030000 { 693 compatible = "cdns,i2c-r1p14\0cdns,i2c-r1p10"; 694 status = "okay"; 695 interrupt-parent = < 0x03 >; 696 interrupts = < 0x00 0x12 0x04 >; 697 reg = < 0x00 0xff030000 0x00 0x1000 >; 698 #address-cells = < 0x01 >; 699 #size-cells = < 0x00 >; 700 clocks = < 0x04 >; 701 clock-frequency = < 0x61a80 >; 702 703 i2c-mux@74 { 704 compatible = "nxp,pca9548"; 705 #address-cells = < 0x01 >; 706 #size-cells = < 0x00 >; 707 reg = < 0x74 >; 708 709 i2c@0 { 710 #address-cells = < 0x01 >; 711 #size-cells = < 0x00 >; 712 reg = < 0x00 >; 713 714 eeprom@54 { 715 compatible = "atmel,24c08"; 716 reg = < 0x54 >; 717 #address-cells = < 0x01 >; 718 #size-cells = < 0x01 >; 719 720 board-sn@0 { 721 reg = < 0x00 0x14 >; 722 }; 723 724 eth-mac@20 { 725 reg = < 0x20 0x06 >; 726 }; 727 728 board-name@d0 { 729 reg = < 0xd0 0x06 >; 730 }; 731 732 board-revision@e0 { 733 reg = < 0xe0 0x03 >; 734 }; 735 }; 736 }; 737 738 i2c@1 { 739 #address-cells = < 0x01 >; 740 #size-cells = < 0x00 >; 741 reg = < 0x01 >; 742 743 clock-generator@36 { 744 reg = < 0x36 >; 745 }; 746 }; 747 748 i2c@2 { 749 #address-cells = < 0x01 >; 750 #size-cells = < 0x00 >; 751 reg = < 0x02 >; 752 753 clock-generator@5d { 754 #clock-cells = < 0x00 >; 755 compatible = "silabs,si570"; 756 reg = < 0x5d >; 757 temperature-stability = < 0x32 >; 758 factory-fout = < 0x11e1a300 >; 759 clock-frequency = < 0x11e1a300 >; 760 }; 761 }; 762 763 i2c@3 { 764 #address-cells = < 0x01 >; 765 #size-cells = < 0x00 >; 766 reg = < 0x03 >; 767 768 clock-generator@5d { 769 #clock-cells = < 0x00 >; 770 compatible = "silabs,si570"; 771 reg = < 0x5d >; 772 temperature-stability = < 0x32 >; 773 factory-fout = < 0x9502f90 >; 774 clock-frequency = < 0x8d9ee20 >; 775 }; 776 }; 777 778 i2c@4 { 779 #address-cells = < 0x01 >; 780 #size-cells = < 0x00 >; 781 reg = < 0x04 >; 782 783 clock-generator@69 { 784 reg = < 0x69 >; 785 }; 786 }; 787 }; 788 789 i2c-mux@75 { 790 compatible = "nxp,pca9548"; 791 #address-cells = < 0x01 >; 792 #size-cells = < 0x00 >; 793 reg = < 0x75 >; 794 795 i2c@0 { 796 #address-cells = < 0x01 >; 797 #size-cells = < 0x00 >; 798 reg = < 0x00 >; 799 }; 800 801 i2c@1 { 802 #address-cells = < 0x01 >; 803 #size-cells = < 0x00 >; 804 reg = < 0x01 >; 805 }; 806 807 i2c@2 { 808 #address-cells = < 0x01 >; 809 #size-cells = < 0x00 >; 810 reg = < 0x02 >; 811 }; 812 813 i2c@3 { 814 #address-cells = < 0x01 >; 815 #size-cells = < 0x00 >; 816 reg = < 0x03 >; 817 }; 818 819 i2c@4 { 820 #address-cells = < 0x01 >; 821 #size-cells = < 0x00 >; 822 reg = < 0x04 >; 823 }; 824 825 i2c@5 { 826 #address-cells = < 0x01 >; 827 #size-cells = < 0x00 >; 828 reg = < 0x05 >; 829 }; 830 831 i2c@6 { 832 #address-cells = < 0x01 >; 833 #size-cells = < 0x00 >; 834 reg = < 0x06 >; 835 }; 836 837 i2c@7 { 838 #address-cells = < 0x01 >; 839 #size-cells = < 0x00 >; 840 reg = < 0x07 >; 841 }; 842 }; 843 }; 844 845 pcie@fd0e0000 { 846 compatible = "xlnx,nwl-pcie-2.11"; 847 status = "okay"; 848 #address-cells = < 0x03 >; 849 #size-cells = < 0x02 >; 850 #interrupt-cells = < 0x01 >; 851 msi-controller; 852 device_type = "pci"; 853 interrupt-parent = < 0x03 >; 854 interrupts = < 0x00 0x76 0x04 0x00 0x75 0x04 0x00 0x74 0x04 0x00 0x73 0x04 0x00 0x72 0x04 >; 855 interrupt-names = "misc\0dummy\0intx\0msi1\0msi0"; 856 msi-parent = < 0x08 >; 857 reg = < 0x00 0xfd0e0000 0x00 0x1000 0x00 0xfd480000 0x00 0x1000 0x80 0x00 0x00 0x1000000 >; 858 reg-names = "breg\0pcireg\0cfg"; 859 ranges = < 0x2000000 0x00 0xe0000000 0x00 0xe0000000 0x00 0x10000000 0x43000000 0x06 0x00 0x06 0x00 0x02 0x00 >; 860 bus-range = < 0x00 0xff >; 861 interrupt-map-mask = < 0x00 0x00 0x00 0x07 >; 862 interrupt-map = < 0x00 0x00 0x00 0x01 0x09 0x01 0x00 0x00 0x00 0x02 0x09 0x02 0x00 0x00 0x00 0x03 0x09 0x03 0x00 0x00 0x00 0x04 0x09 0x04 >; 863 phandle = < 0x08 >; 864 865 legacy-interrupt-controller { 866 interrupt-controller; 867 #address-cells = < 0x00 >; 868 #interrupt-cells = < 0x01 >; 869 phandle = < 0x09 >; 870 }; 871 }; 872 873 rtc@ffa60000 { 874 compatible = "xlnx,zynqmp-rtc"; 875 status = "okay"; 876 reg = < 0x00 0xffa60000 0x00 0x100 >; 877 interrupt-parent = < 0x03 >; 878 interrupts = < 0x00 0x1a 0x04 0x00 0x1b 0x04 >; 879 interrupt-names = "alarm\0sec"; 880 calibration = < 0x8000 >; 881 }; 882 883 ahci@fd0c0000 { 884 compatible = "ceva,ahci-1v84"; 885 status = "okay"; 886 reg = < 0x00 0xfd0c0000 0x00 0x2000 >; 887 interrupt-parent = < 0x03 >; 888 interrupts = < 0x00 0x85 0x04 >; 889 clocks = < 0x0a >; 890 ceva,p0-cominit-params = < 0x18401828 >; 891 ceva,p0-comwake-params = < 0x614080e >; 892 ceva,p0-burst-params = < 0x13084a06 >; 893 ceva,p0-retry-params = < 0x96a43ffc >; 894 ceva,p1-cominit-params = < 0x18401828 >; 895 ceva,p1-comwake-params = < 0x614080e >; 896 ceva,p1-burst-params = < 0x13084a06 >; 897 ceva,p1-retry-params = < 0x96a43ffc >; 898 }; 899 900 sdhci@ff160000 { 901 compatible = "arasan,sdhci-8.9a"; 902 status = "disabled"; 903 interrupt-parent = < 0x03 >; 904 interrupts = < 0x00 0x30 0x04 >; 905 reg = < 0x00 0xff160000 0x00 0x1000 >; 906 clock-names = "clk_xin\0clk_ahb"; 907 clocks = < 0x0b 0x0b >; 908 }; 909 910 sdhci@ff170000 { 911 compatible = "arasan,sdhci-8.9a"; 912 status = "okay"; 913 interrupt-parent = < 0x03 >; 914 interrupts = < 0x00 0x31 0x04 >; 915 reg = < 0x00 0xff170000 0x00 0x1000 >; 916 clock-names = "clk_xin\0clk_ahb"; 917 clocks = < 0x0b 0x0b >; 918 no-1-8-v; 919 }; 920 921 smmu@fd800000 { 922 compatible = "arm,mmu-500"; 923 reg = < 0x00 0xfd800000 0x00 0x20000 >; 924 status = "disabled"; 925 #global-interrupts = < 0x01 >; 926 interrupt-parent = < 0x03 >; 927 interrupts = < 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 >; 928 }; 929 930 spi@ff040000 { 931 compatible = "cdns,spi-r1p6"; 932 status = "disabled"; 933 interrupt-parent = < 0x03 >; 934 interrupts = < 0x00 0x13 0x04 >; 935 reg = < 0x00 0xff040000 0x00 0x1000 >; 936 clock-names = "ref_clk\0pclk"; 937 #address-cells = < 0x01 >; 938 #size-cells = < 0x00 >; 939 clocks = < 0x0b 0x0b >; 940 }; 941 942 spi@ff050000 { 943 compatible = "cdns,spi-r1p6"; 944 status = "disabled"; 945 interrupt-parent = < 0x03 >; 946 interrupts = < 0x00 0x14 0x04 >; 947 reg = < 0x00 0xff050000 0x00 0x1000 >; 948 clock-names = "ref_clk\0pclk"; 949 #address-cells = < 0x01 >; 950 #size-cells = < 0x00 >; 951 clocks = < 0x0b 0x0b >; 952 }; 953 954 timer@ff110000 { 955 compatible = "cdns,ttc"; 956 status = "disabled"; 957 interrupt-parent = < 0x03 >; 958 interrupts = < 0x00 0x24 0x04 0x00 0x25 0x04 0x00 0x26 0x04 >; 959 reg = < 0x00 0xff110000 0x00 0x1000 >; 960 timer-width = < 0x20 >; 961 }; 962 963 timer@ff120000 { 964 compatible = "cdns,ttc"; 965 status = "disabled"; 966 interrupt-parent = < 0x03 >; 967 interrupts = < 0x00 0x27 0x04 0x00 0x28 0x04 0x00 0x29 0x04 >; 968 reg = < 0x00 0xff120000 0x00 0x1000 >; 969 timer-width = < 0x20 >; 970 }; 971 972 timer@ff130000 { 973 compatible = "cdns,ttc"; 974 status = "disabled"; 975 interrupt-parent = < 0x03 >; 976 interrupts = < 0x00 0x2a 0x04 0x00 0x2b 0x04 0x00 0x2c 0x04 >; 977 reg = < 0x00 0xff130000 0x00 0x1000 >; 978 timer-width = < 0x20 >; 979 }; 980 981 timer@ff140000 { 982 compatible = "cdns,ttc"; 983 status = "disabled"; 984 interrupt-parent = < 0x03 >; 985 interrupts = < 0x00 0x2d 0x04 0x00 0x2e 0x04 0x00 0x2f 0x04 >; 986 reg = < 0x00 0xff140000 0x00 0x1000 >; 987 timer-width = < 0x20 >; 988 }; 989 990 serial@ff000000 { 991 compatible = "cdns,uart-r1p12\0xlnx,xuartps"; 992 status = "okay"; 993 interrupt-parent = < 0x03 >; 994 interrupts = < 0x00 0x15 0x04 >; 995 reg = < 0x00 0xff000000 0x00 0x1000 >; 996 clock-names = "uart_clk\0pclk"; 997 clocks = < 0x04 0x04 >; 998 }; 999 1000 serial@ff010000 { 1001 compatible = "cdns,uart-r1p12\0xlnx,xuartps"; 1002 status = "okay"; 1003 interrupt-parent = < 0x03 >; 1004 interrupts = < 0x00 0x16 0x04 >; 1005 reg = < 0x00 0xff010000 0x00 0x1000 >; 1006 clock-names = "uart_clk\0pclk"; 1007 clocks = < 0x04 0x04 >; 1008 }; 1009 1010 usb@fe200000 { 1011 compatible = "snps,dwc3"; 1012 status = "okay"; 1013 interrupt-parent = < 0x03 >; 1014 interrupts = < 0x00 0x41 0x04 >; 1015 reg = < 0x00 0xfe200000 0x00 0x40000 >; 1016 clock-names = "clk_xin\0clk_ahb"; 1017 clocks = < 0x0a 0x0a >; 1018 }; 1019 1020 usb@fe300000 { 1021 compatible = "snps,dwc3"; 1022 status = "disabled"; 1023 interrupt-parent = < 0x03 >; 1024 interrupts = < 0x00 0x46 0x04 >; 1025 reg = < 0x00 0xfe300000 0x00 0x40000 >; 1026 clock-names = "clk_xin\0clk_ahb"; 1027 clocks = < 0x0a 0x0a >; 1028 }; 1029 1030 watchdog@fd4d0000 { 1031 compatible = "cdns,wdt-r1p2"; 1032 status = "okay"; 1033 interrupt-parent = < 0x03 >; 1034 interrupts = < 0x00 0x71 0x01 >; 1035 reg = < 0x00 0xfd4d0000 0x00 0x1000 >; 1036 timeout-sec = < 0x0a >; 1037 clocks = < 0x0a >; 1038 }; 1039 }; 1040 1041 clk100 { 1042 compatible = "fixed-clock"; 1043 #clock-cells = < 0x00 >; 1044 clock-frequency = < 0x5f5e100 >; 1045 phandle = < 0x04 >; 1046 }; 1047 1048 clk125 { 1049 compatible = "fixed-clock"; 1050 #clock-cells = < 0x00 >; 1051 clock-frequency = < 0x7735940 >; 1052 phandle = < 0x06 >; 1053 }; 1054 1055 clk200 { 1056 compatible = "fixed-clock"; 1057 #clock-cells = < 0x00 >; 1058 clock-frequency = < 0xbebc200 >; 1059 phandle = < 0x0b >; 1060 }; 1061 1062 clk250 { 1063 compatible = "fixed-clock"; 1064 #clock-cells = < 0x00 >; 1065 clock-frequency = < 0xee6b280 >; 1066 phandle = < 0x0a >; 1067 }; 1068 1069 clk300 { 1070 compatible = "fixed-clock"; 1071 #clock-cells = < 0x00 >; 1072 clock-frequency = < 0x11e1a300 >; 1073 }; 1074 1075 clk600 { 1076 compatible = "fixed-clock"; 1077 #clock-cells = < 0x00 >; 1078 clock-frequency = < 0x23c34600 >; 1079 phandle = < 0x05 >; 1080 }; 1081 1082 clock0 { 1083 compatible = "fixed-clock"; 1084 #clock-cells = < 0x00 >; 1085 clock-frequency = < 0x5f5e100 >; 1086 clock-accuracy = < 0x64 >; 1087 }; 1088 1089 clock1 { 1090 compatible = "fixed-clock"; 1091 #clock-cells = < 0x00 >; 1092 clock-frequency = < 0x1770000 >; 1093 clock-accuracy = < 0x64 >; 1094 }; 1095 1096 dpdma_clk { 1097 compatible = "fixed-clock"; 1098 #clock-cells = < 0x00 >; 1099 clock-frequency = < 0x1fc4ef40 >; 1100 }; 1101 1102 drm_clock { 1103 compatible = "fixed-clock"; 1104 #clock-cells = < 0x00 >; 1105 clock-frequency = < 0xfa93f30 >; 1106 clock-accuracy = < 0x64 >; 1107 }; 1108 1109 aliases { 1110 ethernet0 = "/amba/ethernet@ff0e0000"; 1111 i2c0 = "/amba/i2c@ff020000"; 1112 i2c1 = "/amba/i2c@ff030000"; 1113 mmc0 = "/amba/sdhci@ff170000"; 1114 rtc0 = "/amba/rtc@ffa60000"; 1115 serial0 = "/amba/serial@ff000000"; 1116 serial1 = "/amba/serial@ff010000"; 1117 serial2 = "/dcc"; 1118 }; 1119 1120 chosen { 1121 bootargs = "earlycon"; 1122 stdout-path = "serial0:115200n8"; 1123 }; 1124 1125 memory@0 { 1126 device_type = "memory"; 1127 reg = < 0x00 0x00 0x00 0x80000000 0x08 0x00 0x00 0x80000000 >; 1128 }; 1129 1130 gpio-keys { 1131 compatible = "gpio-keys"; 1132 autorepeat; 1133 1134 sw19 { 1135 label = "sw19"; 1136 gpios = < 0x0c 0x16 0x00 >; 1137 linux,code = < 0x6c >; 1138 gpio-key,wakeup; 1139 autorepeat; 1140 }; 1141 }; 1142 1143 leds { 1144 compatible = "gpio-leds"; 1145 1146 heartbeat_led { 1147 label = "heartbeat"; 1148 gpios = < 0x0c 0x17 0x00 >; 1149 linux,default-trigger = "heartbeat"; 1150 }; 1151 }; 1152}; 1153