1/*
2 * Copyright Linux Kernel Team
3 *
4 * SPDX-License-Identifier: GPL-2.0-only
5 *
6 * This file is derived from an intermediate build stage of the
7 * Linux kernel. The licenses of all input files to this process
8 * are compatible with GPL-2.0-only.
9 */
10
11/dts-v1/;
12
13/ {
14	#address-cells = < 0x01 >;
15	#size-cells = < 0x01 >;
16	compatible = "xlnx,zynq-zc706\0xlnx,zynq-7000";
17	model = "Xilinx ZC706 board";
18
19	cpus {
20		#address-cells = < 0x01 >;
21		#size-cells = < 0x00 >;
22
23		cpu@0 {
24			compatible = "arm,cortex-a9";
25			device_type = "cpu";
26			reg = < 0x00 >;
27			clocks = < 0x01 0x03 >;
28			clock-latency = < 0x3e8 >;
29			cpu0-supply = < 0x02 >;
30			operating-points = < 0xa2c2b 0xf4240 0x51616 0xf4240 >;
31		};
32
33		cpu@1 {
34			compatible = "arm,cortex-a9";
35			device_type = "cpu";
36			reg = < 0x01 >;
37			clocks = < 0x01 0x03 >;
38		};
39	};
40
41	fpga-full {
42		compatible = "fpga-region";
43		fpga-mgr = < 0x03 >;
44		#address-cells = < 0x01 >;
45		#size-cells = < 0x01 >;
46		ranges;
47	};
48
49	pmu@f8891000 {
50		compatible = "arm,cortex-a9-pmu";
51		interrupts = < 0x00 0x05 0x04 0x00 0x06 0x04 >;
52		interrupt-parent = < 0x04 >;
53		reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
54	};
55
56	fixedregulator {
57		compatible = "regulator-fixed";
58		regulator-name = "VCCPINT";
59		regulator-min-microvolt = < 0xf4240 >;
60		regulator-max-microvolt = < 0xf4240 >;
61		regulator-boot-on;
62		regulator-always-on;
63		phandle = < 0x02 >;
64	};
65
66	amba {
67		compatible = "simple-bus";
68		#address-cells = < 0x01 >;
69		#size-cells = < 0x01 >;
70		interrupt-parent = < 0x04 >;
71		ranges;
72
73		adc@f8007100 {
74			compatible = "xlnx,zynq-xadc-1.00.a";
75			reg = < 0xf8007100 0x20 >;
76			interrupts = < 0x00 0x07 0x04 >;
77			interrupt-parent = < 0x04 >;
78			clocks = < 0x01 0x0c >;
79		};
80
81		can@e0008000 {
82			compatible = "xlnx,zynq-can-1.0";
83			status = "disabled";
84			clocks = < 0x01 0x13 0x01 0x24 >;
85			clock-names = "can_clk\0pclk";
86			reg = < 0xe0008000 0x1000 >;
87			interrupts = < 0x00 0x1c 0x04 >;
88			interrupt-parent = < 0x04 >;
89			tx-fifo-depth = < 0x40 >;
90			rx-fifo-depth = < 0x40 >;
91		};
92
93		can@e0009000 {
94			compatible = "xlnx,zynq-can-1.0";
95			status = "disabled";
96			clocks = < 0x01 0x14 0x01 0x25 >;
97			clock-names = "can_clk\0pclk";
98			reg = < 0xe0009000 0x1000 >;
99			interrupts = < 0x00 0x33 0x04 >;
100			interrupt-parent = < 0x04 >;
101			tx-fifo-depth = < 0x40 >;
102			rx-fifo-depth = < 0x40 >;
103		};
104
105		gpio@e000a000 {
106			compatible = "xlnx,zynq-gpio-1.0";
107			#gpio-cells = < 0x02 >;
108			clocks = < 0x01 0x2a >;
109			gpio-controller;
110			interrupt-controller;
111			#interrupt-cells = < 0x02 >;
112			interrupt-parent = < 0x04 >;
113			interrupts = < 0x00 0x14 0x04 >;
114			reg = < 0xe000a000 0x1000 >;
115			pinctrl-names = "default";
116			pinctrl-0 = < 0x05 >;
117		};
118
119		i2c@e0004000 {
120			compatible = "cdns,i2c-r1p10";
121			status = "okay";
122			clocks = < 0x01 0x26 >;
123			interrupt-parent = < 0x04 >;
124			interrupts = < 0x00 0x19 0x04 >;
125			reg = < 0xe0004000 0x1000 >;
126			#address-cells = < 0x01 >;
127			#size-cells = < 0x00 >;
128			clock-frequency = < 0x61a80 >;
129			pinctrl-names = "default";
130			pinctrl-0 = < 0x06 >;
131
132			i2c-mux@74 {
133				compatible = "nxp,pca9548";
134				#address-cells = < 0x01 >;
135				#size-cells = < 0x00 >;
136				reg = < 0x74 >;
137
138				i2c@0 {
139					#address-cells = < 0x01 >;
140					#size-cells = < 0x00 >;
141					reg = < 0x00 >;
142
143					clock-generator@5d {
144						#clock-cells = < 0x00 >;
145						compatible = "silabs,si570";
146						temperature-stability = < 0x32 >;
147						reg = < 0x5d >;
148						factory-fout = < 0x9502f90 >;
149						clock-frequency = < 0x8d9ee20 >;
150					};
151				};
152
153				i2c@1 {
154					#address-cells = < 0x01 >;
155					#size-cells = < 0x00 >;
156					reg = < 0x01 >;
157
158					hdmi-tx@39 {
159						compatible = "adi,adv7511";
160						reg = < 0x39 >;
161						adi,input-depth = < 0x08 >;
162						adi,input-colorspace = "yuv422";
163						adi,input-clock = "1x";
164						adi,input-style = < 0x03 >;
165						adi,input-justification = "evenly";
166					};
167				};
168
169				i2c@2 {
170					#address-cells = < 0x01 >;
171					#size-cells = < 0x00 >;
172					reg = < 0x02 >;
173
174					eeprom@54 {
175						compatible = "atmel,24c08";
176						reg = < 0x54 >;
177					};
178				};
179
180				i2c@3 {
181					#address-cells = < 0x01 >;
182					#size-cells = < 0x00 >;
183					reg = < 0x03 >;
184
185					gpio@21 {
186						compatible = "ti,tca6416";
187						reg = < 0x21 >;
188						gpio-controller;
189						#gpio-cells = < 0x02 >;
190					};
191				};
192
193				i2c@4 {
194					#address-cells = < 0x01 >;
195					#size-cells = < 0x00 >;
196					reg = < 0x04 >;
197
198					rtc@51 {
199						compatible = "nxp,pcf8563";
200						reg = < 0x51 >;
201					};
202				};
203
204				i2c@7 {
205					#address-cells = < 0x01 >;
206					#size-cells = < 0x00 >;
207					reg = < 0x07 >;
208
209					ucd90120@65 {
210						compatible = "ti,ucd90120";
211						reg = < 0x65 >;
212					};
213				};
214			};
215		};
216
217		i2c@e0005000 {
218			compatible = "cdns,i2c-r1p10";
219			status = "disabled";
220			clocks = < 0x01 0x27 >;
221			interrupt-parent = < 0x04 >;
222			interrupts = < 0x00 0x30 0x04 >;
223			reg = < 0xe0005000 0x1000 >;
224			#address-cells = < 0x01 >;
225			#size-cells = < 0x00 >;
226		};
227
228		interrupt-controller@f8f01000 {
229			compatible = "arm,cortex-a9-gic";
230			#interrupt-cells = < 0x03 >;
231			interrupt-controller;
232			reg = < 0xf8f01000 0x1000 0xf8f00100 0x100 >;
233			phandle = < 0x04 >;
234		};
235
236		cache-controller@f8f02000 {
237			compatible = "arm,pl310-cache";
238			reg = < 0xf8f02000 0x1000 >;
239			interrupts = < 0x00 0x02 0x04 >;
240			arm,data-latency = < 0x03 0x02 0x02 >;
241			arm,tag-latency = < 0x02 0x02 0x02 >;
242			cache-unified;
243			cache-level = < 0x02 >;
244		};
245
246		memory-controller@f8006000 {
247			compatible = "xlnx,zynq-ddrc-a05";
248			reg = < 0xf8006000 0x1000 >;
249		};
250
251		serial@e0000000 {
252			compatible = "xlnx,xuartps\0cdns,uart-r1p8";
253			status = "disabled";
254			clocks = < 0x01 0x17 0x01 0x28 >;
255			clock-names = "uart_clk\0pclk";
256			reg = < 0xe0000000 0x1000 >;
257			interrupts = < 0x00 0x1b 0x04 >;
258		};
259
260		serial@e0001000 {
261			compatible = "xlnx,xuartps\0cdns,uart-r1p8";
262			status = "okay";
263			clocks = < 0x01 0x18 0x01 0x29 >;
264			clock-names = "uart_clk\0pclk";
265			reg = < 0xe0001000 0x1000 >;
266			interrupts = < 0x00 0x32 0x04 >;
267			pinctrl-names = "default";
268			pinctrl-0 = < 0x07 >;
269		};
270
271		spi@e0006000 {
272			compatible = "xlnx,zynq-spi-r1p6";
273			reg = < 0xe0006000 0x1000 >;
274			status = "disabled";
275			interrupt-parent = < 0x04 >;
276			interrupts = < 0x00 0x1a 0x04 >;
277			clocks = < 0x01 0x19 0x01 0x22 >;
278			clock-names = "ref_clk\0pclk";
279			#address-cells = < 0x01 >;
280			#size-cells = < 0x00 >;
281		};
282
283		spi@e0007000 {
284			compatible = "xlnx,zynq-spi-r1p6";
285			reg = < 0xe0007000 0x1000 >;
286			status = "disabled";
287			interrupt-parent = < 0x04 >;
288			interrupts = < 0x00 0x31 0x04 >;
289			clocks = < 0x01 0x1a 0x01 0x23 >;
290			clock-names = "ref_clk\0pclk";
291			#address-cells = < 0x01 >;
292			#size-cells = < 0x00 >;
293		};
294
295		ethernet@e000b000 {
296			compatible = "cdns,zynq-gem\0cdns,gem";
297			reg = < 0xe000b000 0x1000 >;
298			status = "okay";
299			interrupts = < 0x00 0x16 0x04 >;
300			clocks = < 0x01 0x1e 0x01 0x1e 0x01 0x0d >;
301			clock-names = "pclk\0hclk\0tx_clk";
302			#address-cells = < 0x01 >;
303			#size-cells = < 0x00 >;
304			phy-mode = "rgmii-id";
305			phy-handle = < 0x08 >;
306			pinctrl-names = "default";
307			pinctrl-0 = < 0x09 >;
308
309			ethernet-phy@7 {
310				reg = < 0x07 >;
311				device_type = "ethernet-phy";
312				phandle = < 0x08 >;
313			};
314		};
315
316		ethernet@e000c000 {
317			compatible = "cdns,zynq-gem\0cdns,gem";
318			reg = < 0xe000c000 0x1000 >;
319			status = "disabled";
320			interrupts = < 0x00 0x2d 0x04 >;
321			clocks = < 0x01 0x1f 0x01 0x1f 0x01 0x0e >;
322			clock-names = "pclk\0hclk\0tx_clk";
323			#address-cells = < 0x01 >;
324			#size-cells = < 0x00 >;
325		};
326
327		sdhci@e0100000 {
328			compatible = "arasan,sdhci-8.9a";
329			status = "okay";
330			clock-names = "clk_xin\0clk_ahb";
331			clocks = < 0x01 0x15 0x01 0x20 >;
332			interrupt-parent = < 0x04 >;
333			interrupts = < 0x00 0x18 0x04 >;
334			reg = < 0xe0100000 0x1000 >;
335			pinctrl-names = "default";
336			pinctrl-0 = < 0x0a >;
337		};
338
339		sdhci@e0101000 {
340			compatible = "arasan,sdhci-8.9a";
341			status = "disabled";
342			clock-names = "clk_xin\0clk_ahb";
343			clocks = < 0x01 0x16 0x01 0x21 >;
344			interrupt-parent = < 0x04 >;
345			interrupts = < 0x00 0x2f 0x04 >;
346			reg = < 0xe0101000 0x1000 >;
347		};
348
349		slcr@f8000000 {
350			#address-cells = < 0x01 >;
351			#size-cells = < 0x01 >;
352			compatible = "xlnx,zynq-slcr\0syscon\0simple-mfd";
353			reg = < 0xf8000000 0x1000 >;
354			ranges;
355			phandle = < 0x0b >;
356
357			clkc@100 {
358				#clock-cells = < 0x01 >;
359				compatible = "xlnx,ps7-clkc";
360				fclk-enable = < 0x00 >;
361				clock-output-names = "armpll\0ddrpll\0iopll\0cpu_6or4x\0cpu_3or2x\0cpu_2x\0cpu_1x\0ddr2x\0ddr3x\0dci\0lqspi\0smc\0pcap\0gem0\0gem1\0fclk0\0fclk1\0fclk2\0fclk3\0can0\0can1\0sdio0\0sdio1\0uart0\0uart1\0spi0\0spi1\0dma\0usb0_aper\0usb1_aper\0gem0_aper\0gem1_aper\0sdio0_aper\0sdio1_aper\0spi0_aper\0spi1_aper\0can0_aper\0can1_aper\0i2c0_aper\0i2c1_aper\0uart0_aper\0uart1_aper\0gpio_aper\0lqspi_aper\0smc_aper\0swdt\0dbg_trc\0dbg_apb";
362				reg = < 0x100 0x100 >;
363				ps-clk-frequency = < 0x1fca055 >;
364				phandle = < 0x01 >;
365			};
366
367			rstc@200 {
368				compatible = "xlnx,zynq-reset";
369				reg = < 0x200 0x48 >;
370				#reset-cells = < 0x01 >;
371				syscon = < 0x0b >;
372			};
373
374			pinctrl@700 {
375				compatible = "xlnx,pinctrl-zynq";
376				reg = < 0x700 0x200 >;
377				syscon = < 0x0b >;
378
379				gem0-default {
380					phandle = < 0x09 >;
381
382					mux {
383						function = "ethernet0";
384						groups = "ethernet0_0_grp";
385					};
386
387					conf {
388						groups = "ethernet0_0_grp";
389						slew-rate = < 0x00 >;
390						io-standard = < 0x04 >;
391					};
392
393					conf-rx {
394						pins = "MIO22\0MIO23\0MIO24\0MIO25\0MIO26\0MIO27";
395						bias-high-impedance;
396						low-power-disable;
397					};
398
399					conf-tx {
400						pins = "MIO16\0MIO17\0MIO18\0MIO19\0MIO20\0MIO21";
401						low-power-enable;
402						bias-disable;
403					};
404
405					mux-mdio {
406						function = "mdio0";
407						groups = "mdio0_0_grp";
408					};
409
410					conf-mdio {
411						groups = "mdio0_0_grp";
412						slew-rate = < 0x00 >;
413						io-standard = < 0x01 >;
414						bias-disable;
415					};
416				};
417
418				gpio0-default {
419					phandle = < 0x05 >;
420
421					mux {
422						function = "gpio0";
423						groups = "gpio0_7_grp\0gpio0_46_grp\0gpio0_47_grp";
424					};
425
426					conf {
427						groups = "gpio0_7_grp\0gpio0_46_grp\0gpio0_47_grp";
428						slew-rate = < 0x00 >;
429						io-standard = < 0x01 >;
430					};
431
432					conf-pull-up {
433						pins = "MIO46\0MIO47";
434						bias-pull-up;
435					};
436
437					conf-pull-none {
438						pins = "MIO7";
439						bias-disable;
440					};
441				};
442
443				i2c0-default {
444					phandle = < 0x06 >;
445
446					mux {
447						groups = "i2c0_10_grp";
448						function = "i2c0";
449					};
450
451					conf {
452						groups = "i2c0_10_grp";
453						bias-pull-up;
454						slew-rate = < 0x00 >;
455						io-standard = < 0x01 >;
456					};
457				};
458
459				sdhci0-default {
460					phandle = < 0x0a >;
461
462					mux {
463						groups = "sdio0_2_grp";
464						function = "sdio0";
465					};
466
467					conf {
468						groups = "sdio0_2_grp";
469						slew-rate = < 0x00 >;
470						io-standard = < 0x01 >;
471						bias-disable;
472					};
473
474					mux-cd {
475						groups = "gpio0_14_grp";
476						function = "sdio0_cd";
477					};
478
479					conf-cd {
480						groups = "gpio0_14_grp";
481						bias-high-impedance;
482						bias-pull-up;
483						slew-rate = < 0x00 >;
484						io-standard = < 0x01 >;
485					};
486
487					mux-wp {
488						groups = "gpio0_15_grp";
489						function = "sdio0_wp";
490					};
491
492					conf-wp {
493						groups = "gpio0_15_grp";
494						bias-high-impedance;
495						bias-pull-up;
496						slew-rate = < 0x00 >;
497						io-standard = < 0x01 >;
498					};
499				};
500
501				uart1-default {
502					phandle = < 0x07 >;
503
504					mux {
505						groups = "uart1_10_grp";
506						function = "uart1";
507					};
508
509					conf {
510						groups = "uart1_10_grp";
511						slew-rate = < 0x00 >;
512						io-standard = < 0x01 >;
513					};
514
515					conf-rx {
516						pins = "MIO49";
517						bias-high-impedance;
518					};
519
520					conf-tx {
521						pins = "MIO48";
522						bias-disable;
523					};
524				};
525
526				usb0-default {
527					phandle = < 0x0d >;
528
529					mux {
530						groups = "usb0_0_grp";
531						function = "usb0";
532					};
533
534					conf {
535						groups = "usb0_0_grp";
536						slew-rate = < 0x00 >;
537						io-standard = < 0x01 >;
538					};
539
540					conf-rx {
541						pins = "MIO29\0MIO31\0MIO36";
542						bias-high-impedance;
543					};
544
545					conf-tx {
546						pins = "MIO28\0MIO30\0MIO32\0MIO33\0MIO34\0MIO35\0MIO37\0MIO38\0MIO39";
547						bias-disable;
548					};
549				};
550			};
551		};
552
553		dmac@f8003000 {
554			compatible = "arm,pl330\0arm,primecell";
555			reg = < 0xf8003000 0x1000 >;
556			interrupt-parent = < 0x04 >;
557			interrupt-names = "abort\0dma0\0dma1\0dma2\0dma3\0dma4\0dma5\0dma6\0dma7";
558			interrupts = < 0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04 >;
559			#dma-cells = < 0x01 >;
560			#dma-channels = < 0x08 >;
561			#dma-requests = < 0x04 >;
562			clocks = < 0x01 0x1b >;
563			clock-names = "apb_pclk";
564		};
565
566		devcfg@f8007000 {
567			compatible = "xlnx,zynq-devcfg-1.0";
568			reg = < 0xf8007000 0x100 >;
569			interrupt-parent = < 0x04 >;
570			interrupts = < 0x00 0x08 0x04 >;
571			clocks = < 0x01 0x0c >;
572			clock-names = "ref_clk";
573			syscon = < 0x0b >;
574			phandle = < 0x03 >;
575		};
576
577		timer@f8f00200 {
578			compatible = "arm,cortex-a9-global-timer";
579			reg = < 0xf8f00200 0x20 >;
580			interrupts = < 0x01 0x0b 0x301 >;
581			interrupt-parent = < 0x04 >;
582			clocks = < 0x01 0x04 >;
583		};
584
585		timer@f8001000 {
586			interrupt-parent = < 0x04 >;
587			interrupts = < 0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04 >;
588			compatible = "cdns,ttc";
589			clocks = < 0x01 0x06 >;
590			reg = < 0xf8001000 0x1000 >;
591		};
592
593		timer@f8002000 {
594			interrupt-parent = < 0x04 >;
595			interrupts = < 0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04 >;
596			compatible = "cdns,ttc";
597			clocks = < 0x01 0x06 >;
598			reg = < 0xf8002000 0x1000 >;
599		};
600
601		timer@f8f00600 {
602			interrupt-parent = < 0x04 >;
603			interrupts = < 0x01 0x0d 0x301 >;
604			compatible = "arm,cortex-a9-twd-timer";
605			reg = < 0xf8f00600 0x20 >;
606			clocks = < 0x01 0x04 >;
607		};
608
609		usb@e0002000 {
610			compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2";
611			status = "okay";
612			clocks = < 0x01 0x1c >;
613			interrupt-parent = < 0x04 >;
614			interrupts = < 0x00 0x15 0x04 >;
615			reg = < 0xe0002000 0x1000 >;
616			phy_type = "ulpi";
617			dr_mode = "host";
618			usb-phy = < 0x0c >;
619			pinctrl-names = "default";
620			pinctrl-0 = < 0x0d >;
621		};
622
623		usb@e0003000 {
624			compatible = "xlnx,zynq-usb-2.20a\0chipidea,usb2";
625			status = "disabled";
626			clocks = < 0x01 0x1d >;
627			interrupt-parent = < 0x04 >;
628			interrupts = < 0x00 0x2c 0x04 >;
629			reg = < 0xe0003000 0x1000 >;
630			phy_type = "ulpi";
631		};
632
633		watchdog@f8005000 {
634			clocks = < 0x01 0x2d >;
635			compatible = "cdns,wdt-r1p2";
636			interrupt-parent = < 0x04 >;
637			interrupts = < 0x00 0x09 0x01 >;
638			reg = < 0xf8005000 0x1000 >;
639			timeout-sec = < 0x0a >;
640		};
641	};
642
643	aliases {
644		ethernet0 = "/amba/ethernet@e000b000";
645		i2c0 = "/amba/i2c@e0004000";
646		serial0 = "/amba/serial@e0001000";
647		mmc0 = "/amba/sdhci@e0100000";
648	};
649
650	memory@0 {
651		device_type = "memory";
652		reg = < 0x00 0x40000000 >;
653	};
654
655	chosen {
656		bootargs = [ 00 ];
657		stdout-path = "serial0:115200n8";
658	};
659
660	phy0 {
661		compatible = "usb-nop-xceiv";
662		#phy-cells = < 0x00 >;
663		phandle = < 0x0c >;
664	};
665};
666