1/*
2 * Copyright Linux Kernel Team
3 *
4 * SPDX-License-Identifier: GPL-2.0-only
5 *
6 * This file is derived from an intermediate build stage of the
7 * Linux kernel. The licenses of all input files to this process
8 * are compatible with GPL-2.0-only.
9 */
10
11/dts-v1/;
12
13/ {
14	#address-cells = < 0x01 >;
15	#size-cells = < 0x01 >;
16	model = "Freescale i.MX6 Quad SABRE Lite Board";
17	compatible = "fsl,imx6q-sabrelite\0fsl,imx6q";
18
19	chosen {
20		stdout-path = "/soc/aips-bus@2100000/serial@21e8000";
21	};
22
23	memory {
24		device_type = "memory";
25	};
26
27	aliases {
28		ethernet0 = "/soc/aips-bus@2100000/ethernet@2188000";
29		can0 = "/soc/aips-bus@2000000/flexcan@2090000";
30		can1 = "/soc/aips-bus@2000000/flexcan@2094000";
31		gpio0 = "/soc/aips-bus@2000000/gpio@209c000";
32		gpio1 = "/soc/aips-bus@2000000/gpio@20a0000";
33		gpio2 = "/soc/aips-bus@2000000/gpio@20a4000";
34		gpio3 = "/soc/aips-bus@2000000/gpio@20a8000";
35		gpio4 = "/soc/aips-bus@2000000/gpio@20ac000";
36		gpio5 = "/soc/aips-bus@2000000/gpio@20b0000";
37		gpio6 = "/soc/aips-bus@2000000/gpio@20b4000";
38		i2c0 = "/soc/aips-bus@2100000/i2c@21a0000";
39		i2c1 = "/soc/aips-bus@2100000/i2c@21a4000";
40		i2c2 = "/soc/aips-bus@2100000/i2c@21a8000";
41		ipu0 = "/soc/ipu@2400000";
42		mmc0 = "/soc/aips-bus@2100000/usdhc@2190000";
43		mmc1 = "/soc/aips-bus@2100000/usdhc@2194000";
44		mmc2 = "/soc/aips-bus@2100000/usdhc@2198000";
45		mmc3 = "/soc/aips-bus@2100000/usdhc@219c000";
46		serial0 = "/soc/aips-bus@2000000/spba-bus@2000000/serial@2020000";
47		serial1 = "/soc/aips-bus@2100000/serial@21e8000";
48		serial2 = "/soc/aips-bus@2100000/serial@21ec000";
49		serial3 = "/soc/aips-bus@2100000/serial@21f0000";
50		serial4 = "/soc/aips-bus@2100000/serial@21f4000";
51		spi0 = "/soc/aips-bus@2000000/spba-bus@2000000/spi@2008000";
52		spi1 = "/soc/aips-bus@2000000/spba-bus@2000000/spi@200c000";
53		spi2 = "/soc/aips-bus@2000000/spba-bus@2000000/spi@2010000";
54		spi3 = "/soc/aips-bus@2000000/spba-bus@2000000/spi@2014000";
55		usbphy0 = "/soc/aips-bus@2000000/usbphy@20c9000";
56		usbphy1 = "/soc/aips-bus@2000000/usbphy@20ca000";
57		ipu1 = "/soc/ipu@2800000";
58		spi4 = "/soc/aips-bus@2000000/spba-bus@2000000/spi@2018000";
59	};
60
61	clocks {
62
63		ckil {
64			compatible = "fsl,imx-ckil\0fixed-clock";
65			#clock-cells = < 0x00 >;
66			clock-frequency = < 0x8000 >;
67		};
68
69		ckih1 {
70			compatible = "fsl,imx-ckih1\0fixed-clock";
71			#clock-cells = < 0x00 >;
72			clock-frequency = < 0x00 >;
73		};
74
75		osc {
76			compatible = "fsl,imx-osc\0fixed-clock";
77			#clock-cells = < 0x00 >;
78			clock-frequency = < 0x16e3600 >;
79		};
80	};
81
82	tempmon {
83		compatible = "fsl,imx6q-tempmon";
84		interrupt-parent = < 0x01 >;
85		interrupts = < 0x00 0x31 0x04 >;
86		fsl,tempmon = < 0x02 >;
87		fsl,tempmon-data = < 0x03 >;
88		clocks = < 0x04 0xac >;
89	};
90
91	ldb {
92		#address-cells = < 0x01 >;
93		#size-cells = < 0x00 >;
94		compatible = "fsl,imx6q-ldb\0fsl,imx53-ldb";
95		gpr = < 0x05 >;
96		status = "okay";
97		clocks = < 0x04 0x21 0x04 0x22 0x04 0x27 0x04 0x28 0x04 0x29 0x04 0x2a 0x04 0x87 0x04 0x88 >;
98		clock-names = "di0_pll\0di1_pll\0di0_sel\0di1_sel\0di2_sel\0di3_sel\0di0\0di1";
99
100		lvds-channel@0 {
101			#address-cells = < 0x01 >;
102			#size-cells = < 0x00 >;
103			reg = < 0x00 >;
104			status = "okay";
105
106			port@0 {
107				reg = < 0x00 >;
108
109				endpoint {
110					remote-endpoint = < 0x06 >;
111					phandle = < 0x57 >;
112				};
113			};
114
115			port@1 {
116				reg = < 0x01 >;
117
118				endpoint {
119					remote-endpoint = < 0x07 >;
120					phandle = < 0x5b >;
121				};
122			};
123
124			port@2 {
125				reg = < 0x02 >;
126
127				endpoint {
128					remote-endpoint = < 0x08 >;
129					phandle = < 0x61 >;
130				};
131			};
132
133			port@3 {
134				reg = < 0x03 >;
135
136				endpoint {
137					remote-endpoint = < 0x09 >;
138					phandle = < 0x65 >;
139				};
140			};
141
142			port@4 {
143				reg = < 0x04 >;
144
145				endpoint {
146					remote-endpoint = < 0x0a >;
147					phandle = < 0x81 >;
148				};
149			};
150		};
151
152		lvds-channel@1 {
153			#address-cells = < 0x01 >;
154			#size-cells = < 0x00 >;
155			reg = < 0x01 >;
156			status = "disabled";
157
158			port@0 {
159				reg = < 0x00 >;
160
161				endpoint {
162					remote-endpoint = < 0x0b >;
163					phandle = < 0x58 >;
164				};
165			};
166
167			port@1 {
168				reg = < 0x01 >;
169
170				endpoint {
171					remote-endpoint = < 0x0c >;
172					phandle = < 0x5c >;
173				};
174			};
175
176			port@2 {
177				reg = < 0x02 >;
178
179				endpoint {
180					remote-endpoint = < 0x0d >;
181					phandle = < 0x62 >;
182				};
183			};
184
185			port@3 {
186				reg = < 0x03 >;
187
188				endpoint {
189					remote-endpoint = < 0x0e >;
190					phandle = < 0x66 >;
191				};
192			};
193		};
194	};
195
196	pmu {
197		compatible = "arm,cortex-a9-pmu";
198		interrupt-parent = < 0x01 >;
199		interrupts = < 0x00 0x5e 0x04 >;
200	};
201
202	soc {
203		#address-cells = < 0x01 >;
204		#size-cells = < 0x01 >;
205		compatible = "simple-bus";
206		interrupt-parent = < 0x01 >;
207		ranges;
208
209		dma-apbh@110000 {
210			compatible = "fsl,imx6q-dma-apbh\0fsl,imx28-dma-apbh";
211			reg = < 0x110000 0x2000 >;
212			interrupts = < 0x00 0x0d 0x04 0x00 0x0d 0x04 0x00 0x0d 0x04 0x00 0x0d 0x04 >;
213			interrupt-names = "gpmi0\0gpmi1\0gpmi2\0gpmi3";
214			#dma-cells = < 0x01 >;
215			dma-channels = < 0x04 >;
216			clocks = < 0x04 0x6a >;
217			phandle = < 0x0f >;
218		};
219
220		gpmi-nand@112000 {
221			compatible = "fsl,imx6q-gpmi-nand";
222			#address-cells = < 0x01 >;
223			#size-cells = < 0x01 >;
224			reg = < 0x112000 0x2000 0x114000 0x2000 >;
225			reg-names = "gpmi-nand\0bch";
226			interrupts = < 0x00 0x0f 0x04 >;
227			interrupt-names = "bch";
228			clocks = < 0x04 0x98 0x04 0x99 0x04 0x97 0x04 0x96 0x04 0x95 >;
229			clock-names = "gpmi_io\0gpmi_apb\0gpmi_bch\0gpmi_bch_apb\0per1_bch";
230			dmas = < 0x0f 0x00 >;
231			dma-names = "rx-tx";
232			status = "disabled";
233		};
234
235		hdmi@120000 {
236			#address-cells = < 0x01 >;
237			#size-cells = < 0x00 >;
238			reg = < 0x120000 0x9000 >;
239			interrupts = < 0x00 0x73 0x04 >;
240			gpr = < 0x05 >;
241			clocks = < 0x04 0x7b 0x04 0x7c >;
242			clock-names = "iahb\0isfr";
243			status = "okay";
244			compatible = "fsl,imx6q-hdmi";
245			ddc-i2c-bus = < 0x10 >;
246
247			port@0 {
248				reg = < 0x00 >;
249
250				endpoint {
251					remote-endpoint = < 0x11 >;
252					phandle = < 0x55 >;
253				};
254			};
255
256			port@1 {
257				reg = < 0x01 >;
258
259				endpoint {
260					remote-endpoint = < 0x12 >;
261					phandle = < 0x59 >;
262				};
263			};
264
265			port@2 {
266				reg = < 0x02 >;
267
268				endpoint {
269					remote-endpoint = < 0x13 >;
270					phandle = < 0x5f >;
271				};
272			};
273
274			port@3 {
275				reg = < 0x03 >;
276
277				endpoint {
278					remote-endpoint = < 0x14 >;
279					phandle = < 0x63 >;
280				};
281			};
282		};
283
284		gpu@130000 {
285			compatible = "vivante,gc";
286			reg = < 0x130000 0x4000 >;
287			interrupts = < 0x00 0x09 0x04 >;
288			clocks = < 0x04 0x1b 0x04 0x7a 0x04 0x4a >;
289			clock-names = "bus\0core\0shader";
290			power-domains = < 0x15 >;
291		};
292
293		gpu@134000 {
294			compatible = "vivante,gc";
295			reg = < 0x134000 0x4000 >;
296			interrupts = < 0x00 0x0a 0x04 >;
297			clocks = < 0x04 0x1a 0x04 0x79 >;
298			clock-names = "bus\0core";
299			power-domains = < 0x15 >;
300		};
301
302		timer@a00600 {
303			compatible = "arm,cortex-a9-twd-timer";
304			reg = < 0xa00600 0x20 >;
305			interrupts = < 0x01 0x0d 0xf01 >;
306			interrupt-parent = < 0x16 >;
307			clocks = < 0x04 0x0f >;
308		};
309
310		interrupt-controller@a01000 {
311			compatible = "arm,cortex-a9-gic";
312			#interrupt-cells = < 0x03 >;
313			interrupt-controller;
314			reg = < 0xa01000 0x1000 0xa00100 0x100 >;
315			interrupt-parent = < 0x16 >;
316			phandle = < 0x16 >;
317		};
318
319		l2-cache@a02000 {
320			compatible = "arm,pl310-cache";
321			reg = < 0xa02000 0x1000 >;
322			interrupts = < 0x00 0x5c 0x04 >;
323			cache-unified;
324			cache-level = < 0x02 >;
325			arm,tag-latency = < 0x04 0x02 0x03 >;
326			arm,data-latency = < 0x04 0x02 0x03 >;
327			arm,shared-override;
328			phandle = < 0x67 >;
329		};
330
331		pcie@1ffc000 {
332			compatible = "fsl,imx6q-pcie\0snps,dw-pcie";
333			reg = < 0x1ffc000 0x4000 0x1f00000 0x80000 >;
334			reg-names = "dbi\0config";
335			#address-cells = < 0x03 >;
336			#size-cells = < 0x02 >;
337			device_type = "pci";
338			bus-range = < 0x00 0xff >;
339			ranges = < 0x81000000 0x00 0x00 0x1f80000 0x00 0x10000 0x82000000 0x00 0x1000000 0x1000000 0x00 0xf00000 >;
340			num-lanes = < 0x01 >;
341			interrupts = < 0x00 0x78 0x04 >;
342			interrupt-names = "msi";
343			#interrupt-cells = < 0x01 >;
344			interrupt-map-mask = < 0x00 0x00 0x00 0x07 >;
345			interrupt-map = < 0x00 0x00 0x00 0x01 0x01 0x00 0x7b 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x7a 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x79 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x78 0x04 >;
346			clocks = < 0x04 0x90 0x04 0xce 0x04 0xbd >;
347			clock-names = "pcie\0pcie_bus\0pcie_phy";
348			status = "okay";
349		};
350
351		aips-bus@2000000 {
352			compatible = "fsl,aips-bus\0simple-bus";
353			#address-cells = < 0x01 >;
354			#size-cells = < 0x01 >;
355			reg = < 0x2000000 0x100000 >;
356			ranges;
357
358			spba-bus@2000000 {
359				compatible = "fsl,spba-bus\0simple-bus";
360				#address-cells = < 0x01 >;
361				#size-cells = < 0x01 >;
362				reg = < 0x2000000 0x40000 >;
363				ranges;
364
365				spdif@2004000 {
366					compatible = "fsl,imx35-spdif";
367					reg = < 0x2004000 0x4000 >;
368					interrupts = < 0x00 0x34 0x04 >;
369					dmas = < 0x17 0x0e 0x12 0x00 0x17 0x0f 0x12 0x00 >;
370					dma-names = "rx\0tx";
371					clocks = < 0x04 0xf4 0x04 0x03 0x04 0xc5 0x04 0x6b 0x04 0x00 0x04 0x76 0x04 0x3e 0x04 0x00 0x04 0x00 0x04 0x9c >;
372					clock-names = "core\0rxtx0\0rxtx1\0rxtx2\0rxtx3\0rxtx4\0rxtx5\0rxtx6\0rxtx7\0spba";
373					status = "disabled";
374				};
375
376				spi@2008000 {
377					#address-cells = < 0x01 >;
378					#size-cells = < 0x00 >;
379					compatible = "fsl,imx6q-ecspi\0fsl,imx51-ecspi";
380					reg = < 0x2008000 0x4000 >;
381					interrupts = < 0x00 0x1f 0x04 >;
382					clocks = < 0x04 0x70 0x04 0x70 >;
383					clock-names = "ipg\0per";
384					dmas = < 0x17 0x03 0x08 0x01 0x17 0x04 0x08 0x02 >;
385					dma-names = "rx\0tx";
386					status = "okay";
387					cs-gpios = < 0x18 0x13 0x00 >;
388					pinctrl-names = "default";
389					pinctrl-0 = < 0x19 >;
390
391					m25p80@0 {
392						compatible = "sst,sst25vf016b\0jedec,spi-nor";
393						spi-max-frequency = < 0x1312d00 >;
394						reg = < 0x00 >;
395					};
396				};
397
398				spi@200c000 {
399					#address-cells = < 0x01 >;
400					#size-cells = < 0x00 >;
401					compatible = "fsl,imx6q-ecspi\0fsl,imx51-ecspi";
402					reg = < 0x200c000 0x4000 >;
403					interrupts = < 0x00 0x20 0x04 >;
404					clocks = < 0x04 0x71 0x04 0x71 >;
405					clock-names = "ipg\0per";
406					dmas = < 0x17 0x05 0x08 0x01 0x17 0x06 0x08 0x02 >;
407					dma-names = "rx\0tx";
408					status = "disabled";
409				};
410
411				spi@2010000 {
412					#address-cells = < 0x01 >;
413					#size-cells = < 0x00 >;
414					compatible = "fsl,imx6q-ecspi\0fsl,imx51-ecspi";
415					reg = < 0x2010000 0x4000 >;
416					interrupts = < 0x00 0x21 0x04 >;
417					clocks = < 0x04 0x72 0x04 0x72 >;
418					clock-names = "ipg\0per";
419					dmas = < 0x17 0x07 0x08 0x01 0x17 0x08 0x08 0x02 >;
420					dma-names = "rx\0tx";
421					status = "disabled";
422				};
423
424				spi@2014000 {
425					#address-cells = < 0x01 >;
426					#size-cells = < 0x00 >;
427					compatible = "fsl,imx6q-ecspi\0fsl,imx51-ecspi";
428					reg = < 0x2014000 0x4000 >;
429					interrupts = < 0x00 0x22 0x04 >;
430					clocks = < 0x04 0x73 0x04 0x73 >;
431					clock-names = "ipg\0per";
432					dmas = < 0x17 0x09 0x08 0x01 0x17 0x0a 0x08 0x02 >;
433					dma-names = "rx\0tx";
434					status = "disabled";
435				};
436
437				serial@2020000 {
438					compatible = "fsl,imx6q-uart\0fsl,imx21-uart";
439					reg = < 0x2020000 0x4000 >;
440					interrupts = < 0x00 0x1a 0x04 >;
441					clocks = < 0x04 0xa0 0x04 0xa1 >;
442					clock-names = "ipg\0per";
443					dmas = < 0x17 0x19 0x04 0x00 0x17 0x1a 0x04 0x00 >;
444					dma-names = "rx\0tx";
445					status = "okay";
446					pinctrl-names = "default";
447					pinctrl-0 = < 0x1a >;
448				};
449
450				esai@2024000 {
451					#sound-dai-cells = < 0x00 >;
452					compatible = "fsl,imx35-esai";
453					reg = < 0x2024000 0x4000 >;
454					interrupts = < 0x00 0x33 0x04 >;
455					clocks = < 0x04 0xd0 0x04 0xd1 0x04 0x76 0x04 0xd0 0x04 0x9c >;
456					clock-names = "core\0mem\0extal\0fsys\0spba";
457					dmas = < 0x17 0x17 0x15 0x00 0x17 0x18 0x15 0x00 >;
458					dma-names = "rx\0tx";
459					status = "disabled";
460				};
461
462				ssi@2028000 {
463					#sound-dai-cells = < 0x00 >;
464					compatible = "fsl,imx6q-ssi\0fsl,imx51-ssi";
465					reg = < 0x2028000 0x4000 >;
466					interrupts = < 0x00 0x2e 0x04 >;
467					clocks = < 0x04 0xb2 0x04 0x9d >;
468					clock-names = "ipg\0baud";
469					dmas = < 0x17 0x25 0x01 0x00 0x17 0x26 0x01 0x00 >;
470					dma-names = "rx\0tx";
471					fsl,fifo-depth = < 0x0f >;
472					status = "okay";
473					phandle = < 0x77 >;
474				};
475
476				ssi@202c000 {
477					#sound-dai-cells = < 0x00 >;
478					compatible = "fsl,imx6q-ssi\0fsl,imx51-ssi";
479					reg = < 0x202c000 0x4000 >;
480					interrupts = < 0x00 0x2f 0x04 >;
481					clocks = < 0x04 0xb3 0x04 0x9e >;
482					clock-names = "ipg\0baud";
483					dmas = < 0x17 0x29 0x01 0x00 0x17 0x2a 0x01 0x00 >;
484					dma-names = "rx\0tx";
485					fsl,fifo-depth = < 0x0f >;
486					status = "disabled";
487				};
488
489				ssi@2030000 {
490					#sound-dai-cells = < 0x00 >;
491					compatible = "fsl,imx6q-ssi\0fsl,imx51-ssi";
492					reg = < 0x2030000 0x4000 >;
493					interrupts = < 0x00 0x30 0x04 >;
494					clocks = < 0x04 0xb4 0x04 0x9f >;
495					clock-names = "ipg\0baud";
496					dmas = < 0x17 0x2d 0x01 0x00 0x17 0x2e 0x01 0x00 >;
497					dma-names = "rx\0tx";
498					fsl,fifo-depth = < 0x0f >;
499					status = "disabled";
500				};
501
502				asrc@2034000 {
503					compatible = "fsl,imx53-asrc";
504					reg = < 0x2034000 0x4000 >;
505					interrupts = < 0x00 0x32 0x04 >;
506					clocks = < 0x04 0xd2 0x04 0xd3 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0x6b 0x04 0x00 0x04 0x00 0x04 0x9c >;
507					clock-names = "mem\0ipg\0asrck_0\0asrck_1\0asrck_2\0asrck_3\0asrck_4\0asrck_5\0asrck_6\0asrck_7\0asrck_8\0asrck_9\0asrck_a\0asrck_b\0asrck_c\0asrck_d\0asrck_e\0asrck_f\0spba";
508					dmas = < 0x17 0x11 0x17 0x01 0x17 0x12 0x17 0x01 0x17 0x13 0x17 0x01 0x17 0x14 0x17 0x01 0x17 0x15 0x17 0x01 0x17 0x16 0x17 0x01 >;
509					dma-names = "rxa\0rxb\0rxc\0txa\0txb\0txc";
510					fsl,asrc-rate = < 0xbb80 >;
511					fsl,asrc-width = < 0x10 >;
512					status = "okay";
513				};
514
515				spba@203c000 {
516					reg = < 0x203c000 0x4000 >;
517				};
518
519				spi@2018000 {
520					#address-cells = < 0x01 >;
521					#size-cells = < 0x00 >;
522					compatible = "fsl,imx6q-ecspi\0fsl,imx51-ecspi";
523					reg = < 0x2018000 0x4000 >;
524					interrupts = < 0x00 0x23 0x04 >;
525					clocks = < 0x04 0x74 0x04 0x74 >;
526					clock-names = "ipg\0per";
527					dmas = < 0x17 0x0b 0x08 0x01 0x17 0x0c 0x08 0x02 >;
528					dma-names = "rx\0tx";
529					status = "disabled";
530				};
531			};
532
533			vpu@2040000 {
534				compatible = "fsl,imx6q-vpu\0cnm,coda960";
535				reg = < 0x2040000 0x3c000 >;
536				interrupts = < 0x00 0x0c 0x04 0x00 0x03 0x04 >;
537				interrupt-names = "bit\0jpeg";
538				clocks = < 0x04 0xa8 0x04 0x8c >;
539				clock-names = "per\0ahb";
540				power-domains = < 0x15 >;
541				resets = < 0x1b 0x01 >;
542				iram = < 0x1c >;
543			};
544
545			aipstz@207c000 {
546				reg = < 0x207c000 0x4000 >;
547			};
548
549			pwm@2080000 {
550				#pwm-cells = < 0x02 >;
551				compatible = "fsl,imx6q-pwm\0fsl,imx27-pwm";
552				reg = < 0x2080000 0x4000 >;
553				interrupts = < 0x00 0x53 0x04 >;
554				clocks = < 0x04 0x3e 0x04 0x91 >;
555				clock-names = "ipg\0per";
556				status = "okay";
557				pinctrl-names = "default";
558				pinctrl-0 = < 0x1d >;
559				phandle = < 0x79 >;
560			};
561
562			pwm@2084000 {
563				#pwm-cells = < 0x02 >;
564				compatible = "fsl,imx6q-pwm\0fsl,imx27-pwm";
565				reg = < 0x2084000 0x4000 >;
566				interrupts = < 0x00 0x54 0x04 >;
567				clocks = < 0x04 0x3e 0x04 0x92 >;
568				clock-names = "ipg\0per";
569				status = "disabled";
570			};
571
572			pwm@2088000 {
573				#pwm-cells = < 0x02 >;
574				compatible = "fsl,imx6q-pwm\0fsl,imx27-pwm";
575				reg = < 0x2088000 0x4000 >;
576				interrupts = < 0x00 0x55 0x04 >;
577				clocks = < 0x04 0x3e 0x04 0x93 >;
578				clock-names = "ipg\0per";
579				status = "okay";
580				pinctrl-names = "default";
581				pinctrl-0 = < 0x1e >;
582				phandle = < 0x74 >;
583			};
584
585			pwm@208c000 {
586				#pwm-cells = < 0x02 >;
587				compatible = "fsl,imx6q-pwm\0fsl,imx27-pwm";
588				reg = < 0x208c000 0x4000 >;
589				interrupts = < 0x00 0x56 0x04 >;
590				clocks = < 0x04 0x3e 0x04 0x94 >;
591				clock-names = "ipg\0per";
592				status = "okay";
593				pinctrl-names = "default";
594				pinctrl-0 = < 0x1f >;
595				phandle = < 0x7a >;
596			};
597
598			flexcan@2090000 {
599				compatible = "fsl,imx6q-flexcan";
600				reg = < 0x2090000 0x4000 >;
601				interrupts = < 0x00 0x6e 0x04 >;
602				clocks = < 0x04 0x6c 0x04 0x6d >;
603				clock-names = "ipg\0per";
604				status = "okay";
605				pinctrl-names = "default";
606				pinctrl-0 = < 0x20 >;
607				xceiver-supply = < 0x21 >;
608			};
609
610			flexcan@2094000 {
611				compatible = "fsl,imx6q-flexcan";
612				reg = < 0x2094000 0x4000 >;
613				interrupts = < 0x00 0x6f 0x04 >;
614				clocks = < 0x04 0x6e 0x04 0x6f >;
615				clock-names = "ipg\0per";
616				status = "disabled";
617			};
618
619			gpt@2098000 {
620				compatible = "fsl,imx6q-gpt\0fsl,imx31-gpt";
621				reg = < 0x2098000 0x4000 >;
622				interrupts = < 0x00 0x37 0x04 >;
623				clocks = < 0x04 0x77 0x04 0x78 0x04 0xed >;
624				clock-names = "ipg\0per\0osc_per";
625			};
626
627			gpio@209c000 {
628				compatible = "fsl,imx6q-gpio\0fsl,imx35-gpio";
629				reg = < 0x209c000 0x4000 >;
630				interrupts = < 0x00 0x42 0x04 0x00 0x43 0x04 >;
631				gpio-controller;
632				#gpio-cells = < 0x02 >;
633				interrupt-controller;
634				#interrupt-cells = < 0x02 >;
635				gpio-ranges = < 0x22 0x00 0x88 0x02 0x22 0x02 0x8d 0x01 0x22 0x03 0x8b 0x01 0x22 0x04 0x8e 0x02 0x22 0x06 0x8c 0x01 0x22 0x07 0x90 0x02 0x22 0x09 0x8a 0x01 0x22 0x0a 0xd5 0x03 0x22 0x0d 0x14 0x01 0x22 0x0e 0x13 0x01 0x22 0x0f 0x15 0x01 0x22 0x10 0xd0 0x01 0x22 0x11 0xcf 0x01 0x22 0x12 0xd2 0x03 0x22 0x15 0xd1 0x01 0x22 0x16 0x74 0x0a >;
636				phandle = < 0x43 >;
637			};
638
639			gpio@20a0000 {
640				compatible = "fsl,imx6q-gpio\0fsl,imx35-gpio";
641				reg = < 0x20a0000 0x4000 >;
642				interrupts = < 0x00 0x44 0x04 0x00 0x45 0x04 >;
643				gpio-controller;
644				#gpio-cells = < 0x02 >;
645				interrupt-controller;
646				#interrupt-cells = < 0x02 >;
647				gpio-ranges = < 0x22 0x00 0xbf 0x10 0x22 0x10 0x37 0x0e 0x22 0x1e 0x23 0x01 0x22 0x1f 0x2c 0x01 >;
648				phandle = < 0x37 >;
649			};
650
651			gpio@20a4000 {
652				compatible = "fsl,imx6q-gpio\0fsl,imx35-gpio";
653				reg = < 0x20a4000 0x4000 >;
654				interrupts = < 0x00 0x46 0x04 0x00 0x47 0x04 >;
655				gpio-controller;
656				#gpio-cells = < 0x02 >;
657				interrupt-controller;
658				#interrupt-cells = < 0x02 >;
659				gpio-ranges = < 0x22 0x00 0x45 0x10 0x22 0x10 0x24 0x08 0x22 0x18 0x2d 0x08 >;
660				phandle = < 0x18 >;
661			};
662
663			gpio@20a8000 {
664				compatible = "fsl,imx6q-gpio\0fsl,imx35-gpio";
665				reg = < 0x20a8000 0x4000 >;
666				interrupts = < 0x00 0x48 0x04 0x00 0x49 0x04 >;
667				gpio-controller;
668				#gpio-cells = < 0x02 >;
669				interrupt-controller;
670				#interrupt-cells = < 0x02 >;
671				gpio-ranges = < 0x22 0x05 0x95 0x01 0x22 0x06 0x7e 0x0a 0x22 0x10 0x57 0x10 >;
672				phandle = < 0x76 >;
673			};
674
675			gpio@20ac000 {
676				compatible = "fsl,imx6q-gpio\0fsl,imx35-gpio";
677				reg = < 0x20ac000 0x4000 >;
678				interrupts = < 0x00 0x4a 0x04 0x00 0x4b 0x04 >;
679				gpio-controller;
680				#gpio-cells = < 0x02 >;
681				interrupt-controller;
682				#interrupt-cells = < 0x02 >;
683				gpio-ranges = < 0x22 0x00 0x55 0x01 0x22 0x02 0x22 0x01 0x22 0x04 0x35 0x01 0x22 0x05 0x67 0x0d 0x22 0x12 0x96 0x0e >;
684			};
685
686			gpio@20b0000 {
687				compatible = "fsl,imx6q-gpio\0fsl,imx35-gpio";
688				reg = < 0x20b0000 0x4000 >;
689				interrupts = < 0x00 0x4c 0x04 0x00 0x4d 0x04 >;
690				gpio-controller;
691				#gpio-cells = < 0x02 >;
692				interrupt-controller;
693				#interrupt-cells = < 0x02 >;
694				gpio-ranges = < 0x22 0x00 0xa4 0x06 0x22 0x06 0x36 0x01 0x22 0x07 0xb5 0x05 0x22 0x0e 0xba 0x03 0x22 0x11 0xaa 0x02 0x22 0x13 0x16 0x0c 0x22 0x1f 0x56 0x01 >;
695				phandle = < 0x40 >;
696			};
697
698			gpio@20b4000 {
699				compatible = "fsl,imx6q-gpio\0fsl,imx35-gpio";
700				reg = < 0x20b4000 0x4000 >;
701				interrupts = < 0x00 0x4e 0x04 0x00 0x4f 0x04 >;
702				gpio-controller;
703				#gpio-cells = < 0x02 >;
704				interrupt-controller;
705				#interrupt-cells = < 0x02 >;
706				gpio-ranges = < 0x22 0x00 0xac 0x09 0x22 0x09 0xbd 0x02 0x22 0x0b 0x92 0x03 >;
707				phandle = < 0x34 >;
708			};
709
710			kpp@20b8000 {
711				compatible = "fsl,imx6q-kpp\0fsl,imx21-kpp";
712				reg = < 0x20b8000 0x4000 >;
713				interrupts = < 0x00 0x52 0x04 >;
714				clocks = < 0x04 0x3e >;
715				status = "disabled";
716			};
717
718			wdog@20bc000 {
719				compatible = "fsl,imx6q-wdt\0fsl,imx21-wdt";
720				reg = < 0x20bc000 0x4000 >;
721				interrupts = < 0x00 0x50 0x04 >;
722				clocks = < 0x04 0x00 >;
723			};
724
725			wdog@20c0000 {
726				compatible = "fsl,imx6q-wdt\0fsl,imx21-wdt";
727				reg = < 0x20c0000 0x4000 >;
728				interrupts = < 0x00 0x51 0x04 >;
729				clocks = < 0x04 0x00 >;
730				status = "disabled";
731			};
732
733			ccm@20c4000 {
734				compatible = "fsl,imx6q-ccm";
735				reg = < 0x20c4000 0x4000 >;
736				interrupts = < 0x00 0x57 0x04 0x00 0x58 0x04 >;
737				#clock-cells = < 0x01 >;
738				assigned-clocks = < 0x04 0x21 0x04 0x22 >;
739				assigned-clock-parents = < 0x04 0xac 0x04 0xac >;
740				phandle = < 0x04 >;
741			};
742
743			anatop@20c8000 {
744				compatible = "fsl,imx6q-anatop\0syscon\0simple-bus";
745				reg = < 0x20c8000 0x1000 >;
746				interrupts = < 0x00 0x31 0x04 0x00 0x36 0x04 0x00 0x7f 0x04 >;
747				phandle = < 0x02 >;
748
749				regulator-1p1 {
750					compatible = "fsl,anatop-regulator";
751					regulator-name = "vdd1p1";
752					regulator-min-microvolt = < 0xf4240 >;
753					regulator-max-microvolt = < 0x124f80 >;
754					regulator-always-on;
755					anatop-reg-offset = < 0x110 >;
756					anatop-vol-bit-shift = < 0x08 >;
757					anatop-vol-bit-width = < 0x05 >;
758					anatop-min-bit-val = < 0x04 >;
759					anatop-min-voltage = < 0xc3500 >;
760					anatop-max-voltage = < 0x14fb18 >;
761					anatop-enable-bit = < 0x00 >;
762				};
763
764				regulator-3p0 {
765					compatible = "fsl,anatop-regulator";
766					regulator-name = "vdd3p0";
767					regulator-min-microvolt = < 0x2ab980 >;
768					regulator-max-microvolt = < 0x3010b0 >;
769					regulator-always-on;
770					anatop-reg-offset = < 0x120 >;
771					anatop-vol-bit-shift = < 0x08 >;
772					anatop-vol-bit-width = < 0x05 >;
773					anatop-min-bit-val = < 0x00 >;
774					anatop-min-voltage = < 0x280de8 >;
775					anatop-max-voltage = < 0x33e140 >;
776					anatop-enable-bit = < 0x00 >;
777				};
778
779				regulator-2p5 {
780					compatible = "fsl,anatop-regulator";
781					regulator-name = "vdd2p5";
782					regulator-min-microvolt = < 0x225510 >;
783					regulator-max-microvolt = < 0x29f630 >;
784					regulator-always-on;
785					anatop-reg-offset = < 0x130 >;
786					anatop-vol-bit-shift = < 0x08 >;
787					anatop-vol-bit-width = < 0x05 >;
788					anatop-min-bit-val = < 0x00 >;
789					anatop-min-voltage = < 0x200b20 >;
790					anatop-max-voltage = < 0x2bde78 >;
791					anatop-enable-bit = < 0x00 >;
792				};
793
794				regulator-vddcore {
795					compatible = "fsl,anatop-regulator";
796					regulator-name = "vddarm";
797					regulator-min-microvolt = < 0xb1008 >;
798					regulator-max-microvolt = < 0x162010 >;
799					regulator-always-on;
800					anatop-reg-offset = < 0x140 >;
801					anatop-vol-bit-shift = < 0x00 >;
802					anatop-vol-bit-width = < 0x05 >;
803					anatop-delay-reg-offset = < 0x170 >;
804					anatop-delay-bit-shift = < 0x18 >;
805					anatop-delay-bit-width = < 0x02 >;
806					anatop-min-bit-val = < 0x01 >;
807					anatop-min-voltage = < 0xb1008 >;
808					anatop-max-voltage = < 0x162010 >;
809					phandle = < 0x68 >;
810				};
811
812				regulator-vddpu {
813					compatible = "fsl,anatop-regulator";
814					regulator-name = "vddpu";
815					regulator-min-microvolt = < 0xb1008 >;
816					regulator-max-microvolt = < 0x162010 >;
817					regulator-enable-ramp-delay = < 0x96 >;
818					anatop-reg-offset = < 0x140 >;
819					anatop-vol-bit-shift = < 0x09 >;
820					anatop-vol-bit-width = < 0x05 >;
821					anatop-delay-reg-offset = < 0x170 >;
822					anatop-delay-bit-shift = < 0x1a >;
823					anatop-delay-bit-width = < 0x02 >;
824					anatop-min-bit-val = < 0x01 >;
825					anatop-min-voltage = < 0xb1008 >;
826					anatop-max-voltage = < 0x162010 >;
827					phandle = < 0x24 >;
828				};
829
830				regulator-vddsoc {
831					compatible = "fsl,anatop-regulator";
832					regulator-name = "vddsoc";
833					regulator-min-microvolt = < 0xb1008 >;
834					regulator-max-microvolt = < 0x162010 >;
835					regulator-always-on;
836					anatop-reg-offset = < 0x140 >;
837					anatop-vol-bit-shift = < 0x12 >;
838					anatop-vol-bit-width = < 0x05 >;
839					anatop-delay-reg-offset = < 0x170 >;
840					anatop-delay-bit-shift = < 0x1c >;
841					anatop-delay-bit-width = < 0x02 >;
842					anatop-min-bit-val = < 0x01 >;
843					anatop-min-voltage = < 0xb1008 >;
844					anatop-max-voltage = < 0x162010 >;
845					phandle = < 0x69 >;
846				};
847			};
848
849			usbphy@20c9000 {
850				compatible = "fsl,imx6q-usbphy\0fsl,imx23-usbphy";
851				reg = < 0x20c9000 0x1000 >;
852				interrupts = < 0x00 0x2c 0x04 >;
853				clocks = < 0x04 0xb6 >;
854				fsl,anatop = < 0x02 >;
855				phandle = < 0x2c >;
856			};
857
858			usbphy@20ca000 {
859				compatible = "fsl,imx6q-usbphy\0fsl,imx23-usbphy";
860				reg = < 0x20ca000 0x1000 >;
861				interrupts = < 0x00 0x2d 0x04 >;
862				clocks = < 0x04 0xb7 >;
863				fsl,anatop = < 0x02 >;
864				phandle = < 0x30 >;
865			};
866
867			snvs@20cc000 {
868				compatible = "fsl,sec-v4.0-mon\0syscon\0simple-mfd";
869				reg = < 0x20cc000 0x4000 >;
870				phandle = < 0x23 >;
871
872				snvs-rtc-lp {
873					compatible = "fsl,sec-v4.0-mon-rtc-lp";
874					regmap = < 0x23 >;
875					offset = < 0x34 >;
876					interrupts = < 0x00 0x13 0x04 0x00 0x14 0x04 >;
877				};
878
879				snvs-poweroff {
880					compatible = "syscon-poweroff";
881					regmap = < 0x23 >;
882					offset = < 0x38 >;
883					value = < 0x60 >;
884					mask = < 0x60 >;
885					status = "disabled";
886				};
887
888				snvs-lpgpr {
889					compatible = "fsl,imx6q-snvs-lpgpr";
890				};
891			};
892
893			epit@20d0000 {
894				reg = < 0x20d0000 0x4000 >;
895				interrupts = < 0x00 0x38 0x04 >;
896			};
897
898			epit@20d4000 {
899				reg = < 0x20d4000 0x4000 >;
900				interrupts = < 0x00 0x39 0x04 >;
901			};
902
903			src@20d8000 {
904				compatible = "fsl,imx6q-src\0fsl,imx51-src";
905				reg = < 0x20d8000 0x4000 >;
906				interrupts = < 0x00 0x5b 0x04 0x00 0x60 0x04 >;
907				#reset-cells = < 0x01 >;
908				phandle = < 0x1b >;
909			};
910
911			gpc@20dc000 {
912				compatible = "fsl,imx6q-gpc";
913				reg = < 0x20dc000 0x4000 >;
914				interrupt-controller;
915				#interrupt-cells = < 0x03 >;
916				interrupts = < 0x00 0x59 0x04 0x00 0x5a 0x04 >;
917				interrupt-parent = < 0x16 >;
918				clocks = < 0x04 0x3e >;
919				clock-names = "ipg";
920				phandle = < 0x01 >;
921
922				pgc {
923					#address-cells = < 0x01 >;
924					#size-cells = < 0x00 >;
925
926					power-domain@0 {
927						reg = < 0x00 >;
928						#power-domain-cells = < 0x00 >;
929					};
930
931					power-domain@1 {
932						reg = < 0x01 >;
933						#power-domain-cells = < 0x00 >;
934						power-supply = < 0x24 >;
935						clocks = < 0x04 0x7a 0x04 0x4a 0x04 0x79 0x04 0x1a 0x04 0x8f 0x04 0xa8 >;
936						phandle = < 0x15 >;
937					};
938				};
939			};
940
941			iomuxc-gpr@20e0000 {
942				compatible = "fsl,imx6q-iomuxc-gpr\0syscon\0simple-mfd";
943				reg = < 0x20e0000 0x38 >;
944				phandle = < 0x05 >;
945
946				mux-controller {
947					compatible = "mmio-mux";
948					#mux-control-cells = < 0x01 >;
949					mux-reg-masks = < 0x04 0x80000 0x04 0x100000 0x0c 0x0c 0x0c 0xc0 0x0c 0x300 0x28 0x03 0x28 0x0c >;
950					phandle = < 0x25 >;
951				};
952
953				ipu1_csi0_mux {
954					compatible = "video-mux";
955					mux-controls = < 0x25 0x00 >;
956					#address-cells = < 0x01 >;
957					#size-cells = < 0x00 >;
958
959					port@0 {
960						reg = < 0x00 >;
961
962						endpoint {
963							remote-endpoint = < 0x26 >;
964							phandle = < 0x47 >;
965						};
966					};
967
968					port@1 {
969						reg = < 0x01 >;
970
971						endpoint {
972							remote-endpoint = < 0x27 >;
973							phandle = < 0x44 >;
974						};
975					};
976
977					port@2 {
978						reg = < 0x02 >;
979
980						endpoint {
981							remote-endpoint = < 0x28 >;
982							phandle = < 0x52 >;
983						};
984					};
985				};
986
987				ipu2_csi1_mux {
988					compatible = "video-mux";
989					mux-controls = < 0x25 0x01 >;
990					#address-cells = < 0x01 >;
991					#size-cells = < 0x00 >;
992
993					port@0 {
994						reg = < 0x00 >;
995
996						endpoint {
997							remote-endpoint = < 0x29 >;
998							phandle = < 0x4a >;
999						};
1000					};
1001
1002					port@1 {
1003						reg = < 0x01 >;
1004
1005						endpoint {
1006						};
1007					};
1008
1009					port@2 {
1010						reg = < 0x02 >;
1011
1012						endpoint {
1013							remote-endpoint = < 0x2a >;
1014							phandle = < 0x5e >;
1015						};
1016					};
1017				};
1018			};
1019
1020			iomuxc@20e0000 {
1021				compatible = "fsl,imx6q-iomuxc";
1022				reg = < 0x20e0000 0x4000 >;
1023				pinctrl-names = "default";
1024				pinctrl-0 = < 0x2b >;
1025				phandle = < 0x22 >;
1026
1027				imx6q-sabrelite {
1028
1029					hoggrp {
1030						fsl,pins = < 0x220 0x5f0 0x00 0x00 0x00 0x30b0 >;
1031						phandle = < 0x2b >;
1032					};
1033
1034					audmuxgrp {
1035						fsl,pins = < 0x54 0x368 0x7b4 0x03 0x00 0x130b0 0x35c 0x744 0x7c4 0x03 0x01 0x130b0 0x50 0x364 0x7b8 0x03 0x00 0x110b0 0x4c 0x360 0x7c8 0x03 0x00 0x130b0 >;
1036						phandle = < 0x46 >;
1037					};
1038
1039					can1grp {
1040						fsl,pins = < 0x208 0x5d8 0x00 0x02 0x00 0x1b0b0 0x20c 0x5dc 0x7e4 0x02 0x00 0x1b0b0 >;
1041						phandle = < 0x20 >;
1042					};
1043
1044					can-xcvrgrp {
1045						fsl,pins = < 0x234 0x604 0x00 0x05 0x00 0x1b0b0 >;
1046						phandle = < 0x72 >;
1047					};
1048
1049					ecspi1grp {
1050						fsl,pins = < 0x94 0x3a8 0x7f8 0x01 0x00 0x100b1 0x98 0x3ac 0x7fc 0x01 0x00 0x100b1 0x90 0x3a4 0x7f4 0x01 0x00 0x100b1 0x9c 0x3b0 0x00 0x05 0x00 0xb1 >;
1051						phandle = < 0x19 >;
1052					};
1053
1054					enetgrp {
1055						fsl,pins = < 0x1d0 0x4e4 0x840 0x01 0x00 0x100b0 0x1f4 0x508 0x00 0x01 0x00 0x100b0 0x58 0x36c 0x00 0x01 0x00 0x10030 0x5c 0x370 0x00 0x01 0x00 0x10030 0x60 0x374 0x00 0x01 0x00 0x10030 0x64 0x378 0x00 0x01 0x00 0x10030 0x68 0x37c 0x00 0x01 0x00 0x10030 0x74 0x388 0x00 0x01 0x00 0x10030 0x1d4 0x4e8 0x00 0x01 0x00 0x100b0 0x84 0x398 0x844 0x01 0x00 0x1b030 0x70 0x384 0x848 0x01 0x00 0x1b030 0x78 0x38c 0x84c 0x01 0x00 0x1b030 0x7c 0x390 0x850 0x01 0x00 0x1b030 0x80 0x394 0x854 0x01 0x00 0x1b030 0x6c 0x380 0x858 0x01 0x00 0x1b030 0xac 0x3c0 0x00 0x05 0x00 0xb0 >;
1056						phandle = < 0x32 >;
1057					};
1058
1059					gpio-keysgrp {
1060						fsl,pins = < 0x308 0x6f0 0x00 0x05 0x00 0x1b0b0 0x300 0x6e8 0x00 0x05 0x00 0x1b0b0 0x30c 0x6f4 0x00 0x05 0x00 0x1b0b0 0x304 0x6ec 0x00 0x05 0x00 0x1b0b0 0x250 0x620 0x00 0x05 0x00 0x1b0b0 0x254 0x624 0x00 0x05 0x00 0x1b0b0 >;
1061						phandle = < 0x75 >;
1062					};
1063
1064					i2c1grp {
1065						fsl,pins = < 0xa4 0x3b8 0x898 0x06 0x00 0x4001b8b1 0xc4 0x3d8 0x89c 0x01 0x00 0x4001b8b1 >;
1066						phandle = < 0x38 >;
1067					};
1068
1069					i2c2grp {
1070						fsl,pins = < 0x210 0x5e0 0x8a0 0x04 0x01 0x4001b8b1 0x214 0x5e4 0x8a4 0x04 0x01 0x4001b8b1 >;
1071						phandle = < 0x3a >;
1072					};
1073
1074					i2c3grp {
1075						fsl,pins = < 0x23c 0x60c 0x8a8 0x06 0x02 0x4001b8b1 0x248 0x618 0x8ac 0x06 0x02 0x4001b8b1 >;
1076						phandle = < 0x45 >;
1077					};
1078
1079					ipu1csi0grp {
1080						fsl,pins = < 0x288 0x658 0x00 0x00 0x00 0x1b0b0 0x28c 0x65c 0x00 0x00 0x00 0x1b0b0 0x290 0x660 0x00 0x00 0x00 0x1b0b0 0x294 0x664 0x00 0x00 0x00 0x1b0b0 0x298 0x668 0x00 0x00 0x00 0x1b0b0 0x29c 0x66c 0x00 0x00 0x00 0x1b0b0 0x2a0 0x670 0x00 0x00 0x00 0x1b0b0 0x2a4 0x674 0x00 0x00 0x00 0x1b0b0 0x258 0x628 0x00 0x00 0x00 0x1b0b0 0x25c 0x62c 0x00 0x00 0x00 0x1b0b0 0x264 0x634 0x00 0x00 0x00 0x1b0b0 0x260 0x630 0x00 0x00 0x00 0x1b0b0 >;
1081						phandle = < 0x51 >;
1082					};
1083
1084					j15grp {
1085						fsl,pins = < 0x15c 0x470 0x00 0x00 0x00 0x10 0x160 0x474 0x00 0x00 0x00 0x10 0x164 0x478 0x00 0x00 0x00 0x10 0x168 0x47c 0x00 0x00 0x00 0x10 0x170 0x484 0x00 0x00 0x00 0x10 0x174 0x488 0x00 0x00 0x00 0x10 0x178 0x48c 0x00 0x00 0x00 0x10 0x17c 0x490 0x00 0x00 0x00 0x10 0x180 0x494 0x00 0x00 0x00 0x10 0x184 0x498 0x00 0x00 0x00 0x10 0x188 0x49c 0x00 0x00 0x00 0x10 0x18c 0x4a0 0x00 0x00 0x00 0x10 0x190 0x4a4 0x00 0x00 0x00 0x10 0x194 0x4a8 0x00 0x00 0x00 0x10 0x198 0x4ac 0x00 0x00 0x00 0x10 0x19c 0x4b0 0x00 0x00 0x00 0x10 0x1a0 0x4b4 0x00 0x00 0x00 0x10 0x1a4 0x4b8 0x00 0x00 0x00 0x10 0x1a8 0x4bc 0x00 0x00 0x00 0x10 0x1ac 0x4c0 0x00 0x00 0x00 0x10 0x1b0 0x4c4 0x00 0x00 0x00 0x10 0x1b4 0x4c8 0x00 0x00 0x00 0x10 0x1b8 0x4cc 0x00 0x00 0x00 0x10 0x1bc 0x4d0 0x00 0x00 0x00 0x10 0x1c0 0x4d4 0x00 0x00 0x00 0x10 0x1c4 0x4d8 0x00 0x00 0x00 0x10 0x1c8 0x4dc 0x00 0x00 0x00 0x10 0x1cc 0x4e0 0x00 0x00 0x00 0x10 >;
1086						phandle = < 0x7b >;
1087					};
1088
1089					ov5640grp {
1090						fsl,pins = < 0x310 0x6f8 0x00 0x05 0x00 0xb0 0x2dc 0x6c4 0x00 0x05 0x00 0xb0b0 >;
1091						phandle = < 0x3b >;
1092					};
1093
1094					ov5642grp {
1095						fsl,pins = < 0x340 0x728 0x00 0x05 0x00 0x1b0b0 0x230 0x600 0x00 0x05 0x00 0x1b0b0 0x244 0x614 0x00 0x05 0x00 0x130b0 0x22c 0x5fc 0x00 0x04 0x00 0xb0 >;
1096						phandle = < 0x42 >;
1097					};
1098
1099					pwm1grp {
1100						fsl,pins = < 0x344 0x72c 0x00 0x03 0x00 0x1b0b1 >;
1101						phandle = < 0x1d >;
1102					};
1103
1104					pwm3grp {
1105						fsl,pins = < 0x33c 0x724 0x00 0x02 0x00 0x1b0b1 >;
1106						phandle = < 0x1e >;
1107					};
1108
1109					pwm4grp {
1110						fsl,pins = < 0x348 0x730 0x00 0x02 0x00 0x1b0b1 >;
1111						phandle = < 0x1f >;
1112					};
1113
1114					uart1grp {
1115						fsl,pins = < 0x2a8 0x690 0x00 0x01 0x00 0x1b0b1 0x2ac 0x694 0x920 0x01 0x03 0x1b0b1 >;
1116						phandle = < 0x1a >;
1117					};
1118
1119					uart2grp {
1120						fsl,pins = < 0xbc 0x3d0 0x00 0x04 0x00 0x1b0b1 0xc0 0x3d4 0x928 0x04 0x01 0x1b0b1 >;
1121						phandle = < 0x50 >;
1122					};
1123
1124					usbh1grp {
1125						fsl,pins = < 0x24c 0x61c 0x00 0x05 0x00 0x30b0 >;
1126						phandle = < 0x73 >;
1127					};
1128
1129					usbotggrp {
1130						fsl,pins = < 0x224 0x5f4 0x04 0x03 0xff0d0101 0x17059 0x218 0x5e8 0x944 0x02 0x01 0x1b0b0 0xa8 0x3bc 0x00 0x05 0x00 0xb0 >;
1131						phandle = < 0x2f >;
1132					};
1133
1134					usdhc3grp {
1135						fsl,pins = < 0x2b8 0x6a0 0x00 0x00 0x00 0x17059 0x2bc 0x6a4 0x00 0x00 0x00 0x10059 0x2c0 0x6a8 0x00 0x00 0x00 0x17059 0x2c4 0x6ac 0x00 0x00 0x00 0x17059 0x2c8 0x6b0 0x00 0x00 0x00 0x17059 0x2cc 0x6b4 0x00 0x00 0x00 0x17059 0x2b0 0x698 0x00 0x05 0x00 0x1b0b0 0x2b4 0x69c 0x00 0x05 0x00 0x1f0b0 >;
1136						phandle = < 0x33 >;
1137					};
1138
1139					usdhc4grp {
1140						fsl,pins = < 0x2f4 0x6dc 0x00 0x00 0x00 0x17059 0x2f8 0x6e0 0x00 0x00 0x00 0x10059 0x31c 0x704 0x00 0x01 0x00 0x17059 0x320 0x708 0x00 0x01 0x00 0x17059 0x324 0x70c 0x00 0x01 0x00 0x17059 0x328 0x710 0x00 0x01 0x00 0x17059 0x314 0x6fc 0x00 0x05 0x00 0x1b0b0 >;
1141						phandle = < 0x36 >;
1142					};
1143				};
1144			};
1145
1146			dcic@20e4000 {
1147				reg = < 0x20e4000 0x4000 >;
1148				interrupts = < 0x00 0x7c 0x04 >;
1149			};
1150
1151			dcic@20e8000 {
1152				reg = < 0x20e8000 0x4000 >;
1153				interrupts = < 0x00 0x7d 0x04 >;
1154			};
1155
1156			sdma@20ec000 {
1157				compatible = "fsl,imx6q-sdma\0fsl,imx35-sdma";
1158				reg = < 0x20ec000 0x4000 >;
1159				interrupts = < 0x00 0x02 0x04 >;
1160				clocks = < 0x04 0x9b 0x04 0x9b >;
1161				clock-names = "ipg\0ahb";
1162				#dma-cells = < 0x03 >;
1163				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
1164				phandle = < 0x17 >;
1165			};
1166		};
1167
1168		aips-bus@2100000 {
1169			compatible = "fsl,aips-bus\0simple-bus";
1170			#address-cells = < 0x01 >;
1171			#size-cells = < 0x01 >;
1172			reg = < 0x2100000 0x100000 >;
1173			ranges;
1174
1175			caam@2100000 {
1176				compatible = "fsl,sec-v4.0";
1177				#address-cells = < 0x01 >;
1178				#size-cells = < 0x01 >;
1179				reg = < 0x2100000 0x10000 >;
1180				ranges = < 0x00 0x2100000 0x10000 >;
1181				clocks = < 0x04 0xf1 0x04 0xf2 0x04 0xf3 0x04 0xc4 >;
1182				clock-names = "mem\0aclk\0ipg\0emi_slow";
1183
1184				jr0@1000 {
1185					compatible = "fsl,sec-v4.0-job-ring";
1186					reg = < 0x1000 0x1000 >;
1187					interrupts = < 0x00 0x69 0x04 >;
1188				};
1189
1190				jr1@2000 {
1191					compatible = "fsl,sec-v4.0-job-ring";
1192					reg = < 0x2000 0x1000 >;
1193					interrupts = < 0x00 0x6a 0x04 >;
1194				};
1195			};
1196
1197			aipstz@217c000 {
1198				reg = < 0x217c000 0x4000 >;
1199			};
1200
1201			usb@2184000 {
1202				compatible = "fsl,imx6q-usb\0fsl,imx27-usb";
1203				reg = < 0x2184000 0x200 >;
1204				interrupts = < 0x00 0x2b 0x04 >;
1205				clocks = < 0x04 0xa2 >;
1206				fsl,usbphy = < 0x2c >;
1207				fsl,usbmisc = < 0x2d 0x00 >;
1208				ahb-burst-config = < 0x00 >;
1209				tx-burst-size-dword = < 0x10 >;
1210				rx-burst-size-dword = < 0x10 >;
1211				status = "okay";
1212				vbus-supply = < 0x2e >;
1213				pinctrl-names = "default";
1214				pinctrl-0 = < 0x2f >;
1215				disable-over-current;
1216			};
1217
1218			usb@2184200 {
1219				compatible = "fsl,imx6q-usb\0fsl,imx27-usb";
1220				reg = < 0x2184200 0x200 >;
1221				interrupts = < 0x00 0x28 0x04 >;
1222				clocks = < 0x04 0xa2 >;
1223				fsl,usbphy = < 0x30 >;
1224				fsl,usbmisc = < 0x2d 0x01 >;
1225				dr_mode = "host";
1226				ahb-burst-config = < 0x00 >;
1227				tx-burst-size-dword = < 0x10 >;
1228				rx-burst-size-dword = < 0x10 >;
1229				status = "okay";
1230				vbus-supply = < 0x31 >;
1231			};
1232
1233			usb@2184400 {
1234				compatible = "fsl,imx6q-usb\0fsl,imx27-usb";
1235				reg = < 0x2184400 0x200 >;
1236				interrupts = < 0x00 0x29 0x04 >;
1237				clocks = < 0x04 0xa2 >;
1238				fsl,usbmisc = < 0x2d 0x02 >;
1239				dr_mode = "host";
1240				ahb-burst-config = < 0x00 >;
1241				tx-burst-size-dword = < 0x10 >;
1242				rx-burst-size-dword = < 0x10 >;
1243				status = "disabled";
1244			};
1245
1246			usb@2184600 {
1247				compatible = "fsl,imx6q-usb\0fsl,imx27-usb";
1248				reg = < 0x2184600 0x200 >;
1249				interrupts = < 0x00 0x2a 0x04 >;
1250				clocks = < 0x04 0xa2 >;
1251				fsl,usbmisc = < 0x2d 0x03 >;
1252				dr_mode = "host";
1253				ahb-burst-config = < 0x00 >;
1254				tx-burst-size-dword = < 0x10 >;
1255				rx-burst-size-dword = < 0x10 >;
1256				status = "disabled";
1257			};
1258
1259			usbmisc@2184800 {
1260				#index-cells = < 0x01 >;
1261				compatible = "fsl,imx6q-usbmisc";
1262				reg = < 0x2184800 0x200 >;
1263				clocks = < 0x04 0xa2 >;
1264				phandle = < 0x2d >;
1265			};
1266
1267			ethernet@2188000 {
1268				compatible = "fsl,imx6q-fec";
1269				reg = < 0x2188000 0x4000 >;
1270				interrupt-names = "int0\0pps";
1271				interrupts-extended = < 0x16 0x00 0x76 0x04 0x16 0x00 0x77 0x04 >;
1272				clocks = < 0x04 0x75 0x04 0x75 0x04 0xbe >;
1273				clock-names = "ipg\0ahb\0ptp";
1274				status = "okay";
1275				pinctrl-names = "default";
1276				pinctrl-0 = < 0x32 >;
1277				phy-mode = "rgmii";
1278				phy-reset-gpios = < 0x18 0x17 0x01 >;
1279				txen-skew-ps = < 0x00 >;
1280				txc-skew-ps = < 0xbb8 >;
1281				rxdv-skew-ps = < 0x00 >;
1282				rxc-skew-ps = < 0xbb8 >;
1283				rxd0-skew-ps = < 0x00 >;
1284				rxd1-skew-ps = < 0x00 >;
1285				rxd2-skew-ps = < 0x00 >;
1286				rxd3-skew-ps = < 0x00 >;
1287				txd0-skew-ps = < 0x00 >;
1288				txd1-skew-ps = < 0x00 >;
1289				txd2-skew-ps = < 0x00 >;
1290				txd3-skew-ps = < 0x00 >;
1291			};
1292
1293			mlb@218c000 {
1294				reg = < 0x218c000 0x4000 >;
1295				interrupts = < 0x00 0x35 0x04 0x00 0x75 0x04 0x00 0x7e 0x04 >;
1296			};
1297
1298			usdhc@2190000 {
1299				compatible = "fsl,imx6q-usdhc";
1300				reg = < 0x2190000 0x4000 >;
1301				interrupts = < 0x00 0x16 0x04 >;
1302				clocks = < 0x04 0xa3 0x04 0xa3 0x04 0xa3 >;
1303				clock-names = "ipg\0ahb\0per";
1304				bus-width = < 0x04 >;
1305				status = "disabled";
1306			};
1307
1308			usdhc@2194000 {
1309				compatible = "fsl,imx6q-usdhc";
1310				reg = < 0x2194000 0x4000 >;
1311				interrupts = < 0x00 0x17 0x04 >;
1312				clocks = < 0x04 0xa4 0x04 0xa4 0x04 0xa4 >;
1313				clock-names = "ipg\0ahb\0per";
1314				bus-width = < 0x04 >;
1315				status = "disabled";
1316			};
1317
1318			usdhc@2198000 {
1319				compatible = "fsl,imx6q-usdhc";
1320				reg = < 0x2198000 0x4000 >;
1321				interrupts = < 0x00 0x18 0x04 >;
1322				clocks = < 0x04 0xa5 0x04 0xa5 0x04 0xa5 >;
1323				clock-names = "ipg\0ahb\0per";
1324				bus-width = < 0x04 >;
1325				status = "okay";
1326				pinctrl-names = "default";
1327				pinctrl-0 = < 0x33 >;
1328				cd-gpios = < 0x34 0x00 0x01 >;
1329				wp-gpios = < 0x34 0x01 0x00 >;
1330				vmmc-supply = < 0x35 >;
1331			};
1332
1333			usdhc@219c000 {
1334				compatible = "fsl,imx6q-usdhc";
1335				reg = < 0x219c000 0x4000 >;
1336				interrupts = < 0x00 0x19 0x04 >;
1337				clocks = < 0x04 0xa6 0x04 0xa6 0x04 0xa6 >;
1338				clock-names = "ipg\0ahb\0per";
1339				bus-width = < 0x04 >;
1340				status = "okay";
1341				pinctrl-names = "default";
1342				pinctrl-0 = < 0x36 >;
1343				cd-gpios = < 0x37 0x06 0x01 >;
1344				vmmc-supply = < 0x35 >;
1345			};
1346
1347			i2c@21a0000 {
1348				#address-cells = < 0x01 >;
1349				#size-cells = < 0x00 >;
1350				compatible = "fsl,imx6q-i2c\0fsl,imx21-i2c";
1351				reg = < 0x21a0000 0x4000 >;
1352				interrupts = < 0x00 0x24 0x04 >;
1353				clocks = < 0x04 0x7d >;
1354				status = "okay";
1355				clock-frequency = < 0x186a0 >;
1356				pinctrl-names = "default";
1357				pinctrl-0 = < 0x38 >;
1358
1359				sgtl5000@a {
1360					compatible = "fsl,sgtl5000";
1361					reg = < 0x0a >;
1362					clocks = < 0x04 0xc9 >;
1363					VDDA-supply = < 0x39 >;
1364					VDDIO-supply = < 0x35 >;
1365					phandle = < 0x78 >;
1366				};
1367			};
1368
1369			i2c@21a4000 {
1370				#address-cells = < 0x01 >;
1371				#size-cells = < 0x00 >;
1372				compatible = "fsl,imx6q-i2c\0fsl,imx21-i2c";
1373				reg = < 0x21a4000 0x4000 >;
1374				interrupts = < 0x00 0x25 0x04 >;
1375				clocks = < 0x04 0x7e >;
1376				status = "okay";
1377				clock-frequency = < 0x186a0 >;
1378				pinctrl-names = "default";
1379				pinctrl-0 = < 0x3a >;
1380				phandle = < 0x10 >;
1381
1382				camera@40 {
1383					compatible = "ovti,ov5640";
1384					pinctrl-names = "default";
1385					pinctrl-0 = < 0x3b >;
1386					reg = < 0x40 >;
1387					clocks = < 0x3c >;
1388					clock-names = "xclk";
1389					DOVDD-supply = < 0x3d >;
1390					AVDD-supply = < 0x3e >;
1391					DVDD-supply = < 0x3f >;
1392					reset-gpios = < 0x37 0x05 0x01 >;
1393					powerdown-gpios = < 0x40 0x09 0x00 >;
1394
1395					port {
1396
1397						endpoint {
1398							remote-endpoint = < 0x41 >;
1399							clock-lanes = < 0x00 >;
1400							data-lanes = < 0x01 0x02 >;
1401							phandle = < 0x4b >;
1402						};
1403					};
1404				};
1405
1406				camera@42 {
1407					compatible = "ovti,ov5642";
1408					pinctrl-names = "default";
1409					pinctrl-0 = < 0x42 >;
1410					clocks = < 0x04 0xc8 >;
1411					clock-names = "xclk";
1412					reg = < 0x42 >;
1413					reset-gpios = < 0x43 0x08 0x01 >;
1414					powerdown-gpios = < 0x43 0x06 0x00 >;
1415					gp-gpios = < 0x43 0x10 0x00 >;
1416					status = "disabled";
1417
1418					port {
1419
1420						endpoint {
1421							remote-endpoint = < 0x44 >;
1422							bus-width = < 0x08 >;
1423							hsync-active = < 0x01 >;
1424							vsync-active = < 0x01 >;
1425							phandle = < 0x27 >;
1426						};
1427					};
1428				};
1429			};
1430
1431			i2c@21a8000 {
1432				#address-cells = < 0x01 >;
1433				#size-cells = < 0x00 >;
1434				compatible = "fsl,imx6q-i2c\0fsl,imx21-i2c";
1435				reg = < 0x21a8000 0x4000 >;
1436				interrupts = < 0x00 0x26 0x04 >;
1437				clocks = < 0x04 0x7f >;
1438				status = "okay";
1439				clock-frequency = < 0x186a0 >;
1440				pinctrl-names = "default";
1441				pinctrl-0 = < 0x45 >;
1442			};
1443
1444			romcp@21ac000 {
1445				reg = < 0x21ac000 0x4000 >;
1446			};
1447
1448			mmdc@21b0000 {
1449				compatible = "fsl,imx6q-mmdc";
1450				reg = < 0x21b0000 0x4000 >;
1451			};
1452
1453			mmdc@21b4000 {
1454				reg = < 0x21b4000 0x4000 >;
1455			};
1456
1457			weim@21b8000 {
1458				#address-cells = < 0x02 >;
1459				#size-cells = < 0x01 >;
1460				compatible = "fsl,imx6q-weim";
1461				reg = < 0x21b8000 0x4000 >;
1462				interrupts = < 0x00 0x0e 0x04 >;
1463				clocks = < 0x04 0xc4 >;
1464				fsl,weim-cs-gpr = < 0x05 >;
1465				status = "disabled";
1466			};
1467
1468			ocotp@21bc000 {
1469				compatible = "fsl,imx6q-ocotp\0syscon";
1470				reg = < 0x21bc000 0x4000 >;
1471				clocks = < 0x04 0x80 >;
1472				phandle = < 0x03 >;
1473			};
1474
1475			tzasc@21d0000 {
1476				reg = < 0x21d0000 0x4000 >;
1477				interrupts = < 0x00 0x6c 0x04 >;
1478			};
1479
1480			tzasc@21d4000 {
1481				reg = < 0x21d4000 0x4000 >;
1482				interrupts = < 0x00 0x6d 0x04 >;
1483			};
1484
1485			audmux@21d8000 {
1486				compatible = "fsl,imx6q-audmux\0fsl,imx31-audmux";
1487				reg = < 0x21d8000 0x4000 >;
1488				status = "okay";
1489				pinctrl-names = "default";
1490				pinctrl-0 = < 0x46 >;
1491			};
1492
1493			mipi@21dc000 {
1494				compatible = "fsl,imx6-mipi-csi2";
1495				reg = < 0x21dc000 0x4000 >;
1496				#address-cells = < 0x01 >;
1497				#size-cells = < 0x00 >;
1498				interrupts = < 0x00 0x64 0x04 0x00 0x65 0x04 >;
1499				clocks = < 0x04 0x8a 0x04 0xee 0x04 0x61 >;
1500				clock-names = "dphy\0ref\0pix";
1501				status = "okay";
1502
1503				port@1 {
1504					reg = < 0x01 >;
1505
1506					endpoint {
1507						remote-endpoint = < 0x47 >;
1508						phandle = < 0x26 >;
1509					};
1510				};
1511
1512				port@2 {
1513					reg = < 0x02 >;
1514
1515					endpoint {
1516						remote-endpoint = < 0x48 >;
1517						phandle = < 0x53 >;
1518					};
1519				};
1520
1521				port@3 {
1522					reg = < 0x03 >;
1523
1524					endpoint {
1525						remote-endpoint = < 0x49 >;
1526						phandle = < 0x5d >;
1527					};
1528				};
1529
1530				port@4 {
1531					reg = < 0x04 >;
1532
1533					endpoint {
1534						remote-endpoint = < 0x4a >;
1535						phandle = < 0x29 >;
1536					};
1537				};
1538
1539				port@0 {
1540					reg = < 0x00 >;
1541
1542					endpoint {
1543						remote-endpoint = < 0x4b >;
1544						clock-lanes = < 0x00 >;
1545						data-lanes = < 0x01 0x02 >;
1546						phandle = < 0x41 >;
1547					};
1548				};
1549			};
1550
1551			mipi@21e0000 {
1552				reg = < 0x21e0000 0x4000 >;
1553				status = "disabled";
1554
1555				ports {
1556					#address-cells = < 0x01 >;
1557					#size-cells = < 0x00 >;
1558
1559					port@0 {
1560						reg = < 0x00 >;
1561
1562						endpoint {
1563							remote-endpoint = < 0x4c >;
1564							phandle = < 0x56 >;
1565						};
1566					};
1567
1568					port@1 {
1569						reg = < 0x01 >;
1570
1571						endpoint {
1572							remote-endpoint = < 0x4d >;
1573							phandle = < 0x5a >;
1574						};
1575					};
1576
1577					port@2 {
1578						reg = < 0x02 >;
1579
1580						endpoint {
1581							remote-endpoint = < 0x4e >;
1582							phandle = < 0x60 >;
1583						};
1584					};
1585
1586					port@3 {
1587						reg = < 0x03 >;
1588
1589						endpoint {
1590							remote-endpoint = < 0x4f >;
1591							phandle = < 0x64 >;
1592						};
1593					};
1594				};
1595			};
1596
1597			vdoa@21e4000 {
1598				compatible = "fsl,imx6q-vdoa";
1599				reg = < 0x21e4000 0x4000 >;
1600				interrupts = < 0x00 0x12 0x04 >;
1601				clocks = < 0x04 0xca >;
1602			};
1603
1604			serial@21e8000 {
1605				compatible = "fsl,imx6q-uart\0fsl,imx21-uart";
1606				reg = < 0x21e8000 0x4000 >;
1607				interrupts = < 0x00 0x1b 0x04 >;
1608				clocks = < 0x04 0xa0 0x04 0xa1 >;
1609				clock-names = "ipg\0per";
1610				dmas = < 0x17 0x1b 0x04 0x00 0x17 0x1c 0x04 0x00 >;
1611				dma-names = "rx\0tx";
1612				status = "okay";
1613				pinctrl-names = "default";
1614				pinctrl-0 = < 0x50 >;
1615			};
1616
1617			serial@21ec000 {
1618				compatible = "fsl,imx6q-uart\0fsl,imx21-uart";
1619				reg = < 0x21ec000 0x4000 >;
1620				interrupts = < 0x00 0x1c 0x04 >;
1621				clocks = < 0x04 0xa0 0x04 0xa1 >;
1622				clock-names = "ipg\0per";
1623				dmas = < 0x17 0x1d 0x04 0x00 0x17 0x1e 0x04 0x00 >;
1624				dma-names = "rx\0tx";
1625				status = "disabled";
1626			};
1627
1628			serial@21f0000 {
1629				compatible = "fsl,imx6q-uart\0fsl,imx21-uart";
1630				reg = < 0x21f0000 0x4000 >;
1631				interrupts = < 0x00 0x1d 0x04 >;
1632				clocks = < 0x04 0xa0 0x04 0xa1 >;
1633				clock-names = "ipg\0per";
1634				dmas = < 0x17 0x1f 0x04 0x00 0x17 0x20 0x04 0x00 >;
1635				dma-names = "rx\0tx";
1636				status = "disabled";
1637			};
1638
1639			serial@21f4000 {
1640				compatible = "fsl,imx6q-uart\0fsl,imx21-uart";
1641				reg = < 0x21f4000 0x4000 >;
1642				interrupts = < 0x00 0x1e 0x04 >;
1643				clocks = < 0x04 0xa0 0x04 0xa1 >;
1644				clock-names = "ipg\0per";
1645				dmas = < 0x17 0x21 0x04 0x00 0x17 0x22 0x04 0x00 >;
1646				dma-names = "rx\0tx";
1647				status = "disabled";
1648			};
1649		};
1650
1651		ipu@2400000 {
1652			#address-cells = < 0x01 >;
1653			#size-cells = < 0x00 >;
1654			compatible = "fsl,imx6q-ipu";
1655			reg = < 0x2400000 0x400000 >;
1656			interrupts = < 0x00 0x06 0x04 0x00 0x05 0x04 >;
1657			clocks = < 0x04 0x82 0x04 0x83 0x04 0x84 >;
1658			clock-names = "bus\0di0\0di1";
1659			resets = < 0x1b 0x02 >;
1660
1661			port@0 {
1662				reg = < 0x00 >;
1663				pinctrl-names = "default";
1664				pinctrl-0 = < 0x51 >;
1665				phandle = < 0x6a >;
1666
1667				endpoint {
1668					remote-endpoint = < 0x52 >;
1669					bus-width = < 0x08 >;
1670					data-shift = < 0x0c >;
1671					hsync-active = < 0x01 >;
1672					vync-active = < 0x01 >;
1673					phandle = < 0x28 >;
1674				};
1675			};
1676
1677			port@1 {
1678				reg = < 0x01 >;
1679				phandle = < 0x6b >;
1680
1681				endpoint {
1682					remote-endpoint = < 0x53 >;
1683					clock-lanes = < 0x00 >;
1684					data-lanes = < 0x01 0x02 >;
1685					phandle = < 0x48 >;
1686				};
1687			};
1688
1689			port@2 {
1690				#address-cells = < 0x01 >;
1691				#size-cells = < 0x00 >;
1692				reg = < 0x02 >;
1693				phandle = < 0x6e >;
1694
1695				endpoint@0 {
1696					reg = < 0x00 >;
1697					remote-endpoint = < 0x54 >;
1698					phandle = < 0x7c >;
1699				};
1700
1701				endpoint@1 {
1702					reg = < 0x01 >;
1703					remote-endpoint = < 0x55 >;
1704					phandle = < 0x11 >;
1705				};
1706
1707				endpoint@2 {
1708					reg = < 0x02 >;
1709					remote-endpoint = < 0x56 >;
1710					phandle = < 0x4c >;
1711				};
1712
1713				endpoint@3 {
1714					reg = < 0x03 >;
1715					remote-endpoint = < 0x57 >;
1716					phandle = < 0x06 >;
1717				};
1718
1719				endpoint@4 {
1720					reg = < 0x04 >;
1721					remote-endpoint = < 0x58 >;
1722					phandle = < 0x0b >;
1723				};
1724			};
1725
1726			port@3 {
1727				#address-cells = < 0x01 >;
1728				#size-cells = < 0x00 >;
1729				reg = < 0x03 >;
1730				phandle = < 0x6f >;
1731
1732				endpoint@0 {
1733					reg = < 0x00 >;
1734				};
1735
1736				endpoint@1 {
1737					reg = < 0x01 >;
1738					remote-endpoint = < 0x59 >;
1739					phandle = < 0x12 >;
1740				};
1741
1742				endpoint@2 {
1743					reg = < 0x02 >;
1744					remote-endpoint = < 0x5a >;
1745					phandle = < 0x4d >;
1746				};
1747
1748				endpoint@3 {
1749					reg = < 0x03 >;
1750					remote-endpoint = < 0x5b >;
1751					phandle = < 0x07 >;
1752				};
1753
1754				endpoint@4 {
1755					reg = < 0x04 >;
1756					remote-endpoint = < 0x5c >;
1757					phandle = < 0x0c >;
1758				};
1759			};
1760		};
1761
1762		sram@900000 {
1763			compatible = "mmio-sram";
1764			reg = < 0x900000 0x40000 >;
1765			clocks = < 0x04 0x8e >;
1766			phandle = < 0x1c >;
1767		};
1768
1769		sata@2200000 {
1770			compatible = "fsl,imx6q-ahci";
1771			reg = < 0x2200000 0x4000 >;
1772			interrupts = < 0x00 0x27 0x04 >;
1773			clocks = < 0x04 0x9a 0x04 0xbb 0x04 0x69 >;
1774			clock-names = "sata\0sata_ref\0ahb";
1775			status = "okay";
1776		};
1777
1778		gpu@2204000 {
1779			compatible = "vivante,gc";
1780			reg = < 0x2204000 0x4000 >;
1781			interrupts = < 0x00 0x0b 0x04 >;
1782			clocks = < 0x04 0x8f 0x04 0x79 >;
1783			clock-names = "bus\0core";
1784			power-domains = < 0x15 >;
1785		};
1786
1787		ipu@2800000 {
1788			#address-cells = < 0x01 >;
1789			#size-cells = < 0x00 >;
1790			compatible = "fsl,imx6q-ipu";
1791			reg = < 0x2800000 0x400000 >;
1792			interrupts = < 0x00 0x08 0x04 0x00 0x07 0x04 >;
1793			clocks = < 0x04 0x85 0x04 0x86 0x04 0x89 >;
1794			clock-names = "bus\0di0\0di1";
1795			resets = < 0x1b 0x04 >;
1796
1797			port@0 {
1798				reg = < 0x00 >;
1799				phandle = < 0x6c >;
1800
1801				endpoint {
1802					remote-endpoint = < 0x5d >;
1803					phandle = < 0x49 >;
1804				};
1805			};
1806
1807			port@1 {
1808				reg = < 0x01 >;
1809				phandle = < 0x6d >;
1810
1811				endpoint {
1812					remote-endpoint = < 0x5e >;
1813					phandle = < 0x2a >;
1814				};
1815			};
1816
1817			port@2 {
1818				#address-cells = < 0x01 >;
1819				#size-cells = < 0x00 >;
1820				reg = < 0x02 >;
1821				phandle = < 0x70 >;
1822
1823				endpoint@0 {
1824					reg = < 0x00 >;
1825				};
1826
1827				endpoint@1 {
1828					reg = < 0x01 >;
1829					remote-endpoint = < 0x5f >;
1830					phandle = < 0x13 >;
1831				};
1832
1833				endpoint@2 {
1834					reg = < 0x02 >;
1835					remote-endpoint = < 0x60 >;
1836					phandle = < 0x4e >;
1837				};
1838
1839				endpoint@3 {
1840					reg = < 0x03 >;
1841					remote-endpoint = < 0x61 >;
1842					phandle = < 0x08 >;
1843				};
1844
1845				endpoint@4 {
1846					reg = < 0x04 >;
1847					remote-endpoint = < 0x62 >;
1848					phandle = < 0x0d >;
1849				};
1850			};
1851
1852			port@3 {
1853				#address-cells = < 0x01 >;
1854				#size-cells = < 0x00 >;
1855				reg = < 0x03 >;
1856				phandle = < 0x71 >;
1857
1858				endpoint@1 {
1859					reg = < 0x01 >;
1860					remote-endpoint = < 0x63 >;
1861					phandle = < 0x14 >;
1862				};
1863
1864				endpoint@2 {
1865					reg = < 0x02 >;
1866					remote-endpoint = < 0x64 >;
1867					phandle = < 0x4f >;
1868				};
1869
1870				endpoint@3 {
1871					reg = < 0x03 >;
1872					remote-endpoint = < 0x65 >;
1873					phandle = < 0x09 >;
1874				};
1875
1876				endpoint@4 {
1877					reg = < 0x04 >;
1878					remote-endpoint = < 0x66 >;
1879					phandle = < 0x0e >;
1880				};
1881			};
1882		};
1883	};
1884
1885	cpus {
1886		#address-cells = < 0x01 >;
1887		#size-cells = < 0x00 >;
1888
1889		cpu@0 {
1890			compatible = "arm,cortex-a9";
1891			device_type = "cpu";
1892			reg = < 0x00 >;
1893			next-level-cache = < 0x67 >;
1894			operating-points = < 0x124f80 0x137478 0xf32a0 0x1312d0 0xd0020 0x1312d0 0xc15c0 0x11edd8 0x60ae0 0xee098 >;
1895			fsl,soc-operating-points = < 0x124f80 0x137478 0xf32a0 0x1312d0 0xd0020 0x1312d0 0xc15c0 0x11edd8 0x60ae0 0x11edd8 >;
1896			clock-latency = < 0xee6c >;
1897			#cooling-cells = < 0x02 >;
1898			clocks = < 0x04 0x68 0x04 0x06 0x04 0x10 0x04 0x11 0x04 0xaa >;
1899			clock-names = "arm\0pll2_pfd2_396m\0step\0pll1_sw\0pll1_sys";
1900			arm-supply = < 0x68 >;
1901			pu-supply = < 0x24 >;
1902			soc-supply = < 0x69 >;
1903		};
1904
1905		cpu@1 {
1906			compatible = "arm,cortex-a9";
1907			device_type = "cpu";
1908			reg = < 0x01 >;
1909			next-level-cache = < 0x67 >;
1910			operating-points = < 0x124f80 0x137478 0xf32a0 0x1312d0 0xd0020 0x1312d0 0xc15c0 0x11edd8 0x60ae0 0xee098 >;
1911			fsl,soc-operating-points = < 0x124f80 0x137478 0xf32a0 0x1312d0 0xd0020 0x1312d0 0xc15c0 0x11edd8 0x60ae0 0x11edd8 >;
1912			clock-latency = < 0xee6c >;
1913			clocks = < 0x04 0x68 0x04 0x06 0x04 0x10 0x04 0x11 0x04 0xaa >;
1914			clock-names = "arm\0pll2_pfd2_396m\0step\0pll1_sw\0pll1_sys";
1915			arm-supply = < 0x68 >;
1916			pu-supply = < 0x24 >;
1917			soc-supply = < 0x69 >;
1918		};
1919
1920		cpu@2 {
1921			compatible = "arm,cortex-a9";
1922			device_type = "cpu";
1923			reg = < 0x02 >;
1924			next-level-cache = < 0x67 >;
1925			operating-points = < 0x124f80 0x137478 0xf32a0 0x1312d0 0xd0020 0x1312d0 0xc15c0 0x11edd8 0x60ae0 0xee098 >;
1926			fsl,soc-operating-points = < 0x124f80 0x137478 0xf32a0 0x1312d0 0xd0020 0x1312d0 0xc15c0 0x11edd8 0x60ae0 0x11edd8 >;
1927			clock-latency = < 0xee6c >;
1928			clocks = < 0x04 0x68 0x04 0x06 0x04 0x10 0x04 0x11 0x04 0xaa >;
1929			clock-names = "arm\0pll2_pfd2_396m\0step\0pll1_sw\0pll1_sys";
1930			arm-supply = < 0x68 >;
1931			pu-supply = < 0x24 >;
1932			soc-supply = < 0x69 >;
1933		};
1934
1935		cpu@3 {
1936			compatible = "arm,cortex-a9";
1937			device_type = "cpu";
1938			reg = < 0x03 >;
1939			next-level-cache = < 0x67 >;
1940			operating-points = < 0x124f80 0x137478 0xf32a0 0x1312d0 0xd0020 0x1312d0 0xc15c0 0x11edd8 0x60ae0 0xee098 >;
1941			fsl,soc-operating-points = < 0x124f80 0x137478 0xf32a0 0x1312d0 0xd0020 0x1312d0 0xc15c0 0x11edd8 0x60ae0 0x11edd8 >;
1942			clock-latency = < 0xee6c >;
1943			clocks = < 0x04 0x68 0x04 0x06 0x04 0x10 0x04 0x11 0x04 0xaa >;
1944			clock-names = "arm\0pll2_pfd2_396m\0step\0pll1_sw\0pll1_sys";
1945			arm-supply = < 0x68 >;
1946			pu-supply = < 0x24 >;
1947			soc-supply = < 0x69 >;
1948		};
1949	};
1950
1951	capture-subsystem {
1952		compatible = "fsl,imx-capture-subsystem";
1953		ports = < 0x6a 0x6b 0x6c 0x6d >;
1954	};
1955
1956	display-subsystem {
1957		compatible = "fsl,imx-display-subsystem";
1958		ports = < 0x6e 0x6f 0x70 0x71 >;
1959	};
1960
1961	memory@10000000 {
1962		reg = < 0x10000000 0x40000000 >;
1963	};
1964
1965	regulators {
1966		compatible = "simple-bus";
1967		#address-cells = < 0x01 >;
1968		#size-cells = < 0x00 >;
1969
1970		regulator@0 {
1971			compatible = "regulator-fixed";
1972			reg = < 0x00 >;
1973			regulator-name = "2P5V";
1974			regulator-min-microvolt = < 0x2625a0 >;
1975			regulator-max-microvolt = < 0x2625a0 >;
1976			regulator-always-on;
1977			phandle = < 0x39 >;
1978		};
1979
1980		regulator@1 {
1981			compatible = "regulator-fixed";
1982			reg = < 0x01 >;
1983			regulator-name = "3P3V";
1984			regulator-min-microvolt = < 0x325aa0 >;
1985			regulator-max-microvolt = < 0x325aa0 >;
1986			regulator-always-on;
1987			phandle = < 0x35 >;
1988		};
1989
1990		regulator@2 {
1991			compatible = "regulator-fixed";
1992			reg = < 0x02 >;
1993			regulator-name = "usb_otg_vbus";
1994			regulator-min-microvolt = < 0x4c4b40 >;
1995			regulator-max-microvolt = < 0x4c4b40 >;
1996			gpio = < 0x18 0x16 0x00 >;
1997			enable-active-high;
1998			phandle = < 0x2e >;
1999		};
2000
2001		regulator@3 {
2002			compatible = "regulator-fixed";
2003			reg = < 0x03 >;
2004			regulator-name = "CAN XCVR";
2005			regulator-min-microvolt = < 0x325aa0 >;
2006			regulator-max-microvolt = < 0x325aa0 >;
2007			pinctrl-names = "default";
2008			pinctrl-0 = < 0x72 >;
2009			gpio = < 0x43 0x02 0x01 >;
2010			phandle = < 0x21 >;
2011		};
2012
2013		regulator@4 {
2014			compatible = "regulator-fixed";
2015			reg = < 0x04 >;
2016			regulator-name = "1P5V";
2017			regulator-min-microvolt = < 0x16e360 >;
2018			regulator-max-microvolt = < 0x16e360 >;
2019			regulator-always-on;
2020			phandle = < 0x3f >;
2021		};
2022
2023		regulator@5 {
2024			compatible = "regulator-fixed";
2025			reg = < 0x05 >;
2026			regulator-name = "1P8V";
2027			regulator-min-microvolt = < 0x1b7740 >;
2028			regulator-max-microvolt = < 0x1b7740 >;
2029			regulator-always-on;
2030			phandle = < 0x3d >;
2031		};
2032
2033		regulator@6 {
2034			compatible = "regulator-fixed";
2035			reg = < 0x06 >;
2036			regulator-name = "2P8V";
2037			regulator-min-microvolt = < 0x2ab980 >;
2038			regulator-max-microvolt = < 0x2ab980 >;
2039			regulator-always-on;
2040			phandle = < 0x3e >;
2041		};
2042
2043		regulator@7 {
2044			compatible = "regulator-fixed";
2045			reg = < 0x07 >;
2046			pinctrl-names = "default";
2047			pinctrl-0 = < 0x73 >;
2048			regulator-name = "usb_h1_vbus";
2049			regulator-min-microvolt = < 0x325aa0 >;
2050			regulator-max-microvolt = < 0x325aa0 >;
2051			gpio = < 0x34 0x0c 0x00 >;
2052			enable-active-high;
2053			phandle = < 0x31 >;
2054		};
2055	};
2056
2057	mipi_xclk {
2058		compatible = "pwm-clock";
2059		#clock-cells = < 0x00 >;
2060		clock-frequency = < 0x14fb180 >;
2061		clock-output-names = "mipi_pwm3";
2062		pwms = < 0x74 0x00 0x2d >;
2063		status = "okay";
2064		phandle = < 0x3c >;
2065	};
2066
2067	gpio-keys {
2068		compatible = "gpio-keys";
2069		pinctrl-names = "default";
2070		pinctrl-0 = < 0x75 >;
2071
2072		power {
2073			label = "Power Button";
2074			gpios = < 0x37 0x03 0x01 >;
2075			linux,code = < 0x74 >;
2076			wakeup-source;
2077		};
2078
2079		menu {
2080			label = "Menu";
2081			gpios = < 0x37 0x01 0x01 >;
2082			linux,code = < 0x8b >;
2083		};
2084
2085		home {
2086			label = "Home";
2087			gpios = < 0x37 0x04 0x01 >;
2088			linux,code = < 0x66 >;
2089		};
2090
2091		back {
2092			label = "Back";
2093			gpios = < 0x37 0x02 0x01 >;
2094			linux,code = < 0x9e >;
2095		};
2096
2097		volume-up {
2098			label = "Volume Up";
2099			gpios = < 0x34 0x0d 0x01 >;
2100			linux,code = < 0x73 >;
2101		};
2102
2103		volume-down {
2104			label = "Volume Down";
2105			gpios = < 0x76 0x05 0x01 >;
2106			linux,code = < 0x72 >;
2107		};
2108	};
2109
2110	sound {
2111		compatible = "fsl,imx6q-sabrelite-sgtl5000\0fsl,imx-audio-sgtl5000";
2112		model = "imx6q-sabrelite-sgtl5000";
2113		ssi-controller = < 0x77 >;
2114		audio-codec = < 0x78 >;
2115		audio-routing = "MIC_IN\0Mic Jack\0Mic Jack\0Mic Bias\0Headphone Jack\0HP_OUT";
2116		mux-int-port = < 0x01 >;
2117		mux-ext-port = < 0x04 >;
2118	};
2119
2120	backlight-lcd {
2121		compatible = "pwm-backlight";
2122		pwms = < 0x79 0x00 0x4c4b40 >;
2123		brightness-levels = < 0x00 0x04 0x08 0x10 0x20 0x40 0x80 0xff >;
2124		default-brightness-level = < 0x07 >;
2125		power-supply = < 0x35 >;
2126		status = "okay";
2127		phandle = < 0x7e >;
2128	};
2129
2130	backlight-lvds {
2131		compatible = "pwm-backlight";
2132		pwms = < 0x7a 0x00 0x4c4b40 >;
2133		brightness-levels = < 0x00 0x04 0x08 0x10 0x20 0x40 0x80 0xff >;
2134		default-brightness-level = < 0x07 >;
2135		power-supply = < 0x35 >;
2136		status = "okay";
2137		phandle = < 0x80 >;
2138	};
2139
2140	disp0 {
2141		compatible = "fsl,imx-parallel-display";
2142		#address-cells = < 0x01 >;
2143		#size-cells = < 0x00 >;
2144		interface-pix-fmt = "bgr666";
2145		pinctrl-names = "default";
2146		pinctrl-0 = < 0x7b >;
2147		status = "okay";
2148
2149		port@0 {
2150			reg = < 0x00 >;
2151
2152			endpoint {
2153				remote-endpoint = < 0x7c >;
2154				phandle = < 0x54 >;
2155			};
2156		};
2157
2158		port@1 {
2159			reg = < 0x01 >;
2160
2161			endpoint {
2162				remote-endpoint = < 0x7d >;
2163				phandle = < 0x7f >;
2164			};
2165		};
2166	};
2167
2168	panel-lcd {
2169		compatible = "okaya,rs800480t-7x0gp";
2170		backlight = < 0x7e >;
2171
2172		port {
2173
2174			endpoint {
2175				remote-endpoint = < 0x7f >;
2176				phandle = < 0x7d >;
2177			};
2178		};
2179	};
2180
2181	panel-lvds0 {
2182		compatible = "hannstar,hsd100pxn1";
2183		backlight = < 0x80 >;
2184
2185		port {
2186
2187			endpoint {
2188				remote-endpoint = < 0x81 >;
2189				phandle = < 0x0a >;
2190			};
2191		};
2192	};
2193};
2194