1/*
2 * Copyright Linux Kernel Team
3 *
4 * SPDX-License-Identifier: GPL-2.0-only
5 *
6 * This file is derived from an intermediate build stage of the
7 * Linux kernel. The licenses of all input files to this process
8 * are compatible with GPL-2.0-only.
9 */
10
11/dts-v1/;
12
13/ {
14	compatible = "pine64,rockpro64\0rockchip,rk3399";
15	interrupt-parent = < 0x01 >;
16	#address-cells = < 0x02 >;
17	#size-cells = < 0x02 >;
18	model = "Pine64 RockPro64";
19
20	aliases {
21		ethernet0 = "/ethernet@fe300000";
22		i2c0 = "/i2c@ff3c0000";
23		i2c1 = "/i2c@ff110000";
24		i2c2 = "/i2c@ff120000";
25		i2c3 = "/i2c@ff130000";
26		i2c4 = "/i2c@ff3d0000";
27		i2c5 = "/i2c@ff140000";
28		i2c6 = "/i2c@ff150000";
29		i2c7 = "/i2c@ff160000";
30		i2c8 = "/i2c@ff3e0000";
31		serial0 = "/serial@ff180000";
32		serial1 = "/serial@ff190000";
33		serial2 = "/serial@ff1a0000";
34		serial3 = "/serial@ff1b0000";
35		serial4 = "/serial@ff370000";
36	};
37
38	memory@00000000 {
39		device_type = "memory";
40		reg = < 0x00 0x10000000 0x00 0xe8000000 >;
41	};
42
43	cpus {
44		#address-cells = < 0x02 >;
45		#size-cells = < 0x00 >;
46
47		cpu-map {
48
49			cluster0 {
50
51				core0 {
52					cpu = < 0x02 >;
53				};
54
55				core1 {
56					cpu = < 0x03 >;
57				};
58
59				core2 {
60					cpu = < 0x04 >;
61				};
62
63				core3 {
64					cpu = < 0x05 >;
65				};
66			};
67
68			cluster1 {
69
70				core0 {
71					cpu = < 0x06 >;
72				};
73
74				core1 {
75					cpu = < 0x07 >;
76				};
77			};
78		};
79
80		cpu@0 {
81			device_type = "cpu";
82			compatible = "arm,cortex-a53";
83			reg = < 0x00 0x00 >;
84			enable-method = "psci";
85			capacity-dmips-mhz = < 0x1e5 >;
86			clocks = < 0x08 0x08 >;
87			#cooling-cells = < 0x02 >;
88			dynamic-power-coefficient = < 0x64 >;
89			cpu-idle-states = < 0x09 0x0a >;
90			operating-points-v2 = < 0x0b >;
91			cpu-supply = < 0x0c >;
92			phandle = < 0x02 >;
93		};
94
95		cpu@1 {
96			device_type = "cpu";
97			compatible = "arm,cortex-a53";
98			reg = < 0x00 0x01 >;
99			enable-method = "psci";
100			capacity-dmips-mhz = < 0x1e5 >;
101			clocks = < 0x08 0x08 >;
102			#cooling-cells = < 0x02 >;
103			dynamic-power-coefficient = < 0x64 >;
104			cpu-idle-states = < 0x09 0x0a >;
105			operating-points-v2 = < 0x0b >;
106			cpu-supply = < 0x0c >;
107			phandle = < 0x03 >;
108		};
109
110		cpu@2 {
111			device_type = "cpu";
112			compatible = "arm,cortex-a53";
113			reg = < 0x00 0x02 >;
114			enable-method = "psci";
115			capacity-dmips-mhz = < 0x1e5 >;
116			clocks = < 0x08 0x08 >;
117			#cooling-cells = < 0x02 >;
118			dynamic-power-coefficient = < 0x64 >;
119			cpu-idle-states = < 0x09 0x0a >;
120			operating-points-v2 = < 0x0b >;
121			cpu-supply = < 0x0c >;
122			phandle = < 0x04 >;
123		};
124
125		cpu@3 {
126			device_type = "cpu";
127			compatible = "arm,cortex-a53";
128			reg = < 0x00 0x03 >;
129			enable-method = "psci";
130			capacity-dmips-mhz = < 0x1e5 >;
131			clocks = < 0x08 0x08 >;
132			#cooling-cells = < 0x02 >;
133			dynamic-power-coefficient = < 0x64 >;
134			cpu-idle-states = < 0x09 0x0a >;
135			operating-points-v2 = < 0x0b >;
136			cpu-supply = < 0x0c >;
137			phandle = < 0x05 >;
138		};
139
140		cpu@100 {
141			device_type = "cpu";
142			compatible = "arm,cortex-a72";
143			reg = < 0x00 0x100 >;
144			enable-method = "psci";
145			capacity-dmips-mhz = < 0x400 >;
146			clocks = < 0x08 0x09 >;
147			#cooling-cells = < 0x02 >;
148			dynamic-power-coefficient = < 0x1b4 >;
149			cpu-idle-states = < 0x09 0x0a >;
150			operating-points-v2 = < 0x0d >;
151			cpu-supply = < 0x0e >;
152			phandle = < 0x06 >;
153		};
154
155		cpu@101 {
156			device_type = "cpu";
157			compatible = "arm,cortex-a72";
158			reg = < 0x00 0x101 >;
159			enable-method = "psci";
160			capacity-dmips-mhz = < 0x400 >;
161			clocks = < 0x08 0x09 >;
162			#cooling-cells = < 0x02 >;
163			dynamic-power-coefficient = < 0x1b4 >;
164			cpu-idle-states = < 0x09 0x0a >;
165			operating-points-v2 = < 0x0d >;
166			cpu-supply = < 0x0e >;
167			phandle = < 0x07 >;
168		};
169
170		idle-states {
171			entry-method = "psci";
172
173			cpu-sleep {
174				compatible = "arm,idle-state";
175				local-timer-stop;
176				arm,psci-suspend-param = < 0x10000 >;
177				entry-latency-us = < 0x78 >;
178				exit-latency-us = < 0xfa >;
179				min-residency-us = < 0x384 >;
180				phandle = < 0x09 >;
181			};
182
183			cluster-sleep {
184				compatible = "arm,idle-state";
185				local-timer-stop;
186				arm,psci-suspend-param = < 0x1010000 >;
187				entry-latency-us = < 0x190 >;
188				exit-latency-us = < 0x1f4 >;
189				min-residency-us = < 0x7d0 >;
190				phandle = < 0x0a >;
191			};
192		};
193	};
194
195	display-subsystem {
196		compatible = "rockchip,display-subsystem";
197		ports = < 0x0f 0x10 >;
198	};
199
200	pmu_a53 {
201		compatible = "arm,cortex-a53-pmu";
202		interrupts = < 0x01 0x07 0x08 0x11 >;
203	};
204
205	pmu_a72 {
206		compatible = "arm,cortex-a72-pmu";
207		interrupts = < 0x01 0x07 0x08 0x12 >;
208	};
209
210	psci {
211		compatible = "arm,psci-1.0";
212		method = "smc";
213	};
214
215	timer {
216		compatible = "arm,armv8-timer";
217		interrupts = < 0x01 0x0d 0x08 0x00 0x01 0x0e 0x08 0x00 0x01 0x0b 0x08 0x00 0x01 0x0a 0x08 0x00 >;
218		arm,no-tick-in-suspend;
219	};
220
221	xin24m {
222		compatible = "fixed-clock";
223		clock-frequency = < 0x16e3600 >;
224		clock-output-names = "xin24m";
225		#clock-cells = < 0x00 >;
226	};
227
228	amba {
229		compatible = "simple-bus";
230		#address-cells = < 0x02 >;
231		#size-cells = < 0x02 >;
232		ranges;
233
234		dma-controller@ff6d0000 {
235			compatible = "arm,pl330\0arm,primecell";
236			reg = < 0x00 0xff6d0000 0x00 0x4000 >;
237			interrupts = < 0x00 0x05 0x04 0x00 0x00 0x06 0x04 0x00 >;
238			#dma-cells = < 0x01 >;
239			clocks = < 0x08 0xd3 >;
240			clock-names = "apb_pclk";
241			phandle = < 0x4a >;
242		};
243
244		dma-controller@ff6e0000 {
245			compatible = "arm,pl330\0arm,primecell";
246			reg = < 0x00 0xff6e0000 0x00 0x4000 >;
247			interrupts = < 0x00 0x07 0x04 0x00 0x00 0x08 0x04 0x00 >;
248			#dma-cells = < 0x01 >;
249			clocks = < 0x08 0xd4 >;
250			clock-names = "apb_pclk";
251			phandle = < 0x39 >;
252		};
253	};
254
255	pcie@f8000000 {
256		compatible = "rockchip,rk3399-pcie";
257		reg = < 0x00 0xf8000000 0x00 0x2000000 0x00 0xfd000000 0x00 0x1000000 >;
258		reg-names = "axi-base\0apb-base";
259		#address-cells = < 0x03 >;
260		#size-cells = < 0x02 >;
261		#interrupt-cells = < 0x01 >;
262		aspm-no-l0s;
263		bus-range = < 0x00 0x1f >;
264		clocks = < 0x08 0xc5 0x08 0xc4 0x08 0x147 0x08 0xa0 >;
265		clock-names = "aclk\0aclk-perf\0hclk\0pm";
266		interrupts = < 0x00 0x31 0x04 0x00 0x00 0x32 0x04 0x00 0x00 0x33 0x04 0x00 >;
267		interrupt-names = "sys\0legacy\0client";
268		interrupt-map-mask = < 0x00 0x00 0x00 0x07 >;
269		interrupt-map = < 0x00 0x00 0x00 0x01 0x13 0x00 0x00 0x00 0x00 0x02 0x13 0x01 0x00 0x00 0x00 0x03 0x13 0x02 0x00 0x00 0x00 0x04 0x13 0x03 >;
270		linux,pci-domain = < 0x00 >;
271		max-link-speed = < 0x01 >;
272		msi-map = < 0x00 0x14 0x00 0x1000 >;
273		phys = < 0x15 0x00 0x15 0x01 0x15 0x02 0x15 0x03 >;
274		phy-names = "pcie-phy-0\0pcie-phy-1\0pcie-phy-2\0pcie-phy-3";
275		ranges = < 0x83000000 0x00 0xfa000000 0x00 0xfa000000 0x00 0x1e00000 0x81000000 0x00 0xfbe00000 0x00 0xfbe00000 0x00 0x100000 >;
276		resets = < 0x08 0x82 0x08 0x83 0x08 0x84 0x08 0x85 0x08 0x86 0x08 0x81 0x08 0x80 >;
277		reset-names = "core\0mgmt\0mgmt-sticky\0pipe\0pm\0pclk\0aclk";
278		status = "disabled";
279
280		interrupt-controller {
281			interrupt-controller;
282			#address-cells = < 0x00 >;
283			#interrupt-cells = < 0x01 >;
284			phandle = < 0x13 >;
285		};
286	};
287
288	ethernet@fe300000 {
289		compatible = "rockchip,rk3399-gmac";
290		reg = < 0x00 0xfe300000 0x00 0x10000 >;
291		interrupts = < 0x00 0x0c 0x04 0x00 >;
292		interrupt-names = "macirq";
293		clocks = < 0x08 0x69 0x08 0x67 0x08 0x68 0x08 0x66 0x08 0x6a 0x08 0xd5 0x08 0x166 >;
294		clock-names = "stmmaceth\0mac_clk_rx\0mac_clk_tx\0clk_mac_ref\0clk_mac_refout\0aclk_mac\0pclk_mac";
295		power-domains = < 0x16 0x16 >;
296		resets = < 0x08 0x89 >;
297		reset-names = "stmmaceth";
298		rockchip,grf = < 0x17 >;
299		status = "okay";
300		assigned-clocks = < 0x08 0xa6 >;
301		assigned-clock-parents = < 0x18 >;
302		clock_in_out = "input";
303		phy-supply = < 0x19 >;
304		phy-mode = "rgmii";
305		pinctrl-names = "default";
306		pinctrl-0 = < 0x1a >;
307		snps,reset-gpio = < 0x1b 0x0f 0x01 >;
308		snps,reset-active-low;
309		snps,reset-delays-us = < 0x00 0x2710 0xc350 >;
310		tx_delay = < 0x28 >;
311		rx_delay = < 0x11 >;
312	};
313
314	dwmmc@fe310000 {
315		compatible = "rockchip,rk3399-dw-mshc\0rockchip,rk3288-dw-mshc";
316		reg = < 0x00 0xfe310000 0x00 0x4000 >;
317		interrupts = < 0x00 0x40 0x04 0x00 >;
318		max-frequency = < 0x8f0d180 >;
319		clocks = < 0x08 0x1ee 0x08 0x4d 0x08 0x9c 0x08 0x9d >;
320		clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
321		fifo-depth = < 0x100 >;
322		power-domains = < 0x16 0x1c >;
323		resets = < 0x08 0x79 >;
324		reset-names = "reset";
325		status = "disabled";
326	};
327
328	dwmmc@fe320000 {
329		compatible = "rockchip,rk3399-dw-mshc\0rockchip,rk3288-dw-mshc";
330		reg = < 0x00 0xfe320000 0x00 0x4000 >;
331		interrupts = < 0x00 0x41 0x04 0x00 >;
332		max-frequency = < 0x8f0d180 >;
333		assigned-clocks = < 0x08 0x1cd >;
334		assigned-clock-rates = < 0xbebc200 >;
335		clocks = < 0x08 0x1ce 0x08 0x4c 0x08 0x9a 0x08 0x9b >;
336		clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
337		fifo-depth = < 0x100 >;
338		power-domains = < 0x16 0x1b >;
339		resets = < 0x08 0x7a >;
340		reset-names = "reset";
341		status = "okay";
342		bus-width = < 0x04 >;
343		cap-mmc-highspeed;
344		cap-sd-highspeed;
345		cd-gpios = < 0x1c 0x07 0x01 >;
346		disable-wp;
347		pinctrl-names = "default";
348		pinctrl-0 = < 0x1d 0x1e 0x1f >;
349	};
350
351	sdhci@fe330000 {
352		compatible = "rockchip,rk3399-sdhci-5.1\0arasan,sdhci-5.1";
353		reg = < 0x00 0xfe330000 0x00 0x10000 >;
354		interrupts = < 0x00 0x0b 0x04 0x00 >;
355		arasan,soc-ctl-syscon = < 0x17 >;
356		assigned-clocks = < 0x08 0x4e >;
357		assigned-clock-rates = < 0xbebc200 >;
358		clocks = < 0x08 0x4e 0x08 0xf0 >;
359		clock-names = "clk_xin\0clk_ahb";
360		clock-output-names = "emmc_cardclock";
361		#clock-cells = < 0x00 >;
362		phys = < 0x20 >;
363		phy-names = "phy_arasan";
364		power-domains = < 0x16 0x17 >;
365		disable-cqe-dcmd;
366		status = "okay";
367		bus-width = < 0x08 >;
368		mmc-hs400-1_8v;
369		mmc-hs400-enhanced-strobe;
370		non-removable;
371		phandle = < 0x86 >;
372	};
373
374	usb@fe380000 {
375		compatible = "generic-ehci";
376		reg = < 0x00 0xfe380000 0x00 0x20000 >;
377		interrupts = < 0x00 0x1a 0x04 0x00 >;
378		clocks = < 0x08 0x1c8 0x08 0x1c9 0x21 >;
379		clock-names = "usbhost\0arbiter\0utmi";
380		phys = < 0x22 >;
381		phy-names = "usb";
382		status = "okay";
383	};
384
385	usb@fe3a0000 {
386		compatible = "generic-ohci";
387		reg = < 0x00 0xfe3a0000 0x00 0x20000 >;
388		interrupts = < 0x00 0x1c 0x04 0x00 >;
389		clocks = < 0x08 0x1c8 0x08 0x1c9 0x21 >;
390		clock-names = "usbhost\0arbiter\0utmi";
391		phys = < 0x22 >;
392		phy-names = "usb";
393		status = "okay";
394	};
395
396	usb@fe3c0000 {
397		compatible = "generic-ehci";
398		reg = < 0x00 0xfe3c0000 0x00 0x20000 >;
399		interrupts = < 0x00 0x1e 0x04 0x00 >;
400		clocks = < 0x08 0x1ca 0x08 0x1cb 0x23 >;
401		clock-names = "usbhost\0arbiter\0utmi";
402		phys = < 0x24 >;
403		phy-names = "usb";
404		status = "okay";
405	};
406
407	usb@fe3e0000 {
408		compatible = "generic-ohci";
409		reg = < 0x00 0xfe3e0000 0x00 0x20000 >;
410		interrupts = < 0x00 0x20 0x04 0x00 >;
411		clocks = < 0x08 0x1ca 0x08 0x1cb 0x23 >;
412		clock-names = "usbhost\0arbiter\0utmi";
413		phys = < 0x24 >;
414		phy-names = "usb";
415		status = "okay";
416	};
417
418	usb@fe800000 {
419		compatible = "rockchip,rk3399-dwc3";
420		#address-cells = < 0x02 >;
421		#size-cells = < 0x02 >;
422		ranges;
423		clocks = < 0x08 0x81 0x08 0x83 0x08 0xf6 0x08 0xf8 0x08 0xf4 0x08 0xf9 >;
424		clock-names = "ref_clk\0suspend_clk\0bus_clk\0aclk_usb3_rksoc_axi_perf\0aclk_usb3\0grf_clk";
425		resets = < 0x08 0x125 >;
426		reset-names = "usb3-otg";
427		status = "okay";
428
429		dwc3 {
430			compatible = "snps,dwc3";
431			reg = < 0x00 0xfe800000 0x00 0x100000 >;
432			interrupts = < 0x00 0x69 0x04 0x00 >;
433			dr_mode = "otg";
434			phys = < 0x25 0x26 >;
435			phy-names = "usb2-phy\0usb3-phy";
436			phy_type = "utmi_wide";
437			snps,dis_enblslpm_quirk;
438			snps,dis-u2-freeclk-exists-quirk;
439			snps,dis_u2_susphy_quirk;
440			snps,dis-del-phy-power-chg-quirk;
441			snps,dis-tx-ipgap-linecheck-quirk;
442			power-domains = < 0x16 0x18 >;
443			status = "okay";
444		};
445	};
446
447	usb@fe900000 {
448		compatible = "rockchip,rk3399-dwc3";
449		#address-cells = < 0x02 >;
450		#size-cells = < 0x02 >;
451		ranges;
452		clocks = < 0x08 0x82 0x08 0x84 0x08 0xf7 0x08 0xf8 0x08 0xf4 0x08 0xf9 >;
453		clock-names = "ref_clk\0suspend_clk\0bus_clk\0aclk_usb3_rksoc_axi_perf\0aclk_usb3\0grf_clk";
454		resets = < 0x08 0x126 >;
455		reset-names = "usb3-otg";
456		status = "okay";
457
458		dwc3 {
459			compatible = "snps,dwc3";
460			reg = < 0x00 0xfe900000 0x00 0x100000 >;
461			interrupts = < 0x00 0x6e 0x04 0x00 >;
462			dr_mode = "host";
463			phys = < 0x27 0x28 >;
464			phy-names = "usb2-phy\0usb3-phy";
465			phy_type = "utmi_wide";
466			snps,dis_enblslpm_quirk;
467			snps,dis-u2-freeclk-exists-quirk;
468			snps,dis_u2_susphy_quirk;
469			snps,dis-del-phy-power-chg-quirk;
470			snps,dis-tx-ipgap-linecheck-quirk;
471			power-domains = < 0x16 0x18 >;
472			status = "okay";
473		};
474	};
475
476	dp@fec00000 {
477		compatible = "rockchip,rk3399-cdn-dp";
478		reg = < 0x00 0xfec00000 0x00 0x100000 >;
479		interrupts = < 0x00 0x09 0x04 0x00 >;
480		assigned-clocks = < 0x08 0x72 0x08 0xa1 >;
481		assigned-clock-rates = < 0x5f5e100 0xbebc200 >;
482		clocks = < 0x08 0x72 0x08 0x175 0x08 0xa1 0x08 0x16f >;
483		clock-names = "core-clk\0pclk\0spdif\0grf";
484		phys = < 0x29 0x2a >;
485		power-domains = < 0x16 0x15 >;
486		resets = < 0x08 0x103 0x08 0x148 0x08 0x14a 0x08 0xfd >;
487		reset-names = "spdif\0dptx\0apb\0core";
488		rockchip,grf = < 0x17 >;
489		#sound-dai-cells = < 0x01 >;
490		status = "disabled";
491
492		ports {
493
494			port {
495				#address-cells = < 0x01 >;
496				#size-cells = < 0x00 >;
497
498				endpoint@0 {
499					reg = < 0x00 >;
500					remote-endpoint = < 0x2b >;
501					phandle = < 0x95 >;
502				};
503
504				endpoint@1 {
505					reg = < 0x01 >;
506					remote-endpoint = < 0x2c >;
507					phandle = < 0x8f >;
508				};
509			};
510		};
511	};
512
513	interrupt-controller@fee00000 {
514		compatible = "arm,gic-v3";
515		#interrupt-cells = < 0x04 >;
516		#address-cells = < 0x02 >;
517		#size-cells = < 0x02 >;
518		ranges;
519		interrupt-controller;
520		reg = < 0x00 0xfee00000 0x00 0x10000 0x00 0xfef00000 0x00 0xc0000 0x00 0xfff00000 0x00 0x10000 0x00 0xfff10000 0x00 0x10000 0x00 0xfff20000 0x00 0x10000 >;
521		interrupts = < 0x01 0x09 0x04 0x00 >;
522		phandle = < 0x01 >;
523
524		interrupt-controller@fee20000 {
525			compatible = "arm,gic-v3-its";
526			msi-controller;
527			reg = < 0x00 0xfee20000 0x00 0x20000 >;
528			phandle = < 0x14 >;
529		};
530
531		ppi-partitions {
532
533			interrupt-partition-0 {
534				affinity = < 0x02 0x03 0x04 0x05 >;
535				phandle = < 0x11 >;
536			};
537
538			interrupt-partition-1 {
539				affinity = < 0x06 0x07 >;
540				phandle = < 0x12 >;
541			};
542		};
543	};
544
545	saradc@ff100000 {
546		compatible = "rockchip,rk3399-saradc";
547		reg = < 0x00 0xff100000 0x00 0x100 >;
548		interrupts = < 0x00 0x3e 0x04 0x00 >;
549		#io-channel-cells = < 0x01 >;
550		clocks = < 0x08 0x50 0x08 0x165 >;
551		clock-names = "saradc\0apb_pclk";
552		resets = < 0x08 0xd4 >;
553		reset-names = "saradc-apb";
554		status = "okay";
555		vref-supply = < 0x2d >;
556	};
557
558	i2c@ff110000 {
559		compatible = "rockchip,rk3399-i2c";
560		reg = < 0x00 0xff110000 0x00 0x1000 >;
561		assigned-clocks = < 0x08 0x41 >;
562		assigned-clock-rates = < 0xbebc200 >;
563		clocks = < 0x08 0x41 0x08 0x155 >;
564		clock-names = "i2c\0pclk";
565		interrupts = < 0x00 0x3b 0x04 0x00 >;
566		pinctrl-names = "default";
567		pinctrl-0 = < 0x2e >;
568		#address-cells = < 0x01 >;
569		#size-cells = < 0x00 >;
570		status = "okay";
571		i2c-scl-rising-time-ns = < 0x12c >;
572		i2c-scl-falling-time-ns = < 0x0f >;
573	};
574
575	i2c@ff120000 {
576		compatible = "rockchip,rk3399-i2c";
577		reg = < 0x00 0xff120000 0x00 0x1000 >;
578		assigned-clocks = < 0x08 0x42 >;
579		assigned-clock-rates = < 0xbebc200 >;
580		clocks = < 0x08 0x42 0x08 0x156 >;
581		clock-names = "i2c\0pclk";
582		interrupts = < 0x00 0x23 0x04 0x00 >;
583		pinctrl-names = "default";
584		pinctrl-0 = < 0x2f >;
585		#address-cells = < 0x01 >;
586		#size-cells = < 0x00 >;
587		status = "disabled";
588	};
589
590	i2c@ff130000 {
591		compatible = "rockchip,rk3399-i2c";
592		reg = < 0x00 0xff130000 0x00 0x1000 >;
593		assigned-clocks = < 0x08 0x43 >;
594		assigned-clock-rates = < 0xbebc200 >;
595		clocks = < 0x08 0x43 0x08 0x157 >;
596		clock-names = "i2c\0pclk";
597		interrupts = < 0x00 0x22 0x04 0x00 >;
598		pinctrl-names = "default";
599		pinctrl-0 = < 0x30 >;
600		#address-cells = < 0x01 >;
601		#size-cells = < 0x00 >;
602		status = "okay";
603		i2c-scl-rising-time-ns = < 0x1c2 >;
604		i2c-scl-falling-time-ns = < 0x0f >;
605		phandle = < 0x98 >;
606	};
607
608	i2c@ff140000 {
609		compatible = "rockchip,rk3399-i2c";
610		reg = < 0x00 0xff140000 0x00 0x1000 >;
611		assigned-clocks = < 0x08 0x44 >;
612		assigned-clock-rates = < 0xbebc200 >;
613		clocks = < 0x08 0x44 0x08 0x158 >;
614		clock-names = "i2c\0pclk";
615		interrupts = < 0x00 0x26 0x04 0x00 >;
616		pinctrl-names = "default";
617		pinctrl-0 = < 0x31 >;
618		#address-cells = < 0x01 >;
619		#size-cells = < 0x00 >;
620		status = "disabled";
621	};
622
623	i2c@ff150000 {
624		compatible = "rockchip,rk3399-i2c";
625		reg = < 0x00 0xff150000 0x00 0x1000 >;
626		assigned-clocks = < 0x08 0x45 >;
627		assigned-clock-rates = < 0xbebc200 >;
628		clocks = < 0x08 0x45 0x08 0x159 >;
629		clock-names = "i2c\0pclk";
630		interrupts = < 0x00 0x25 0x04 0x00 >;
631		pinctrl-names = "default";
632		pinctrl-0 = < 0x32 >;
633		#address-cells = < 0x01 >;
634		#size-cells = < 0x00 >;
635		status = "disabled";
636	};
637
638	i2c@ff160000 {
639		compatible = "rockchip,rk3399-i2c";
640		reg = < 0x00 0xff160000 0x00 0x1000 >;
641		assigned-clocks = < 0x08 0x46 >;
642		assigned-clock-rates = < 0xbebc200 >;
643		clocks = < 0x08 0x46 0x08 0x15a >;
644		clock-names = "i2c\0pclk";
645		interrupts = < 0x00 0x24 0x04 0x00 >;
646		pinctrl-names = "default";
647		pinctrl-0 = < 0x33 >;
648		#address-cells = < 0x01 >;
649		#size-cells = < 0x00 >;
650		status = "disabled";
651	};
652
653	serial@ff180000 {
654		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
655		reg = < 0x00 0xff180000 0x00 0x100 >;
656		clocks = < 0x08 0x51 0x08 0x160 >;
657		clock-names = "baudclk\0apb_pclk";
658		interrupts = < 0x00 0x63 0x04 0x00 >;
659		reg-shift = < 0x02 >;
660		reg-io-width = < 0x04 >;
661		pinctrl-names = "default";
662		pinctrl-0 = < 0x34 0x35 >;
663		status = "okay";
664	};
665
666	serial@ff190000 {
667		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
668		reg = < 0x00 0xff190000 0x00 0x100 >;
669		clocks = < 0x08 0x52 0x08 0x161 >;
670		clock-names = "baudclk\0apb_pclk";
671		interrupts = < 0x00 0x62 0x04 0x00 >;
672		reg-shift = < 0x02 >;
673		reg-io-width = < 0x04 >;
674		pinctrl-names = "default";
675		pinctrl-0 = < 0x36 >;
676		status = "disabled";
677	};
678
679	serial@ff1a0000 {
680		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
681		reg = < 0x00 0xff1a0000 0x00 0x100 >;
682		clocks = < 0x08 0x53 0x08 0x162 >;
683		clock-names = "baudclk\0apb_pclk";
684		interrupts = < 0x00 0x64 0x04 0x00 >;
685		reg-shift = < 0x02 >;
686		reg-io-width = < 0x04 >;
687		pinctrl-names = "default";
688		pinctrl-0 = < 0x37 >;
689		status = "okay";
690	};
691
692	serial@ff1b0000 {
693		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
694		reg = < 0x00 0xff1b0000 0x00 0x100 >;
695		clocks = < 0x08 0x54 0x08 0x163 >;
696		clock-names = "baudclk\0apb_pclk";
697		interrupts = < 0x00 0x65 0x04 0x00 >;
698		reg-shift = < 0x02 >;
699		reg-io-width = < 0x04 >;
700		pinctrl-names = "default";
701		pinctrl-0 = < 0x38 >;
702		status = "disabled";
703	};
704
705	spi@ff1c0000 {
706		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
707		reg = < 0x00 0xff1c0000 0x00 0x1000 >;
708		clocks = < 0x08 0x47 0x08 0x15b >;
709		clock-names = "spiclk\0apb_pclk";
710		interrupts = < 0x00 0x44 0x04 0x00 >;
711		dmas = < 0x39 0x0a 0x39 0x0b >;
712		dma-names = "tx\0rx";
713		pinctrl-names = "default";
714		pinctrl-0 = < 0x3a 0x3b 0x3c 0x3d >;
715		#address-cells = < 0x01 >;
716		#size-cells = < 0x00 >;
717		status = "disabled";
718	};
719
720	spi@ff1d0000 {
721		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
722		reg = < 0x00 0xff1d0000 0x00 0x1000 >;
723		clocks = < 0x08 0x48 0x08 0x15c >;
724		clock-names = "spiclk\0apb_pclk";
725		interrupts = < 0x00 0x35 0x04 0x00 >;
726		dmas = < 0x39 0x0c 0x39 0x0d >;
727		dma-names = "tx\0rx";
728		pinctrl-names = "default";
729		pinctrl-0 = < 0x3e 0x3f 0x40 0x41 >;
730		#address-cells = < 0x01 >;
731		#size-cells = < 0x00 >;
732		status = "disabled";
733	};
734
735	spi@ff1e0000 {
736		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
737		reg = < 0x00 0xff1e0000 0x00 0x1000 >;
738		clocks = < 0x08 0x49 0x08 0x15d >;
739		clock-names = "spiclk\0apb_pclk";
740		interrupts = < 0x00 0x34 0x04 0x00 >;
741		dmas = < 0x39 0x0e 0x39 0x0f >;
742		dma-names = "tx\0rx";
743		pinctrl-names = "default";
744		pinctrl-0 = < 0x42 0x43 0x44 0x45 >;
745		#address-cells = < 0x01 >;
746		#size-cells = < 0x00 >;
747		status = "disabled";
748	};
749
750	spi@ff1f0000 {
751		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
752		reg = < 0x00 0xff1f0000 0x00 0x1000 >;
753		clocks = < 0x08 0x4a 0x08 0x15e >;
754		clock-names = "spiclk\0apb_pclk";
755		interrupts = < 0x00 0x43 0x04 0x00 >;
756		dmas = < 0x39 0x12 0x39 0x13 >;
757		dma-names = "tx\0rx";
758		pinctrl-names = "default";
759		pinctrl-0 = < 0x46 0x47 0x48 0x49 >;
760		#address-cells = < 0x01 >;
761		#size-cells = < 0x00 >;
762		status = "disabled";
763	};
764
765	spi@ff200000 {
766		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
767		reg = < 0x00 0xff200000 0x00 0x1000 >;
768		clocks = < 0x08 0x4b 0x08 0x15f >;
769		clock-names = "spiclk\0apb_pclk";
770		interrupts = < 0x00 0x84 0x04 0x00 >;
771		dmas = < 0x4a 0x08 0x4a 0x09 >;
772		dma-names = "tx\0rx";
773		pinctrl-names = "default";
774		pinctrl-0 = < 0x4b 0x4c 0x4d 0x4e >;
775		power-domains = < 0x16 0x1c >;
776		#address-cells = < 0x01 >;
777		#size-cells = < 0x00 >;
778		status = "disabled";
779	};
780
781	thermal-zones {
782
783		cpu {
784			polling-delay-passive = < 0x64 >;
785			polling-delay = < 0x3e8 >;
786			thermal-sensors = < 0x4f 0x00 >;
787
788			trips {
789
790				cpu_alert0 {
791					temperature = < 0x11170 >;
792					hysteresis = < 0x7d0 >;
793					type = "passive";
794					phandle = < 0x50 >;
795				};
796
797				cpu_alert1 {
798					temperature = < 0x124f8 >;
799					hysteresis = < 0x7d0 >;
800					type = "passive";
801					phandle = < 0x51 >;
802				};
803
804				cpu_crit {
805					temperature = < 0x17318 >;
806					hysteresis = < 0x7d0 >;
807					type = "critical";
808				};
809			};
810
811			cooling-maps {
812
813				map0 {
814					trip = < 0x50 >;
815					cooling-device = < 0x06 0xffffffff 0xffffffff 0x07 0xffffffff 0xffffffff >;
816				};
817
818				map1 {
819					trip = < 0x51 >;
820					cooling-device = < 0x02 0xffffffff 0xffffffff 0x03 0xffffffff 0xffffffff 0x04 0xffffffff 0xffffffff 0x05 0xffffffff 0xffffffff 0x06 0xffffffff 0xffffffff 0x07 0xffffffff 0xffffffff >;
821				};
822			};
823		};
824
825		gpu {
826			polling-delay-passive = < 0x64 >;
827			polling-delay = < 0x3e8 >;
828			thermal-sensors = < 0x4f 0x01 >;
829
830			trips {
831
832				gpu_alert0 {
833					temperature = < 0x124f8 >;
834					hysteresis = < 0x7d0 >;
835					type = "passive";
836					phandle = < 0x52 >;
837				};
838
839				gpu_crit {
840					temperature = < 0x17318 >;
841					hysteresis = < 0x7d0 >;
842					type = "critical";
843				};
844			};
845
846			cooling-maps {
847
848				map0 {
849					trip = < 0x52 >;
850					cooling-device = < 0x06 0xffffffff 0xffffffff 0x07 0xffffffff 0xffffffff >;
851				};
852			};
853		};
854	};
855
856	tsadc@ff260000 {
857		compatible = "rockchip,rk3399-tsadc";
858		reg = < 0x00 0xff260000 0x00 0x100 >;
859		interrupts = < 0x00 0x61 0x04 0x00 >;
860		assigned-clocks = < 0x08 0x4f >;
861		assigned-clock-rates = < 0xb71b0 >;
862		clocks = < 0x08 0x4f 0x08 0x164 >;
863		clock-names = "tsadc\0apb_pclk";
864		resets = < 0x08 0xe8 >;
865		reset-names = "tsadc-apb";
866		rockchip,grf = < 0x17 >;
867		rockchip,hw-tshut-temp = < 0x17318 >;
868		pinctrl-names = "init\0default\0sleep";
869		pinctrl-0 = < 0x53 >;
870		pinctrl-1 = < 0x54 >;
871		pinctrl-2 = < 0x53 >;
872		#thermal-sensor-cells = < 0x01 >;
873		status = "okay";
874		rockchip,hw-tshut-mode = < 0x01 >;
875		rockchip,hw-tshut-polarity = < 0x01 >;
876		phandle = < 0x4f >;
877	};
878
879	qos@ffa58000 {
880		compatible = "syscon";
881		reg = < 0x00 0xffa58000 0x00 0x20 >;
882		phandle = < 0x5c >;
883	};
884
885	qos@ffa5c000 {
886		compatible = "syscon";
887		reg = < 0x00 0xffa5c000 0x00 0x20 >;
888		phandle = < 0x5d >;
889	};
890
891	qos@ffa60080 {
892		compatible = "syscon";
893		reg = < 0x00 0xffa60080 0x00 0x20 >;
894	};
895
896	qos@ffa60100 {
897		compatible = "syscon";
898		reg = < 0x00 0xffa60100 0x00 0x20 >;
899	};
900
901	qos@ffa60180 {
902		compatible = "syscon";
903		reg = < 0x00 0xffa60180 0x00 0x20 >;
904	};
905
906	qos@ffa70000 {
907		compatible = "syscon";
908		reg = < 0x00 0xffa70000 0x00 0x20 >;
909		phandle = < 0x60 >;
910	};
911
912	qos@ffa70080 {
913		compatible = "syscon";
914		reg = < 0x00 0xffa70080 0x00 0x20 >;
915		phandle = < 0x61 >;
916	};
917
918	qos@ffa74000 {
919		compatible = "syscon";
920		reg = < 0x00 0xffa74000 0x00 0x20 >;
921		phandle = < 0x5e >;
922	};
923
924	qos@ffa76000 {
925		compatible = "syscon";
926		reg = < 0x00 0xffa76000 0x00 0x20 >;
927		phandle = < 0x5f >;
928	};
929
930	qos@ffa90000 {
931		compatible = "syscon";
932		reg = < 0x00 0xffa90000 0x00 0x20 >;
933		phandle = < 0x62 >;
934	};
935
936	qos@ffa98000 {
937		compatible = "syscon";
938		reg = < 0x00 0xffa98000 0x00 0x20 >;
939		phandle = < 0x55 >;
940	};
941
942	qos@ffaa0000 {
943		compatible = "syscon";
944		reg = < 0x00 0xffaa0000 0x00 0x20 >;
945		phandle = < 0x63 >;
946	};
947
948	qos@ffaa0080 {
949		compatible = "syscon";
950		reg = < 0x00 0xffaa0080 0x00 0x20 >;
951		phandle = < 0x64 >;
952	};
953
954	qos@ffaa8000 {
955		compatible = "syscon";
956		reg = < 0x00 0xffaa8000 0x00 0x20 >;
957		phandle = < 0x65 >;
958	};
959
960	qos@ffaa8080 {
961		compatible = "syscon";
962		reg = < 0x00 0xffaa8080 0x00 0x20 >;
963		phandle = < 0x66 >;
964	};
965
966	qos@ffab0000 {
967		compatible = "syscon";
968		reg = < 0x00 0xffab0000 0x00 0x20 >;
969		phandle = < 0x56 >;
970	};
971
972	qos@ffab0080 {
973		compatible = "syscon";
974		reg = < 0x00 0xffab0080 0x00 0x20 >;
975		phandle = < 0x57 >;
976	};
977
978	qos@ffab8000 {
979		compatible = "syscon";
980		reg = < 0x00 0xffab8000 0x00 0x20 >;
981		phandle = < 0x58 >;
982	};
983
984	qos@ffac0000 {
985		compatible = "syscon";
986		reg = < 0x00 0xffac0000 0x00 0x20 >;
987		phandle = < 0x59 >;
988	};
989
990	qos@ffac0080 {
991		compatible = "syscon";
992		reg = < 0x00 0xffac0080 0x00 0x20 >;
993		phandle = < 0x5a >;
994	};
995
996	qos@ffac8000 {
997		compatible = "syscon";
998		reg = < 0x00 0xffac8000 0x00 0x20 >;
999		phandle = < 0x67 >;
1000	};
1001
1002	qos@ffac8080 {
1003		compatible = "syscon";
1004		reg = < 0x00 0xffac8080 0x00 0x20 >;
1005		phandle = < 0x68 >;
1006	};
1007
1008	qos@ffad0000 {
1009		compatible = "syscon";
1010		reg = < 0x00 0xffad0000 0x00 0x20 >;
1011		phandle = < 0x69 >;
1012	};
1013
1014	qos@ffad8080 {
1015		compatible = "syscon";
1016		reg = < 0x00 0xffad8080 0x00 0x20 >;
1017	};
1018
1019	qos@ffae0000 {
1020		compatible = "syscon";
1021		reg = < 0x00 0xffae0000 0x00 0x20 >;
1022		phandle = < 0x5b >;
1023	};
1024
1025	power-management@ff310000 {
1026		compatible = "rockchip,rk3399-pmu\0syscon\0simple-mfd";
1027		reg = < 0x00 0xff310000 0x00 0x1000 >;
1028
1029		power-controller {
1030			compatible = "rockchip,rk3399-power-controller";
1031			#power-domain-cells = < 0x01 >;
1032			#address-cells = < 0x01 >;
1033			#size-cells = < 0x00 >;
1034			phandle = < 0x16 >;
1035
1036			pd_iep@34 {
1037				reg = < 0x22 >;
1038				clocks = < 0x08 0xe1 0x08 0x1dd >;
1039				pm_qos = < 0x55 >;
1040			};
1041
1042			pd_rga@33 {
1043				reg = < 0x21 >;
1044				clocks = < 0x08 0xdc 0x08 0x1e5 >;
1045				pm_qos = < 0x56 0x57 >;
1046			};
1047
1048			pd_vcodec@31 {
1049				reg = < 0x1f >;
1050				clocks = < 0x08 0xeb 0x08 0x1ea >;
1051				pm_qos = < 0x58 >;
1052			};
1053
1054			pd_vdu@32 {
1055				reg = < 0x20 >;
1056				clocks = < 0x08 0xed 0x08 0x1ec >;
1057				pm_qos = < 0x59 0x5a >;
1058			};
1059
1060			pd_gpu@35 {
1061				reg = < 0x23 >;
1062				clocks = < 0x08 0xd0 >;
1063				pm_qos = < 0x5b >;
1064			};
1065
1066			pd_edp@25 {
1067				reg = < 0x19 >;
1068				clocks = < 0x08 0x16c >;
1069			};
1070
1071			pd_emmc@23 {
1072				reg = < 0x17 >;
1073				clocks = < 0x08 0xf0 >;
1074				pm_qos = < 0x5c >;
1075			};
1076
1077			pd_gmac@22 {
1078				reg = < 0x16 >;
1079				clocks = < 0x08 0xd5 0x08 0x166 >;
1080				pm_qos = < 0x5d >;
1081			};
1082
1083			pd_sd@27 {
1084				reg = < 0x1b >;
1085				clocks = < 0x08 0x1ce 0x08 0x4c >;
1086				pm_qos = < 0x5e >;
1087			};
1088
1089			pd_sdioaudio@28 {
1090				reg = < 0x1c >;
1091				clocks = < 0x08 0x1ee >;
1092				pm_qos = < 0x5f >;
1093			};
1094
1095			pd_usb3@24 {
1096				reg = < 0x18 >;
1097				clocks = < 0x08 0xf4 >;
1098				pm_qos = < 0x60 0x61 >;
1099			};
1100
1101			pd_vio@15 {
1102				reg = < 0x0f >;
1103				#address-cells = < 0x01 >;
1104				#size-cells = < 0x00 >;
1105
1106				pd_hdcp@21 {
1107					reg = < 0x15 >;
1108					clocks = < 0x08 0xde 0x08 0x1e7 0x08 0x172 >;
1109					pm_qos = < 0x62 >;
1110				};
1111
1112				pd_isp0@19 {
1113					reg = < 0x13 >;
1114					clocks = < 0x08 0xe5 0x08 0x1df >;
1115					pm_qos = < 0x63 0x64 >;
1116				};
1117
1118				pd_isp1@20 {
1119					reg = < 0x14 >;
1120					clocks = < 0x08 0xe6 0x08 0x1e0 >;
1121					pm_qos = < 0x65 0x66 >;
1122				};
1123
1124				pd_tcpc0@RK3399_PD_TCPC0 {
1125					reg = < 0x08 >;
1126					clocks = < 0x08 0x7e 0x08 0x7d >;
1127				};
1128
1129				pd_tcpc1@RK3399_PD_TCPC1 {
1130					reg = < 0x09 >;
1131					clocks = < 0x08 0x80 0x08 0x7f >;
1132				};
1133
1134				pd_vo@16 {
1135					reg = < 0x10 >;
1136					#address-cells = < 0x01 >;
1137					#size-cells = < 0x00 >;
1138
1139					pd_vopb@17 {
1140						reg = < 0x11 >;
1141						clocks = < 0x08 0xd9 0x08 0x1d9 >;
1142						pm_qos = < 0x67 0x68 >;
1143					};
1144
1145					pd_vopl@18 {
1146						reg = < 0x12 >;
1147						clocks = < 0x08 0xdb 0x08 0x1db >;
1148						pm_qos = < 0x69 >;
1149					};
1150				};
1151			};
1152		};
1153	};
1154
1155	syscon@ff320000 {
1156		compatible = "rockchip,rk3399-pmugrf\0syscon\0simple-mfd";
1157		reg = < 0x00 0xff320000 0x00 0x1000 >;
1158		#address-cells = < 0x01 >;
1159		#size-cells = < 0x01 >;
1160		phandle = < 0x82 >;
1161
1162		io-domains {
1163			compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1164			status = "okay";
1165			pmu1830-supply = < 0x6a >;
1166		};
1167	};
1168
1169	spi@ff350000 {
1170		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
1171		reg = < 0x00 0xff350000 0x00 0x1000 >;
1172		clocks = < 0x6b 0x03 0x6b 0x1f >;
1173		clock-names = "spiclk\0apb_pclk";
1174		interrupts = < 0x00 0x3c 0x04 0x00 >;
1175		pinctrl-names = "default";
1176		pinctrl-0 = < 0x6c 0x6d 0x6e 0x6f >;
1177		#address-cells = < 0x01 >;
1178		#size-cells = < 0x00 >;
1179		status = "disabled";
1180	};
1181
1182	serial@ff370000 {
1183		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
1184		reg = < 0x00 0xff370000 0x00 0x100 >;
1185		clocks = < 0x6b 0x06 0x6b 0x22 >;
1186		clock-names = "baudclk\0apb_pclk";
1187		interrupts = < 0x00 0x66 0x04 0x00 >;
1188		reg-shift = < 0x02 >;
1189		reg-io-width = < 0x04 >;
1190		pinctrl-names = "default";
1191		pinctrl-0 = < 0x70 >;
1192		status = "disabled";
1193	};
1194
1195	i2c@ff3c0000 {
1196		compatible = "rockchip,rk3399-i2c";
1197		reg = < 0x00 0xff3c0000 0x00 0x1000 >;
1198		assigned-clocks = < 0x6b 0x09 >;
1199		assigned-clock-rates = < 0xbebc200 >;
1200		clocks = < 0x6b 0x09 0x6b 0x1b >;
1201		clock-names = "i2c\0pclk";
1202		interrupts = < 0x00 0x39 0x04 0x00 >;
1203		pinctrl-names = "default";
1204		pinctrl-0 = < 0x71 >;
1205		#address-cells = < 0x01 >;
1206		#size-cells = < 0x00 >;
1207		status = "okay";
1208		clock-frequency = < 0x61a80 >;
1209		i2c-scl-rising-time-ns = < 0xa8 >;
1210		i2c-scl-falling-time-ns = < 0x04 >;
1211
1212		pmic@1b {
1213			compatible = "rockchip,rk808";
1214			reg = < 0x1b >;
1215			interrupt-parent = < 0x72 >;
1216			interrupts = < 0x15 0x08 >;
1217			#clock-cells = < 0x01 >;
1218			clock-output-names = "xin32k\0rk808-clkout2";
1219			pinctrl-names = "default";
1220			pinctrl-0 = < 0x73 >;
1221			rockchip,system-power-controller;
1222			wakeup-source;
1223			vcc1-supply = < 0x74 >;
1224			vcc2-supply = < 0x74 >;
1225			vcc3-supply = < 0x74 >;
1226			vcc4-supply = < 0x74 >;
1227			vcc6-supply = < 0x74 >;
1228			vcc7-supply = < 0x74 >;
1229			vcc8-supply = < 0x75 >;
1230			vcc9-supply = < 0x74 >;
1231			vcc10-supply = < 0x74 >;
1232			vcc11-supply = < 0x74 >;
1233			vcc12-supply = < 0x75 >;
1234			vddio-supply = < 0x76 >;
1235			phandle = < 0xad >;
1236
1237			regulators {
1238
1239				DCDC_REG1 {
1240					regulator-name = "vdd_center";
1241					regulator-always-on;
1242					regulator-boot-on;
1243					regulator-min-microvolt = < 0xb71b0 >;
1244					regulator-max-microvolt = < 0x149970 >;
1245					regulator-ramp-delay = < 0x1771 >;
1246
1247					regulator-state-mem {
1248						regulator-off-in-suspend;
1249					};
1250				};
1251
1252				DCDC_REG2 {
1253					regulator-name = "vdd_cpu_l";
1254					regulator-always-on;
1255					regulator-boot-on;
1256					regulator-min-microvolt = < 0xb71b0 >;
1257					regulator-max-microvolt = < 0x149970 >;
1258					regulator-ramp-delay = < 0x1771 >;
1259					phandle = < 0x0c >;
1260
1261					regulator-state-mem {
1262						regulator-off-in-suspend;
1263					};
1264				};
1265
1266				DCDC_REG3 {
1267					regulator-name = "vcc_ddr";
1268					regulator-always-on;
1269					regulator-boot-on;
1270
1271					regulator-state-mem {
1272						regulator-on-in-suspend;
1273					};
1274				};
1275
1276				DCDC_REG4 {
1277					regulator-name = "vcc_1v8";
1278					regulator-always-on;
1279					regulator-boot-on;
1280					regulator-min-microvolt = < 0x1b7740 >;
1281					regulator-max-microvolt = < 0x1b7740 >;
1282					phandle = < 0xaf >;
1283
1284					regulator-state-mem {
1285						regulator-on-in-suspend;
1286						regulator-suspend-microvolt = < 0x1b7740 >;
1287					};
1288				};
1289
1290				LDO_REG1 {
1291					regulator-name = "vcc1v8_dvp";
1292					regulator-always-on;
1293					regulator-boot-on;
1294					regulator-min-microvolt = < 0x1b7740 >;
1295					regulator-max-microvolt = < 0x1b7740 >;
1296					phandle = < 0x83 >;
1297
1298					regulator-state-mem {
1299						regulator-off-in-suspend;
1300					};
1301				};
1302
1303				LDO_REG2 {
1304					regulator-name = "vcc3v0_touch";
1305					regulator-always-on;
1306					regulator-boot-on;
1307					regulator-min-microvolt = < 0x2dc6c0 >;
1308					regulator-max-microvolt = < 0x2dc6c0 >;
1309
1310					regulator-state-mem {
1311						regulator-off-in-suspend;
1312					};
1313				};
1314
1315				LDO_REG3 {
1316					regulator-name = "vcca_1v8";
1317					regulator-always-on;
1318					regulator-boot-on;
1319					regulator-min-microvolt = < 0x1b7740 >;
1320					regulator-max-microvolt = < 0x1b7740 >;
1321					phandle = < 0x76 >;
1322
1323					regulator-state-mem {
1324						regulator-on-in-suspend;
1325						regulator-suspend-microvolt = < 0x1b7740 >;
1326					};
1327				};
1328
1329				LDO_REG4 {
1330					regulator-name = "vcc_sdio";
1331					regulator-always-on;
1332					regulator-boot-on;
1333					regulator-min-microvolt = < 0x1b7740 >;
1334					regulator-max-microvolt = < 0x2dc6c0 >;
1335					phandle = < 0x84 >;
1336
1337					regulator-state-mem {
1338						regulator-on-in-suspend;
1339						regulator-suspend-microvolt = < 0x2dc6c0 >;
1340					};
1341				};
1342
1343				LDO_REG5 {
1344					regulator-name = "vcca3v0_codec";
1345					regulator-always-on;
1346					regulator-boot-on;
1347					regulator-min-microvolt = < 0x2dc6c0 >;
1348					regulator-max-microvolt = < 0x2dc6c0 >;
1349
1350					regulator-state-mem {
1351						regulator-off-in-suspend;
1352					};
1353				};
1354
1355				LDO_REG6 {
1356					regulator-name = "vcc_1v5";
1357					regulator-always-on;
1358					regulator-boot-on;
1359					regulator-min-microvolt = < 0x16e360 >;
1360					regulator-max-microvolt = < 0x16e360 >;
1361
1362					regulator-state-mem {
1363						regulator-on-in-suspend;
1364						regulator-suspend-microvolt = < 0x16e360 >;
1365					};
1366				};
1367
1368				LDO_REG7 {
1369					regulator-name = "vcca1v8_codec";
1370					regulator-always-on;
1371					regulator-boot-on;
1372					regulator-min-microvolt = < 0x1b7740 >;
1373					regulator-max-microvolt = < 0x1b7740 >;
1374
1375					regulator-state-mem {
1376						regulator-off-in-suspend;
1377					};
1378				};
1379
1380				LDO_REG8 {
1381					regulator-name = "vcc_3v0";
1382					regulator-always-on;
1383					regulator-boot-on;
1384					regulator-min-microvolt = < 0x2dc6c0 >;
1385					regulator-max-microvolt = < 0x2dc6c0 >;
1386					phandle = < 0x6a >;
1387
1388					regulator-state-mem {
1389						regulator-on-in-suspend;
1390						regulator-suspend-microvolt = < 0x2dc6c0 >;
1391					};
1392				};
1393
1394				SWITCH_REG1 {
1395					regulator-name = "vcc3v3_s3";
1396					regulator-always-on;
1397					regulator-boot-on;
1398					phandle = < 0x19 >;
1399
1400					regulator-state-mem {
1401						regulator-off-in-suspend;
1402					};
1403				};
1404
1405				SWITCH_REG2 {
1406					regulator-name = "vcc3v3_s0";
1407					regulator-always-on;
1408					regulator-boot-on;
1409
1410					regulator-state-mem {
1411						regulator-off-in-suspend;
1412					};
1413				};
1414			};
1415		};
1416
1417		regulator@40 {
1418			compatible = "silergy,syr827";
1419			reg = < 0x40 >;
1420			fcs,suspend-voltage-selector = < 0x01 >;
1421			pinctrl-names = "default";
1422			pinctrl-0 = < 0x77 >;
1423			regulator-name = "vdd_cpu_b";
1424			regulator-min-microvolt = < 0xadf34 >;
1425			regulator-max-microvolt = < 0x16e360 >;
1426			regulator-ramp-delay = < 0x3e8 >;
1427			regulator-always-on;
1428			regulator-boot-on;
1429			vin-supply = < 0x74 >;
1430			phandle = < 0x0e >;
1431
1432			regulator-state-mem {
1433				regulator-off-in-suspend;
1434			};
1435		};
1436
1437		regulator@41 {
1438			compatible = "silergy,syr828";
1439			reg = < 0x41 >;
1440			fcs,suspend-voltage-selector = < 0x01 >;
1441			pinctrl-names = "default";
1442			pinctrl-0 = < 0x78 >;
1443			regulator-name = "vdd_gpu";
1444			regulator-min-microvolt = < 0xadf34 >;
1445			regulator-max-microvolt = < 0x16e360 >;
1446			regulator-ramp-delay = < 0x3e8 >;
1447			regulator-always-on;
1448			regulator-boot-on;
1449			vin-supply = < 0x74 >;
1450			phandle = < 0xa4 >;
1451
1452			regulator-state-mem {
1453				regulator-off-in-suspend;
1454			};
1455		};
1456	};
1457
1458	i2c@ff3d0000 {
1459		compatible = "rockchip,rk3399-i2c";
1460		reg = < 0x00 0xff3d0000 0x00 0x1000 >;
1461		assigned-clocks = < 0x6b 0x0a >;
1462		assigned-clock-rates = < 0xbebc200 >;
1463		clocks = < 0x6b 0x0a 0x6b 0x1c >;
1464		clock-names = "i2c\0pclk";
1465		interrupts = < 0x00 0x38 0x04 0x00 >;
1466		pinctrl-names = "default";
1467		pinctrl-0 = < 0x79 >;
1468		#address-cells = < 0x01 >;
1469		#size-cells = < 0x00 >;
1470		status = "okay";
1471		i2c-scl-rising-time-ns = < 0x258 >;
1472		i2c-scl-falling-time-ns = < 0x14 >;
1473
1474		typec-portc@22 {
1475			compatible = "fcs,fusb302";
1476			reg = < 0x22 >;
1477			interrupt-parent = < 0x72 >;
1478			interrupts = < 0x02 0x08 >;
1479			pinctrl-names = "default";
1480			pinctrl-0 = < 0x7a >;
1481			vbus-supply = < 0x7b >;
1482			status = "okay";
1483		};
1484	};
1485
1486	i2c@ff3e0000 {
1487		compatible = "rockchip,rk3399-i2c";
1488		reg = < 0x00 0xff3e0000 0x00 0x1000 >;
1489		assigned-clocks = < 0x6b 0x0b >;
1490		assigned-clock-rates = < 0xbebc200 >;
1491		clocks = < 0x6b 0x0b 0x6b 0x1d >;
1492		clock-names = "i2c\0pclk";
1493		interrupts = < 0x00 0x3a 0x04 0x00 >;
1494		pinctrl-names = "default";
1495		pinctrl-0 = < 0x7c >;
1496		#address-cells = < 0x01 >;
1497		#size-cells = < 0x00 >;
1498		status = "disabled";
1499	};
1500
1501	pwm@ff420000 {
1502		compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm";
1503		reg = < 0x00 0xff420000 0x00 0x10 >;
1504		#pwm-cells = < 0x03 >;
1505		pinctrl-names = "default";
1506		pinctrl-0 = < 0x7d >;
1507		clocks = < 0x6b 0x1e >;
1508		clock-names = "pwm";
1509		status = "okay";
1510	};
1511
1512	pwm@ff420010 {
1513		compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm";
1514		reg = < 0x00 0xff420010 0x00 0x10 >;
1515		#pwm-cells = < 0x03 >;
1516		pinctrl-names = "default";
1517		pinctrl-0 = < 0x7e >;
1518		clocks = < 0x6b 0x1e >;
1519		clock-names = "pwm";
1520		status = "disabled";
1521	};
1522
1523	pwm@ff420020 {
1524		compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm";
1525		reg = < 0x00 0xff420020 0x00 0x10 >;
1526		#pwm-cells = < 0x03 >;
1527		pinctrl-names = "default";
1528		pinctrl-0 = < 0x7f >;
1529		clocks = < 0x6b 0x1e >;
1530		clock-names = "pwm";
1531		status = "okay";
1532		phandle = < 0xb6 >;
1533	};
1534
1535	pwm@ff420030 {
1536		compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm";
1537		reg = < 0x00 0xff420030 0x00 0x10 >;
1538		#pwm-cells = < 0x03 >;
1539		pinctrl-names = "default";
1540		pinctrl-0 = < 0x80 >;
1541		clocks = < 0x6b 0x1e >;
1542		clock-names = "pwm";
1543		status = "disabled";
1544	};
1545
1546	video-codec@ff650000 {
1547		compatible = "rockchip,rk3399-vpu";
1548		reg = < 0x00 0xff650000 0x00 0x800 >;
1549		interrupts = < 0x00 0x72 0x04 0x00 0x00 0x71 0x04 0x00 >;
1550		interrupt-names = "vepu\0vdpu";
1551		clocks = < 0x08 0xeb 0x08 0x1ea >;
1552		clock-names = "aclk\0hclk";
1553		iommus = < 0x81 >;
1554		power-domains = < 0x16 0x1f >;
1555	};
1556
1557	iommu@ff650800 {
1558		compatible = "rockchip,iommu";
1559		reg = < 0x00 0xff650800 0x00 0x40 >;
1560		interrupts = < 0x00 0x73 0x04 0x00 >;
1561		interrupt-names = "vpu_mmu";
1562		clocks = < 0x08 0xeb 0x08 0x1ea >;
1563		clock-names = "aclk\0iface";
1564		#iommu-cells = < 0x00 >;
1565		power-domains = < 0x16 0x1f >;
1566		phandle = < 0x81 >;
1567	};
1568
1569	iommu@ff660480 {
1570		compatible = "rockchip,iommu";
1571		reg = < 0x00 0xff660480 0x00 0x40 0x00 0xff6604c0 0x00 0x40 >;
1572		interrupts = < 0x00 0x75 0x04 0x00 >;
1573		interrupt-names = "vdec_mmu";
1574		clocks = < 0x08 0xed 0x08 0x1ec >;
1575		clock-names = "aclk\0iface";
1576		#iommu-cells = < 0x00 >;
1577		status = "disabled";
1578	};
1579
1580	iommu@ff670800 {
1581		compatible = "rockchip,iommu";
1582		reg = < 0x00 0xff670800 0x00 0x40 >;
1583		interrupts = < 0x00 0x2a 0x04 0x00 >;
1584		interrupt-names = "iep_mmu";
1585		clocks = < 0x08 0xe1 0x08 0x1dd >;
1586		clock-names = "aclk\0iface";
1587		#iommu-cells = < 0x00 >;
1588		status = "disabled";
1589	};
1590
1591	rga@ff680000 {
1592		compatible = "rockchip,rk3399-rga";
1593		reg = < 0x00 0xff680000 0x00 0x10000 >;
1594		interrupts = < 0x00 0x37 0x04 0x00 >;
1595		clocks = < 0x08 0xdc 0x08 0x1e5 0x08 0x6d >;
1596		clock-names = "aclk\0hclk\0sclk";
1597		resets = < 0x08 0x6a 0x08 0x67 0x08 0x69 >;
1598		reset-names = "core\0axi\0ahb";
1599		power-domains = < 0x16 0x21 >;
1600	};
1601
1602	efuse@ff690000 {
1603		compatible = "rockchip,rk3399-efuse";
1604		reg = < 0x00 0xff690000 0x00 0x80 >;
1605		#address-cells = < 0x01 >;
1606		#size-cells = < 0x01 >;
1607		clocks = < 0x08 0x17d >;
1608		clock-names = "pclk_efuse";
1609
1610		cpu-id@7 {
1611			reg = < 0x07 0x10 >;
1612		};
1613
1614		cpu-leakage@17 {
1615			reg = < 0x17 0x01 >;
1616		};
1617
1618		gpu-leakage@18 {
1619			reg = < 0x18 0x01 >;
1620		};
1621
1622		center-leakage@19 {
1623			reg = < 0x19 0x01 >;
1624		};
1625
1626		cpu-leakage@1a {
1627			reg = < 0x1a 0x01 >;
1628		};
1629
1630		logic-leakage@1b {
1631			reg = < 0x1b 0x01 >;
1632		};
1633
1634		wafer-info@1c {
1635			reg = < 0x1c 0x01 >;
1636		};
1637	};
1638
1639	pmu-clock-controller@ff750000 {
1640		compatible = "rockchip,rk3399-pmucru";
1641		reg = < 0x00 0xff750000 0x00 0x1000 >;
1642		rockchip,grf = < 0x82 >;
1643		#clock-cells = < 0x01 >;
1644		#reset-cells = < 0x01 >;
1645		assigned-clocks = < 0x6b 0x01 >;
1646		assigned-clock-rates = < 0x284af100 >;
1647		phandle = < 0x6b >;
1648	};
1649
1650	clock-controller@ff760000 {
1651		compatible = "rockchip,rk3399-cru";
1652		reg = < 0x00 0xff760000 0x00 0x1000 >;
1653		rockchip,grf = < 0x17 >;
1654		#clock-cells = < 0x01 >;
1655		#reset-cells = < 0x01 >;
1656		assigned-clocks = < 0x08 0x05 0x08 0x04 0x08 0x06 0x08 0xc0 0x08 0x1c0 0x08 0x140 0x08 0xc2 0x08 0x1c1 0x08 0x142 0x08 0xc9 0x08 0x1c2 0x08 0x143 0x08 0xe3 0x08 0xde 0x08 0x106 0x08 0x178 >;
1657		assigned-clock-rates = < 0x2367b880 0x2faf0800 0x3b9aca00 0x8f0d180 0x47868c0 0x23c3460 0x5f5e100 0x5f5e100 0x2faf080 0x23c34600 0x5f5e100 0x2faf080 0x17d78400 0x17d78400 0xbebc200 0xbebc200 >;
1658		phandle = < 0x08 >;
1659	};
1660
1661	syscon@ff770000 {
1662		compatible = "rockchip,rk3399-grf\0syscon\0simple-mfd";
1663		reg = < 0x00 0xff770000 0x00 0x10000 >;
1664		#address-cells = < 0x01 >;
1665		#size-cells = < 0x01 >;
1666		phandle = < 0x17 >;
1667
1668		io-domains {
1669			compatible = "rockchip,rk3399-io-voltage-domain";
1670			status = "okay";
1671			bt656-supply = < 0x83 >;
1672			audio-supply = < 0x6a >;
1673			sdmmc-supply = < 0x84 >;
1674			gpio1830-supply = < 0x6a >;
1675		};
1676
1677		usb2-phy@e450 {
1678			compatible = "rockchip,rk3399-usb2phy";
1679			reg = < 0xe450 0x10 >;
1680			clocks = < 0x08 0x7b >;
1681			clock-names = "phyclk";
1682			#clock-cells = < 0x00 >;
1683			clock-output-names = "clk_usbphy0_480m";
1684			status = "okay";
1685			phandle = < 0x21 >;
1686
1687			host-port {
1688				#phy-cells = < 0x00 >;
1689				interrupts = < 0x00 0x1b 0x04 0x00 >;
1690				interrupt-names = "linestate";
1691				status = "okay";
1692				phy-supply = < 0x85 >;
1693				phandle = < 0x22 >;
1694			};
1695
1696			otg-port {
1697				#phy-cells = < 0x00 >;
1698				interrupts = < 0x00 0x67 0x04 0x00 0x00 0x68 0x04 0x00 0x00 0x6a 0x04 0x00 >;
1699				interrupt-names = "otg-bvalid\0otg-id\0linestate";
1700				status = "okay";
1701				phandle = < 0x25 >;
1702			};
1703		};
1704
1705		usb2-phy@e460 {
1706			compatible = "rockchip,rk3399-usb2phy";
1707			reg = < 0xe460 0x10 >;
1708			clocks = < 0x08 0x7c >;
1709			clock-names = "phyclk";
1710			#clock-cells = < 0x00 >;
1711			clock-output-names = "clk_usbphy1_480m";
1712			status = "okay";
1713			phandle = < 0x23 >;
1714
1715			host-port {
1716				#phy-cells = < 0x00 >;
1717				interrupts = < 0x00 0x1f 0x04 0x00 >;
1718				interrupt-names = "linestate";
1719				status = "okay";
1720				phy-supply = < 0x85 >;
1721				phandle = < 0x24 >;
1722			};
1723
1724			otg-port {
1725				#phy-cells = < 0x00 >;
1726				interrupts = < 0x00 0x6c 0x04 0x00 0x00 0x6d 0x04 0x00 0x00 0x6f 0x04 0x00 >;
1727				interrupt-names = "otg-bvalid\0otg-id\0linestate";
1728				status = "okay";
1729				phandle = < 0x27 >;
1730			};
1731		};
1732
1733		phy@f780 {
1734			compatible = "rockchip,rk3399-emmc-phy";
1735			reg = < 0xf780 0x24 >;
1736			clocks = < 0x86 >;
1737			clock-names = "emmcclk";
1738			#phy-cells = < 0x00 >;
1739			status = "okay";
1740			phandle = < 0x20 >;
1741		};
1742
1743		pcie-phy {
1744			compatible = "rockchip,rk3399-pcie-phy";
1745			clocks = < 0x08 0x8a >;
1746			clock-names = "refclk";
1747			#phy-cells = < 0x01 >;
1748			resets = < 0x08 0x87 >;
1749			drive-impedance-ohm = < 0x32 >;
1750			reset-names = "phy";
1751			status = "disabled";
1752			phandle = < 0x15 >;
1753		};
1754	};
1755
1756	phy@ff7c0000 {
1757		compatible = "rockchip,rk3399-typec-phy";
1758		reg = < 0x00 0xff7c0000 0x00 0x40000 >;
1759		clocks = < 0x08 0x7e 0x08 0x7d >;
1760		clock-names = "tcpdcore\0tcpdphy-ref";
1761		assigned-clocks = < 0x08 0x7e >;
1762		assigned-clock-rates = < 0x2faf080 >;
1763		power-domains = < 0x16 0x08 >;
1764		resets = < 0x08 0x95 0x08 0x94 0x08 0x14c >;
1765		reset-names = "uphy\0uphy-pipe\0uphy-tcphy";
1766		rockchip,grf = < 0x17 >;
1767		status = "okay";
1768
1769		dp-port {
1770			#phy-cells = < 0x00 >;
1771			phandle = < 0x29 >;
1772		};
1773
1774		usb3-port {
1775			#phy-cells = < 0x00 >;
1776			phandle = < 0x26 >;
1777		};
1778	};
1779
1780	phy@ff800000 {
1781		compatible = "rockchip,rk3399-typec-phy";
1782		reg = < 0x00 0xff800000 0x00 0x40000 >;
1783		clocks = < 0x08 0x80 0x08 0x7f >;
1784		clock-names = "tcpdcore\0tcpdphy-ref";
1785		assigned-clocks = < 0x08 0x80 >;
1786		assigned-clock-rates = < 0x2faf080 >;
1787		power-domains = < 0x16 0x09 >;
1788		resets = < 0x08 0x9d 0x08 0x9c 0x08 0x14d >;
1789		reset-names = "uphy\0uphy-pipe\0uphy-tcphy";
1790		rockchip,grf = < 0x17 >;
1791		status = "okay";
1792
1793		dp-port {
1794			#phy-cells = < 0x00 >;
1795			phandle = < 0x2a >;
1796		};
1797
1798		usb3-port {
1799			#phy-cells = < 0x00 >;
1800			phandle = < 0x28 >;
1801		};
1802	};
1803
1804	watchdog@ff848000 {
1805		compatible = "snps,dw-wdt";
1806		reg = < 0x00 0xff848000 0x00 0x100 >;
1807		clocks = < 0x08 0x17c >;
1808		interrupts = < 0x00 0x78 0x04 0x00 >;
1809	};
1810/*
1811For future reference timer blocks are 0x20
1812and sit next to one another from a base address.
1813*/
1814	rktimer@ff850000 {
1815		compatible = "rockchip,rk3399-timer";
1816		reg = < 0x00 0xff850000 0x00 0x20 >;
1817		interrupts = < 0x00 0x51 0x04 0x00 >;
1818		clocks = < 0x08 0x168 0x08 0x5a >;
1819		clock-names = "pclk\0timer";
1820	};
1821
1822	rktimer@ff858000 {
1823		compatible = "rockchip,rk3399-timer";
1824		reg = < 0x00 0xff850020 0x00 0x20 >;
1825		interrupts = < 0x00 0x52 0x04 0x00>;
1826		clocks = < 0x08 0x168 0x08 0x5a >;
1827		clock-names = "pclk\1timer";
1828	};
1829
1830	spdif@ff870000 {
1831		compatible = "rockchip,rk3399-spdif";
1832		reg = < 0x00 0xff870000 0x00 0x1000 >;
1833		interrupts = < 0x00 0x42 0x04 0x00 >;
1834		dmas = < 0x4a 0x07 >;
1835		dma-names = "tx";
1836		clock-names = "mclk\0hclk";
1837		clocks = < 0x08 0x55 0x08 0x1d7 >;
1838		pinctrl-names = "default";
1839		pinctrl-0 = < 0x87 >;
1840		power-domains = < 0x16 0x1c >;
1841		#sound-dai-cells = < 0x00 >;
1842		status = "disabled";
1843	};
1844
1845	i2s@ff880000 {
1846		compatible = "rockchip,rk3399-i2s\0rockchip,rk3066-i2s";
1847		reg = < 0x00 0xff880000 0x00 0x1000 >;
1848		rockchip,grf = < 0x17 >;
1849		interrupts = < 0x00 0x27 0x04 0x00 >;
1850		dmas = < 0x4a 0x00 0x4a 0x01 >;
1851		dma-names = "tx\0rx";
1852		clock-names = "i2s_clk\0i2s_hclk";
1853		clocks = < 0x08 0x56 0x08 0x1d4 >;
1854		pinctrl-names = "default";
1855		pinctrl-0 = < 0x88 >;
1856		power-domains = < 0x16 0x1c >;
1857		#sound-dai-cells = < 0x00 >;
1858		status = "okay";
1859		rockchip,playback-channels = < 0x08 >;
1860		rockchip,capture-channels = < 0x08 >;
1861	};
1862
1863	i2s@ff890000 {
1864		compatible = "rockchip,rk3399-i2s\0rockchip,rk3066-i2s";
1865		reg = < 0x00 0xff890000 0x00 0x1000 >;
1866		interrupts = < 0x00 0x28 0x04 0x00 >;
1867		dmas = < 0x4a 0x02 0x4a 0x03 >;
1868		dma-names = "tx\0rx";
1869		clock-names = "i2s_clk\0i2s_hclk";
1870		clocks = < 0x08 0x57 0x08 0x1d5 >;
1871		pinctrl-names = "default";
1872		pinctrl-0 = < 0x89 >;
1873		power-domains = < 0x16 0x1c >;
1874		#sound-dai-cells = < 0x00 >;
1875		status = "okay";
1876		rockchip,playback-channels = < 0x02 >;
1877		rockchip,capture-channels = < 0x02 >;
1878	};
1879
1880	i2s@ff8a0000 {
1881		compatible = "rockchip,rk3399-i2s\0rockchip,rk3066-i2s";
1882		reg = < 0x00 0xff8a0000 0x00 0x1000 >;
1883		interrupts = < 0x00 0x29 0x04 0x00 >;
1884		dmas = < 0x4a 0x04 0x4a 0x05 >;
1885		dma-names = "tx\0rx";
1886		clock-names = "i2s_clk\0i2s_hclk";
1887		clocks = < 0x08 0x58 0x08 0x1d6 >;
1888		power-domains = < 0x16 0x1c >;
1889		#sound-dai-cells = < 0x00 >;
1890		status = "okay";
1891		phandle = < 0x96 >;
1892	};
1893
1894	vop@ff8f0000 {
1895		compatible = "rockchip,rk3399-vop-lit";
1896		reg = < 0x00 0xff8f0000 0x00 0x3efc >;
1897		interrupts = < 0x00 0x77 0x04 0x00 >;
1898		assigned-clocks = < 0x08 0xdb 0x08 0x1db >;
1899		assigned-clock-rates = < 0x17d78400 0x5f5e100 >;
1900		clocks = < 0x08 0xdb 0x08 0xb5 0x08 0x1db >;
1901		clock-names = "aclk_vop\0dclk_vop\0hclk_vop";
1902		iommus = < 0x8a >;
1903		power-domains = < 0x16 0x12 >;
1904		resets = < 0x08 0x113 0x08 0x117 0x08 0x119 >;
1905		reset-names = "axi\0ahb\0dclk";
1906		status = "okay";
1907
1908		port {
1909			#address-cells = < 0x01 >;
1910			#size-cells = < 0x00 >;
1911			phandle = < 0x0f >;
1912
1913			endpoint@0 {
1914				reg = < 0x00 >;
1915				remote-endpoint = < 0x8b >;
1916				phandle = < 0x9d >;
1917			};
1918
1919			endpoint@1 {
1920				reg = < 0x01 >;
1921				remote-endpoint = < 0x8c >;
1922				phandle = < 0xa2 >;
1923			};
1924
1925			endpoint@2 {
1926				reg = < 0x02 >;
1927				remote-endpoint = < 0x8d >;
1928				phandle = < 0x9b >;
1929			};
1930
1931			endpoint@3 {
1932				reg = < 0x03 >;
1933				remote-endpoint = < 0x8e >;
1934				phandle = < 0x9f >;
1935			};
1936
1937			endpoint@4 {
1938				reg = < 0x04 >;
1939				remote-endpoint = < 0x8f >;
1940				phandle = < 0x2c >;
1941			};
1942		};
1943	};
1944
1945	iommu@ff8f3f00 {
1946		compatible = "rockchip,iommu";
1947		reg = < 0x00 0xff8f3f00 0x00 0x100 >;
1948		interrupts = < 0x00 0x77 0x04 0x00 >;
1949		interrupt-names = "vopl_mmu";
1950		clocks = < 0x08 0xdb 0x08 0x1db >;
1951		clock-names = "aclk\0iface";
1952		power-domains = < 0x16 0x12 >;
1953		#iommu-cells = < 0x00 >;
1954		status = "okay";
1955		phandle = < 0x8a >;
1956	};
1957
1958	vop@ff900000 {
1959		compatible = "rockchip,rk3399-vop-big";
1960		reg = < 0x00 0xff900000 0x00 0x3efc >;
1961		interrupts = < 0x00 0x76 0x04 0x00 >;
1962		assigned-clocks = < 0x08 0xd9 0x08 0x1d9 >;
1963		assigned-clock-rates = < 0x17d78400 0x5f5e100 >;
1964		clocks = < 0x08 0xd9 0x08 0xb4 0x08 0x1d9 >;
1965		clock-names = "aclk_vop\0dclk_vop\0hclk_vop";
1966		iommus = < 0x90 >;
1967		power-domains = < 0x16 0x11 >;
1968		resets = < 0x08 0x112 0x08 0x116 0x08 0x118 >;
1969		reset-names = "axi\0ahb\0dclk";
1970		status = "okay";
1971
1972		port {
1973			#address-cells = < 0x01 >;
1974			#size-cells = < 0x00 >;
1975			phandle = < 0x10 >;
1976
1977			endpoint@0 {
1978				reg = < 0x00 >;
1979				remote-endpoint = < 0x91 >;
1980				phandle = < 0xa1 >;
1981			};
1982
1983			endpoint@1 {
1984				reg = < 0x01 >;
1985				remote-endpoint = < 0x92 >;
1986				phandle = < 0x9c >;
1987			};
1988
1989			endpoint@2 {
1990				reg = < 0x02 >;
1991				remote-endpoint = < 0x93 >;
1992				phandle = < 0x9a >;
1993			};
1994
1995			endpoint@3 {
1996				reg = < 0x03 >;
1997				remote-endpoint = < 0x94 >;
1998				phandle = < 0x9e >;
1999			};
2000
2001			endpoint@4 {
2002				reg = < 0x04 >;
2003				remote-endpoint = < 0x95 >;
2004				phandle = < 0x2b >;
2005			};
2006		};
2007	};
2008
2009	iommu@ff903f00 {
2010		compatible = "rockchip,iommu";
2011		reg = < 0x00 0xff903f00 0x00 0x100 >;
2012		interrupts = < 0x00 0x76 0x04 0x00 >;
2013		interrupt-names = "vopb_mmu";
2014		clocks = < 0x08 0xd9 0x08 0x1d9 >;
2015		clock-names = "aclk\0iface";
2016		power-domains = < 0x16 0x11 >;
2017		#iommu-cells = < 0x00 >;
2018		status = "okay";
2019		phandle = < 0x90 >;
2020	};
2021
2022	iommu@ff914000 {
2023		compatible = "rockchip,iommu";
2024		reg = < 0x00 0xff914000 0x00 0x100 0x00 0xff915000 0x00 0x100 >;
2025		interrupts = < 0x00 0x2b 0x04 0x00 >;
2026		interrupt-names = "isp0_mmu";
2027		clocks = < 0x08 0xe7 0x08 0x1e1 >;
2028		clock-names = "aclk\0iface";
2029		#iommu-cells = < 0x00 >;
2030		rockchip,disable-mmu-reset;
2031		status = "disabled";
2032	};
2033
2034	iommu@ff924000 {
2035		compatible = "rockchip,iommu";
2036		reg = < 0x00 0xff924000 0x00 0x100 0x00 0xff925000 0x00 0x100 >;
2037		interrupts = < 0x00 0x2c 0x04 0x00 >;
2038		interrupt-names = "isp1_mmu";
2039		clocks = < 0x08 0xe8 0x08 0x1e2 >;
2040		clock-names = "aclk\0iface";
2041		#iommu-cells = < 0x00 >;
2042		rockchip,disable-mmu-reset;
2043		status = "disabled";
2044	};
2045
2046	hdmi-sound {
2047		compatible = "simple-audio-card";
2048		simple-audio-card,format = "i2s";
2049		simple-audio-card,mclk-fs = < 0x100 >;
2050		simple-audio-card,name = "hdmi-sound";
2051		status = "okay";
2052
2053		simple-audio-card,cpu {
2054			sound-dai = < 0x96 >;
2055		};
2056
2057		simple-audio-card,codec {
2058			sound-dai = < 0x97 >;
2059		};
2060	};
2061
2062	hdmi@ff940000 {
2063		compatible = "rockchip,rk3399-dw-hdmi";
2064		reg = < 0x00 0xff940000 0x00 0x20000 >;
2065		interrupts = < 0x00 0x17 0x04 0x00 >;
2066		clocks = < 0x08 0x174 0x08 0x71 0x08 0x07 0x08 0x16f 0x08 0x70 >;
2067		clock-names = "iahb\0isfr\0vpll\0grf\0cec";
2068		power-domains = < 0x16 0x15 >;
2069		reg-io-width = < 0x04 >;
2070		rockchip,grf = < 0x17 >;
2071		#sound-dai-cells = < 0x00 >;
2072		status = "okay";
2073		ddc-i2c-bus = < 0x98 >;
2074		pinctrl-names = "default";
2075		pinctrl-0 = < 0x99 >;
2076		phandle = < 0x97 >;
2077
2078		ports {
2079
2080			port {
2081				#address-cells = < 0x01 >;
2082				#size-cells = < 0x00 >;
2083
2084				endpoint@0 {
2085					reg = < 0x00 >;
2086					remote-endpoint = < 0x9a >;
2087					phandle = < 0x93 >;
2088				};
2089
2090				endpoint@1 {
2091					reg = < 0x01 >;
2092					remote-endpoint = < 0x9b >;
2093					phandle = < 0x8d >;
2094				};
2095			};
2096		};
2097	};
2098
2099	mipi@ff960000 {
2100		compatible = "rockchip,rk3399-mipi-dsi\0snps,dw-mipi-dsi";
2101		reg = < 0x00 0xff960000 0x00 0x8000 >;
2102		interrupts = < 0x00 0x2d 0x04 0x00 >;
2103		clocks = < 0x08 0xa2 0x08 0x170 0x08 0xa3 0x08 0x16f >;
2104		clock-names = "ref\0pclk\0phy_cfg\0grf";
2105		power-domains = < 0x16 0x0f >;
2106		resets = < 0x08 0xfb >;
2107		reset-names = "apb";
2108		rockchip,grf = < 0x17 >;
2109		#address-cells = < 0x01 >;
2110		#size-cells = < 0x00 >;
2111		status = "disabled";
2112
2113		ports {
2114			#address-cells = < 0x01 >;
2115			#size-cells = < 0x00 >;
2116
2117			port@0 {
2118				reg = < 0x00 >;
2119				#address-cells = < 0x01 >;
2120				#size-cells = < 0x00 >;
2121
2122				endpoint@0 {
2123					reg = < 0x00 >;
2124					remote-endpoint = < 0x9c >;
2125					phandle = < 0x92 >;
2126				};
2127
2128				endpoint@1 {
2129					reg = < 0x01 >;
2130					remote-endpoint = < 0x9d >;
2131					phandle = < 0x8b >;
2132				};
2133			};
2134		};
2135	};
2136
2137	mipi@ff968000 {
2138		compatible = "rockchip,rk3399-mipi-dsi\0snps,dw-mipi-dsi";
2139		reg = < 0x00 0xff968000 0x00 0x8000 >;
2140		interrupts = < 0x00 0x2e 0x04 0x00 >;
2141		clocks = < 0x08 0xa2 0x08 0x171 0x08 0xa4 0x08 0x16f >;
2142		clock-names = "ref\0pclk\0phy_cfg\0grf";
2143		power-domains = < 0x16 0x0f >;
2144		resets = < 0x08 0xfc >;
2145		reset-names = "apb";
2146		rockchip,grf = < 0x17 >;
2147		#address-cells = < 0x01 >;
2148		#size-cells = < 0x00 >;
2149		status = "disabled";
2150
2151		ports {
2152			#address-cells = < 0x01 >;
2153			#size-cells = < 0x00 >;
2154
2155			port@0 {
2156				reg = < 0x00 >;
2157				#address-cells = < 0x01 >;
2158				#size-cells = < 0x00 >;
2159
2160				endpoint@0 {
2161					reg = < 0x00 >;
2162					remote-endpoint = < 0x9e >;
2163					phandle = < 0x94 >;
2164				};
2165
2166				endpoint@1 {
2167					reg = < 0x01 >;
2168					remote-endpoint = < 0x9f >;
2169					phandle = < 0x8e >;
2170				};
2171			};
2172		};
2173	};
2174
2175	edp@ff970000 {
2176		compatible = "rockchip,rk3399-edp";
2177		reg = < 0x00 0xff970000 0x00 0x8000 >;
2178		interrupts = < 0x00 0x0a 0x04 0x00 >;
2179		clocks = < 0x08 0x16a 0x08 0x16c 0x08 0x16f >;
2180		clock-names = "dp\0pclk\0grf";
2181		pinctrl-names = "default";
2182		pinctrl-0 = < 0xa0 >;
2183		power-domains = < 0x16 0x19 >;
2184		resets = < 0x08 0x11d >;
2185		reset-names = "dp";
2186		rockchip,grf = < 0x17 >;
2187		status = "disabled";
2188
2189		ports {
2190			#address-cells = < 0x01 >;
2191			#size-cells = < 0x00 >;
2192
2193			port@0 {
2194				reg = < 0x00 >;
2195				#address-cells = < 0x01 >;
2196				#size-cells = < 0x00 >;
2197
2198				endpoint@0 {
2199					reg = < 0x00 >;
2200					remote-endpoint = < 0xa1 >;
2201					phandle = < 0x91 >;
2202				};
2203
2204				endpoint@1 {
2205					reg = < 0x01 >;
2206					remote-endpoint = < 0xa2 >;
2207					phandle = < 0x8c >;
2208				};
2209			};
2210		};
2211	};
2212
2213	gpu@ff9a0000 {
2214		compatible = "rockchip,rk3399-mali\0arm,mali-t860";
2215		reg = < 0x00 0xff9a0000 0x00 0x10000 >;
2216		interrupts = < 0x00 0x13 0x04 0x00 0x00 0x14 0x04 0x00 0x00 0x15 0x04 0x00 >;
2217		interrupt-names = "gpu\0job\0mmu";
2218		clocks = < 0x08 0xd0 >;
2219		power-domains = < 0x16 0x23 >;
2220		status = "okay";
2221		operating-points-v2 = < 0xa3 >;
2222		mali-supply = < 0xa4 >;
2223	};
2224
2225	pinctrl {
2226		compatible = "rockchip,rk3399-pinctrl";
2227		rockchip,grf = < 0x17 >;
2228		rockchip,pmu = < 0x82 >;
2229		#address-cells = < 0x02 >;
2230		#size-cells = < 0x02 >;
2231		ranges;
2232
2233		gpio0@ff720000 {
2234			compatible = "rockchip,gpio-bank";
2235			reg = < 0x00 0xff720000 0x00 0x100 >;
2236			clocks = < 0x6b 0x17 >;
2237			interrupts = < 0x00 0x0e 0x04 0x00 >;
2238			gpio-controller;
2239			#gpio-cells = < 0x02 >;
2240			interrupt-controller;
2241			#interrupt-cells = < 0x02 >;
2242			phandle = < 0x1c >;
2243		};
2244
2245		gpio1@ff730000 {
2246			compatible = "rockchip,gpio-bank";
2247			reg = < 0x00 0xff730000 0x00 0x100 >;
2248			clocks = < 0x6b 0x18 >;
2249			interrupts = < 0x00 0x0f 0x04 0x00 >;
2250			gpio-controller;
2251			#gpio-cells = < 0x02 >;
2252			interrupt-controller;
2253			#interrupt-cells = < 0x02 >;
2254			phandle = < 0x72 >;
2255		};
2256
2257		gpio2@ff780000 {
2258			compatible = "rockchip,gpio-bank";
2259			reg = < 0x00 0xff780000 0x00 0x100 >;
2260			clocks = < 0x08 0x150 >;
2261			interrupts = < 0x00 0x10 0x04 0x00 >;
2262			gpio-controller;
2263			#gpio-cells = < 0x02 >;
2264			interrupt-controller;
2265			#interrupt-cells = < 0x02 >;
2266		};
2267
2268		gpio3@ff788000 {
2269			compatible = "rockchip,gpio-bank";
2270			reg = < 0x00 0xff788000 0x00 0x100 >;
2271			clocks = < 0x08 0x151 >;
2272			interrupts = < 0x00 0x11 0x04 0x00 >;
2273			gpio-controller;
2274			#gpio-cells = < 0x02 >;
2275			interrupt-controller;
2276			#interrupt-cells = < 0x02 >;
2277			phandle = < 0x1b >;
2278		};
2279
2280		gpio4@ff790000 {
2281			compatible = "rockchip,gpio-bank";
2282			reg = < 0x00 0xff790000 0x00 0x100 >;
2283			clocks = < 0x08 0x152 >;
2284			interrupts = < 0x00 0x12 0x04 0x00 >;
2285			gpio-controller;
2286			#gpio-cells = < 0x02 >;
2287			interrupt-controller;
2288			#interrupt-cells = < 0x02 >;
2289			phandle = < 0xb2 >;
2290		};
2291
2292		pcfg-pull-up {
2293			bias-pull-up;
2294			phandle = < 0xa8 >;
2295		};
2296
2297		pcfg-pull-down {
2298			bias-pull-down;
2299			phandle = < 0xa9 >;
2300		};
2301
2302		pcfg-pull-none {
2303			bias-disable;
2304			phandle = < 0xa5 >;
2305		};
2306
2307		pcfg-pull-none-12ma {
2308			bias-disable;
2309			drive-strength = < 0x0c >;
2310			phandle = < 0xa7 >;
2311		};
2312
2313		pcfg-pull-none-13ma {
2314			bias-disable;
2315			drive-strength = < 0x0d >;
2316			phandle = < 0xa6 >;
2317		};
2318
2319		pcfg-pull-none-18ma {
2320			bias-disable;
2321			drive-strength = < 0x12 >;
2322		};
2323
2324		pcfg-pull-none-20ma {
2325			bias-disable;
2326			drive-strength = < 0x14 >;
2327		};
2328
2329		pcfg-pull-up-2ma {
2330			bias-pull-up;
2331			drive-strength = < 0x02 >;
2332		};
2333
2334		pcfg-pull-up-8ma {
2335			bias-pull-up;
2336			drive-strength = < 0x08 >;
2337		};
2338
2339		pcfg-pull-up-18ma {
2340			bias-pull-up;
2341			drive-strength = < 0x12 >;
2342		};
2343
2344		pcfg-pull-up-20ma {
2345			bias-pull-up;
2346			drive-strength = < 0x14 >;
2347		};
2348
2349		pcfg-pull-down-4ma {
2350			bias-pull-down;
2351			drive-strength = < 0x04 >;
2352		};
2353
2354		pcfg-pull-down-8ma {
2355			bias-pull-down;
2356			drive-strength = < 0x08 >;
2357		};
2358
2359		pcfg-pull-down-12ma {
2360			bias-pull-down;
2361			drive-strength = < 0x0c >;
2362		};
2363
2364		pcfg-pull-down-18ma {
2365			bias-pull-down;
2366			drive-strength = < 0x12 >;
2367		};
2368
2369		pcfg-pull-down-20ma {
2370			bias-pull-down;
2371			drive-strength = < 0x14 >;
2372		};
2373
2374		pcfg-output-high {
2375			output-high;
2376		};
2377
2378		pcfg-output-low {
2379			output-low;
2380		};
2381
2382		clock {
2383
2384			clk-32k {
2385				rockchip,pins = < 0x00 0x00 0x02 0xa5 >;
2386			};
2387		};
2388
2389		edp {
2390
2391			edp-hpd {
2392				rockchip,pins = < 0x04 0x17 0x02 0xa5 >;
2393				phandle = < 0xa0 >;
2394			};
2395		};
2396
2397		gmac {
2398
2399			rgmii-pins {
2400				rockchip,pins = < 0x03 0x11 0x01 0xa6 0x03 0x0e 0x01 0xa5 0x03 0x0d 0x01 0xa5 0x03 0x0c 0x01 0xa6 0x03 0x0b 0x01 0xa5 0x03 0x09 0x01 0xa5 0x03 0x08 0x01 0xa5 0x03 0x07 0x01 0xa5 0x03 0x06 0x01 0xa5 0x03 0x05 0x01 0xa6 0x03 0x04 0x01 0xa6 0x03 0x03 0x01 0xa5 0x03 0x02 0x01 0xa5 0x03 0x01 0x01 0xa6 0x03 0x00 0x01 0xa6 >;
2401				phandle = < 0x1a >;
2402			};
2403
2404			rmii-pins {
2405				rockchip,pins = < 0x03 0x0d 0x01 0xa5 0x03 0x0c 0x01 0xa6 0x03 0x0b 0x01 0xa5 0x03 0x0a 0x01 0xa5 0x03 0x09 0x01 0xa5 0x03 0x08 0x01 0xa5 0x03 0x07 0x01 0xa5 0x03 0x06 0x01 0xa5 0x03 0x05 0x01 0xa6 0x03 0x04 0x01 0xa6 >;
2406			};
2407		};
2408
2409		i2c0 {
2410
2411			i2c0-xfer {
2412				rockchip,pins = < 0x01 0x0f 0x02 0xa5 0x01 0x10 0x02 0xa5 >;
2413				phandle = < 0x71 >;
2414			};
2415		};
2416
2417		i2c1 {
2418
2419			i2c1-xfer {
2420				rockchip,pins = < 0x04 0x02 0x01 0xa5 0x04 0x01 0x01 0xa5 >;
2421				phandle = < 0x2e >;
2422			};
2423		};
2424
2425		i2c2 {
2426
2427			i2c2-xfer {
2428				rockchip,pins = < 0x02 0x01 0x02 0xa7 0x02 0x00 0x02 0xa7 >;
2429				phandle = < 0x2f >;
2430			};
2431		};
2432
2433		i2c3 {
2434
2435			i2c3-xfer {
2436				rockchip,pins = < 0x04 0x11 0x01 0xa5 0x04 0x10 0x01 0xa5 >;
2437				phandle = < 0x30 >;
2438			};
2439		};
2440
2441		i2c4 {
2442
2443			i2c4-xfer {
2444				rockchip,pins = < 0x01 0x0c 0x01 0xa5 0x01 0x0b 0x01 0xa5 >;
2445				phandle = < 0x79 >;
2446			};
2447		};
2448
2449		i2c5 {
2450
2451			i2c5-xfer {
2452				rockchip,pins = < 0x03 0x0b 0x02 0xa5 0x03 0x0a 0x02 0xa5 >;
2453				phandle = < 0x31 >;
2454			};
2455		};
2456
2457		i2c6 {
2458
2459			i2c6-xfer {
2460				rockchip,pins = < 0x02 0x0a 0x02 0xa5 0x02 0x09 0x02 0xa5 >;
2461				phandle = < 0x32 >;
2462			};
2463		};
2464
2465		i2c7 {
2466
2467			i2c7-xfer {
2468				rockchip,pins = < 0x02 0x08 0x02 0xa5 0x02 0x07 0x02 0xa5 >;
2469				phandle = < 0x33 >;
2470			};
2471		};
2472
2473		i2c8 {
2474
2475			i2c8-xfer {
2476				rockchip,pins = < 0x01 0x15 0x01 0xa5 0x01 0x14 0x01 0xa5 >;
2477				phandle = < 0x7c >;
2478			};
2479		};
2480
2481		i2s0 {
2482
2483			i2s0-2ch-bus {
2484				rockchip,pins = < 0x03 0x18 0x01 0xa5 0x03 0x19 0x01 0xa5 0x03 0x1a 0x01 0xa5 0x03 0x1b 0x01 0xa5 0x03 0x1f 0x01 0xa5 0x04 0x00 0x01 0xa5 >;
2485			};
2486
2487			i2s0-8ch-bus {
2488				rockchip,pins = < 0x03 0x18 0x01 0xa5 0x03 0x19 0x01 0xa5 0x03 0x1a 0x01 0xa5 0x03 0x1b 0x01 0xa5 0x03 0x1c 0x01 0xa5 0x03 0x1d 0x01 0xa5 0x03 0x1e 0x01 0xa5 0x03 0x1f 0x01 0xa5 0x04 0x00 0x01 0xa5 >;
2489				phandle = < 0x88 >;
2490			};
2491		};
2492
2493		i2s1 {
2494
2495			i2s1-2ch-bus {
2496				rockchip,pins = < 0x04 0x03 0x01 0xa5 0x04 0x04 0x01 0xa5 0x04 0x05 0x01 0xa5 0x04 0x06 0x01 0xa5 0x04 0x07 0x01 0xa5 >;
2497				phandle = < 0x89 >;
2498			};
2499		};
2500
2501		sdio0 {
2502
2503			sdio0-bus1 {
2504				rockchip,pins = < 0x02 0x14 0x01 0xa8 >;
2505			};
2506
2507			sdio0-bus4 {
2508				rockchip,pins = < 0x02 0x14 0x01 0xa8 0x02 0x15 0x01 0xa8 0x02 0x16 0x01 0xa8 0x02 0x17 0x01 0xa8 >;
2509			};
2510
2511			sdio0-cmd {
2512				rockchip,pins = < 0x02 0x18 0x01 0xa8 >;
2513			};
2514
2515			sdio0-clk {
2516				rockchip,pins = < 0x02 0x19 0x01 0xa5 >;
2517			};
2518
2519			sdio0-cd {
2520				rockchip,pins = < 0x02 0x1a 0x01 0xa8 >;
2521			};
2522
2523			sdio0-pwr {
2524				rockchip,pins = < 0x02 0x1b 0x01 0xa8 >;
2525			};
2526
2527			sdio0-bkpwr {
2528				rockchip,pins = < 0x02 0x1c 0x01 0xa8 >;
2529			};
2530
2531			sdio0-wp {
2532				rockchip,pins = < 0x00 0x03 0x01 0xa8 >;
2533			};
2534
2535			sdio0-int {
2536				rockchip,pins = < 0x00 0x04 0x01 0xa8 >;
2537			};
2538		};
2539
2540		sdmmc {
2541
2542			sdmmc-bus1 {
2543				rockchip,pins = < 0x04 0x08 0x01 0xa8 >;
2544			};
2545
2546			sdmmc-bus4 {
2547				rockchip,pins = < 0x04 0x08 0x01 0xa8 0x04 0x09 0x01 0xa8 0x04 0x0a 0x01 0xa8 0x04 0x0b 0x01 0xa8 >;
2548				phandle = < 0x1f >;
2549			};
2550
2551			sdmmc-clk {
2552				rockchip,pins = < 0x04 0x0c 0x01 0xa5 >;
2553				phandle = < 0x1d >;
2554			};
2555
2556			sdmmc-cmd {
2557				rockchip,pins = < 0x04 0x0d 0x01 0xa8 >;
2558				phandle = < 0x1e >;
2559			};
2560
2561			sdmmc-cd {
2562				rockchip,pins = < 0x00 0x07 0x01 0xa8 >;
2563			};
2564
2565			sdmmc-wp {
2566				rockchip,pins = < 0x00 0x08 0x01 0xa8 >;
2567			};
2568		};
2569
2570		sleep {
2571
2572			ap-pwroff {
2573				rockchip,pins = < 0x01 0x05 0x01 0xa5 >;
2574			};
2575
2576			ddrio-pwroff {
2577				rockchip,pins = < 0x00 0x01 0x01 0xa5 >;
2578			};
2579		};
2580
2581		spdif {
2582
2583			spdif-bus {
2584				rockchip,pins = < 0x04 0x15 0x01 0xa5 >;
2585				phandle = < 0x87 >;
2586			};
2587
2588			spdif-bus-1 {
2589				rockchip,pins = < 0x03 0x10 0x03 0xa5 >;
2590			};
2591		};
2592
2593		spi0 {
2594
2595			spi0-clk {
2596				rockchip,pins = < 0x03 0x06 0x02 0xa8 >;
2597				phandle = < 0x3a >;
2598			};
2599
2600			spi0-cs0 {
2601				rockchip,pins = < 0x03 0x07 0x02 0xa8 >;
2602				phandle = < 0x3d >;
2603			};
2604
2605			spi0-cs1 {
2606				rockchip,pins = < 0x03 0x08 0x02 0xa8 >;
2607			};
2608
2609			spi0-tx {
2610				rockchip,pins = < 0x03 0x05 0x02 0xa8 >;
2611				phandle = < 0x3b >;
2612			};
2613
2614			spi0-rx {
2615				rockchip,pins = < 0x03 0x04 0x02 0xa8 >;
2616				phandle = < 0x3c >;
2617			};
2618		};
2619
2620		spi1 {
2621
2622			spi1-clk {
2623				rockchip,pins = < 0x01 0x09 0x02 0xa8 >;
2624				phandle = < 0x3e >;
2625			};
2626
2627			spi1-cs0 {
2628				rockchip,pins = < 0x01 0x0a 0x02 0xa8 >;
2629				phandle = < 0x41 >;
2630			};
2631
2632			spi1-rx {
2633				rockchip,pins = < 0x01 0x07 0x02 0xa8 >;
2634				phandle = < 0x40 >;
2635			};
2636
2637			spi1-tx {
2638				rockchip,pins = < 0x01 0x08 0x02 0xa8 >;
2639				phandle = < 0x3f >;
2640			};
2641		};
2642
2643		spi2 {
2644
2645			spi2-clk {
2646				rockchip,pins = < 0x02 0x0b 0x01 0xa8 >;
2647				phandle = < 0x42 >;
2648			};
2649
2650			spi2-cs0 {
2651				rockchip,pins = < 0x02 0x0c 0x01 0xa8 >;
2652				phandle = < 0x45 >;
2653			};
2654
2655			spi2-rx {
2656				rockchip,pins = < 0x02 0x09 0x01 0xa8 >;
2657				phandle = < 0x44 >;
2658			};
2659
2660			spi2-tx {
2661				rockchip,pins = < 0x02 0x0a 0x01 0xa8 >;
2662				phandle = < 0x43 >;
2663			};
2664		};
2665
2666		spi3 {
2667
2668			spi3-clk {
2669				rockchip,pins = < 0x01 0x11 0x01 0xa8 >;
2670				phandle = < 0x6c >;
2671			};
2672
2673			spi3-cs0 {
2674				rockchip,pins = < 0x01 0x12 0x01 0xa8 >;
2675				phandle = < 0x6f >;
2676			};
2677
2678			spi3-rx {
2679				rockchip,pins = < 0x01 0x0f 0x01 0xa8 >;
2680				phandle = < 0x6e >;
2681			};
2682
2683			spi3-tx {
2684				rockchip,pins = < 0x01 0x10 0x01 0xa8 >;
2685				phandle = < 0x6d >;
2686			};
2687		};
2688
2689		spi4 {
2690
2691			spi4-clk {
2692				rockchip,pins = < 0x03 0x02 0x02 0xa8 >;
2693				phandle = < 0x46 >;
2694			};
2695
2696			spi4-cs0 {
2697				rockchip,pins = < 0x03 0x03 0x02 0xa8 >;
2698				phandle = < 0x49 >;
2699			};
2700
2701			spi4-rx {
2702				rockchip,pins = < 0x03 0x00 0x02 0xa8 >;
2703				phandle = < 0x48 >;
2704			};
2705
2706			spi4-tx {
2707				rockchip,pins = < 0x03 0x01 0x02 0xa8 >;
2708				phandle = < 0x47 >;
2709			};
2710		};
2711
2712		spi5 {
2713
2714			spi5-clk {
2715				rockchip,pins = < 0x02 0x16 0x02 0xa8 >;
2716				phandle = < 0x4b >;
2717			};
2718
2719			spi5-cs0 {
2720				rockchip,pins = < 0x02 0x17 0x02 0xa8 >;
2721				phandle = < 0x4e >;
2722			};
2723
2724			spi5-rx {
2725				rockchip,pins = < 0x02 0x14 0x02 0xa8 >;
2726				phandle = < 0x4d >;
2727			};
2728
2729			spi5-tx {
2730				rockchip,pins = < 0x02 0x15 0x02 0xa8 >;
2731				phandle = < 0x4c >;
2732			};
2733		};
2734
2735		testclk {
2736
2737			test-clkout0 {
2738				rockchip,pins = < 0x00 0x00 0x01 0xa5 >;
2739			};
2740
2741			test-clkout1 {
2742				rockchip,pins = < 0x02 0x19 0x02 0xa5 >;
2743			};
2744
2745			test-clkout2 {
2746				rockchip,pins = < 0x00 0x08 0x03 0xa5 >;
2747			};
2748		};
2749
2750		tsadc {
2751
2752			otp-gpio {
2753				rockchip,pins = < 0x01 0x06 0x00 0xa5 >;
2754				phandle = < 0x53 >;
2755			};
2756
2757			otp-out {
2758				rockchip,pins = < 0x01 0x06 0x01 0xa5 >;
2759				phandle = < 0x54 >;
2760			};
2761		};
2762
2763		uart0 {
2764
2765			uart0-xfer {
2766				rockchip,pins = < 0x02 0x10 0x01 0xa8 0x02 0x11 0x01 0xa5 >;
2767				phandle = < 0x34 >;
2768			};
2769
2770			uart0-cts {
2771				rockchip,pins = < 0x02 0x12 0x01 0xa5 >;
2772				phandle = < 0x35 >;
2773			};
2774
2775			uart0-rts {
2776				rockchip,pins = < 0x02 0x13 0x01 0xa5 >;
2777			};
2778		};
2779
2780		uart1 {
2781
2782			uart1-xfer {
2783				rockchip,pins = < 0x03 0x0c 0x02 0xa8 0x03 0x0d 0x02 0xa5 >;
2784				phandle = < 0x36 >;
2785			};
2786		};
2787
2788		uart2a {
2789
2790			uart2a-xfer {
2791				rockchip,pins = < 0x04 0x08 0x02 0xa8 0x04 0x09 0x02 0xa5 >;
2792			};
2793		};
2794
2795		uart2b {
2796
2797			uart2b-xfer {
2798				rockchip,pins = < 0x04 0x10 0x02 0xa8 0x04 0x11 0x02 0xa5 >;
2799			};
2800		};
2801
2802		uart2c {
2803
2804			uart2c-xfer {
2805				rockchip,pins = < 0x04 0x13 0x01 0xa8 0x04 0x14 0x01 0xa5 >;
2806				phandle = < 0x37 >;
2807			};
2808		};
2809
2810		uart3 {
2811
2812			uart3-xfer {
2813				rockchip,pins = < 0x03 0x0e 0x02 0xa8 0x03 0x0f 0x02 0xa5 >;
2814				phandle = < 0x38 >;
2815			};
2816
2817			uart3-cts {
2818				rockchip,pins = < 0x03 0x10 0x02 0xa5 >;
2819			};
2820
2821			uart3-rts {
2822				rockchip,pins = < 0x03 0x11 0x02 0xa5 >;
2823			};
2824		};
2825
2826		uart4 {
2827
2828			uart4-xfer {
2829				rockchip,pins = < 0x01 0x07 0x01 0xa8 0x01 0x08 0x01 0xa5 >;
2830				phandle = < 0x70 >;
2831			};
2832		};
2833
2834		uarthdcp {
2835
2836			uarthdcp-xfer {
2837				rockchip,pins = < 0x04 0x15 0x02 0xa8 0x04 0x16 0x02 0xa5 >;
2838			};
2839		};
2840
2841		pwm0 {
2842
2843			pwm0-pin {
2844				rockchip,pins = < 0x04 0x12 0x01 0xa5 >;
2845				phandle = < 0x7d >;
2846			};
2847
2848			pwm0-pin-pull-down {
2849				rockchip,pins = < 0x04 0x12 0x01 0xa9 >;
2850			};
2851
2852			vop0-pwm-pin {
2853				rockchip,pins = < 0x04 0x12 0x02 0xa5 >;
2854			};
2855
2856			vop1-pwm-pin {
2857				rockchip,pins = < 0x04 0x12 0x03 0xa5 >;
2858			};
2859		};
2860
2861		pwm1 {
2862
2863			pwm1-pin {
2864				rockchip,pins = < 0x04 0x16 0x01 0xa5 >;
2865				phandle = < 0x7e >;
2866			};
2867
2868			pwm1-pin-pull-down {
2869				rockchip,pins = < 0x04 0x16 0x01 0xa9 >;
2870			};
2871		};
2872
2873		pwm2 {
2874
2875			pwm2-pin {
2876				rockchip,pins = < 0x01 0x13 0x01 0xa5 >;
2877				phandle = < 0x7f >;
2878			};
2879
2880			pwm2-pin-pull-down {
2881				rockchip,pins = < 0x01 0x13 0x01 0xa9 >;
2882			};
2883		};
2884
2885		pwm3a {
2886
2887			pwm3a-pin {
2888				rockchip,pins = < 0x00 0x06 0x01 0xa5 >;
2889				phandle = < 0x80 >;
2890			};
2891		};
2892
2893		pwm3b {
2894
2895			pwm3b-pin {
2896				rockchip,pins = < 0x01 0x0e 0x01 0xa5 >;
2897			};
2898		};
2899
2900		hdmi {
2901
2902			hdmi-i2c-xfer {
2903				rockchip,pins = < 0x04 0x11 0x03 0xa5 0x04 0x10 0x03 0xa5 >;
2904			};
2905
2906			hdmi-cec {
2907				rockchip,pins = < 0x04 0x17 0x01 0xa5 >;
2908				phandle = < 0x99 >;
2909			};
2910		};
2911
2912		pcie {
2913
2914			pci-clkreqn-cpm {
2915				rockchip,pins = < 0x02 0x1a 0x00 0xa5 >;
2916			};
2917
2918			pci-clkreqnb-cpm {
2919				rockchip,pins = < 0x04 0x18 0x00 0xa5 >;
2920			};
2921
2922			pcie-pwr-en {
2923				rockchip,pins = < 0x01 0x18 0x00 0xa5 >;
2924				phandle = < 0xb0 >;
2925			};
2926		};
2927
2928		buttons {
2929
2930			pwrbtn {
2931				rockchip,pins = < 0x00 0x05 0x00 0xa8 >;
2932				phandle = < 0xaa >;
2933			};
2934		};
2935
2936		fusb302x {
2937
2938			fusb0-int {
2939				rockchip,pins = < 0x01 0x02 0x00 0xa8 >;
2940				phandle = < 0x7a >;
2941			};
2942		};
2943
2944		leds {
2945
2946			work_led-gpio {
2947				rockchip,pins = < 0x00 0x0b 0x00 0xa5 >;
2948				phandle = < 0xab >;
2949			};
2950
2951			diy_led-gpio {
2952				rockchip,pins = < 0x00 0x02 0x00 0xa5 >;
2953				phandle = < 0xac >;
2954			};
2955		};
2956
2957		pmic {
2958
2959			pmic-int-l {
2960				rockchip,pins = < 0x01 0x15 0x00 0xa8 >;
2961				phandle = < 0x73 >;
2962			};
2963
2964			vsel1-gpio {
2965				rockchip,pins = < 0x01 0x11 0x00 0xa9 >;
2966				phandle = < 0x77 >;
2967			};
2968
2969			vsel2-gpio {
2970				rockchip,pins = < 0x01 0x0e 0x00 0xa9 >;
2971				phandle = < 0x78 >;
2972			};
2973		};
2974
2975		sdio-pwrseq {
2976
2977			wifi-enable-h {
2978				rockchip,pins = < 0x00 0x0a 0x00 0xa5 >;
2979				phandle = < 0xae >;
2980			};
2981		};
2982
2983		usb-typec {
2984
2985			vcc5v0_typec_en {
2986				rockchip,pins = < 0x01 0x03 0x00 0xa8 >;
2987				phandle = < 0xb5 >;
2988			};
2989		};
2990
2991		usb2 {
2992
2993			vcc5v0-host-en {
2994				rockchip,pins = < 0x04 0x1a 0x00 0xa5 >;
2995				phandle = < 0xb3 >;
2996			};
2997		};
2998	};
2999
3000	opp-table0 {
3001		compatible = "operating-points-v2";
3002		opp-shared;
3003		phandle = < 0x0b >;
3004
3005		opp00 {
3006			opp-hz = < 0x00 0x18519600 >;
3007			opp-microvolt = < 0xc3500 >;
3008			clock-latency-ns = < 0x9c40 >;
3009		};
3010
3011		opp01 {
3012			opp-hz = < 0x00 0x23c34600 >;
3013			opp-microvolt = < 0xc3500 >;
3014		};
3015
3016		opp02 {
3017			opp-hz = < 0x00 0x30a32c00 >;
3018			opp-microvolt = < 0xcf850 >;
3019		};
3020
3021		opp03 {
3022			opp-hz = < 0x00 0x3c14dc00 >;
3023			opp-microvolt = < 0xe1d48 >;
3024		};
3025
3026		opp04 {
3027			opp-hz = < 0x00 0x47868c00 >;
3028			opp-microvolt = < 0xf4240 >;
3029		};
3030
3031		opp05 {
3032			opp-hz = < 0x00 0x54667200 >;
3033			opp-microvolt = < 0x112a88 >;
3034		};
3035	};
3036
3037	opp-table1 {
3038		compatible = "operating-points-v2";
3039		opp-shared;
3040		phandle = < 0x0d >;
3041
3042		opp00 {
3043			opp-hz = < 0x00 0x18519600 >;
3044			opp-microvolt = < 0xc3500 >;
3045			clock-latency-ns = < 0x9c40 >;
3046		};
3047
3048		opp01 {
3049			opp-hz = < 0x00 0x23c34600 >;
3050			opp-microvolt = < 0xc3500 >;
3051		};
3052
3053		opp02 {
3054			opp-hz = < 0x00 0x30a32c00 >;
3055			opp-microvolt = < 0xc96a8 >;
3056		};
3057
3058		opp03 {
3059			opp-hz = < 0x00 0x3c14dc00 >;
3060			opp-microvolt = < 0xd59f8 >;
3061		};
3062
3063		opp04 {
3064			opp-hz = < 0x00 0x47868c00 >;
3065			opp-microvolt = < 0xe7ef0 >;
3066		};
3067
3068		opp05 {
3069			opp-hz = < 0x00 0x54667200 >;
3070			opp-microvolt = < 0xfa3e8 >;
3071		};
3072
3073		opp06 {
3074			opp-hz = < 0x00 0x5fd82200 >;
3075			opp-microvolt = < 0x10c8e0 >;
3076		};
3077
3078		opp07 {
3079			opp-hz = < 0x00 0x6b49d200 >;
3080			opp-microvolt = < 0x124f80 >;
3081		};
3082	};
3083
3084	opp-table2 {
3085		compatible = "operating-points-v2";
3086		phandle = < 0xa3 >;
3087
3088		opp00 {
3089			opp-hz = < 0x00 0xbebc200 >;
3090			opp-microvolt = < 0xc3500 >;
3091		};
3092
3093		opp01 {
3094			opp-hz = < 0x00 0x11b3dc40 >;
3095			opp-microvolt = < 0xc3500 >;
3096		};
3097
3098		opp02 {
3099			opp-hz = < 0x00 0x17d78400 >;
3100			opp-microvolt = < 0xc96a8 >;
3101		};
3102
3103		opp03 {
3104			opp-hz = < 0x00 0x1dcd6500 >;
3105			opp-microvolt = < 0xd59f8 >;
3106		};
3107
3108		opp04 {
3109			opp-hz = < 0x00 0x23c34600 >;
3110			opp-microvolt = < 0xe1d48 >;
3111		};
3112
3113		opp05 {
3114			opp-hz = < 0x00 0x2faf0800 >;
3115			opp-microvolt = < 0x10c8e0 >;
3116		};
3117	};
3118
3119	chosen {
3120		stdout-path = "serial2:1500000n8";
3121	};
3122
3123	external-gmac-clock {
3124		compatible = "fixed-clock";
3125		clock-frequency = < 0x7735940 >;
3126		clock-output-names = "clkin_gmac";
3127		#clock-cells = < 0x00 >;
3128		phandle = < 0x18 >;
3129	};
3130
3131	gpio-keys {
3132		compatible = "gpio-keys";
3133		autorepeat;
3134		pinctrl-names = "default";
3135		pinctrl-0 = < 0xaa >;
3136
3137		power {
3138			debounce-interval = < 0x64 >;
3139			gpios = < 0x1c 0x05 0x01 >;
3140			label = "GPIO Key Power";
3141			linux,code = < 0x74 >;
3142			wakeup-source;
3143		};
3144	};
3145
3146	leds {
3147		compatible = "gpio-leds";
3148		pinctrl-names = "default";
3149		pinctrl-0 = < 0xab 0xac >;
3150
3151		work-led {
3152			label = "work";
3153			default-state = "on";
3154			gpios = < 0x1c 0x0b 0x00 >;
3155		};
3156
3157		diy-led {
3158			label = "diy";
3159			default-state = "off";
3160			gpios = < 0x1c 0x02 0x00 >;
3161		};
3162	};
3163
3164	sdio-pwrseq {
3165		compatible = "mmc-pwrseq-simple";
3166		clocks = < 0xad 0x01 >;
3167		clock-names = "ext_clock";
3168		pinctrl-names = "default";
3169		pinctrl-0 = < 0xae >;
3170		reset-gpios = < 0x1c 0x0a 0x01 >;
3171	};
3172
3173	vcc12v-dcin {
3174		compatible = "regulator-fixed";
3175		regulator-name = "vcc12v_dcin";
3176		regulator-always-on;
3177		regulator-boot-on;
3178		regulator-min-microvolt = < 0xb71b00 >;
3179		regulator-max-microvolt = < 0xb71b00 >;
3180		phandle = < 0xb1 >;
3181	};
3182
3183	vcc1v8-s3 {
3184		compatible = "regulator-fixed";
3185		regulator-name = "vcc1v8_s3";
3186		regulator-always-on;
3187		regulator-boot-on;
3188		regulator-min-microvolt = < 0x1b7740 >;
3189		regulator-max-microvolt = < 0x1b7740 >;
3190		vin-supply = < 0xaf >;
3191		phandle = < 0x2d >;
3192	};
3193
3194	vcc3v3-pcie-regulator {
3195		compatible = "regulator-fixed";
3196		enable-active-high;
3197		gpio = < 0x72 0x18 0x00 >;
3198		pinctrl-names = "default";
3199		pinctrl-0 = < 0xb0 >;
3200		regulator-name = "vcc3v3_pcie";
3201		regulator-always-on;
3202		regulator-boot-on;
3203		vin-supply = < 0xb1 >;
3204	};
3205
3206	vcc3v3-sys {
3207		compatible = "regulator-fixed";
3208		regulator-name = "vcc3v3_sys";
3209		regulator-always-on;
3210		regulator-boot-on;
3211		regulator-min-microvolt = < 0x325aa0 >;
3212		regulator-max-microvolt = < 0x325aa0 >;
3213		vin-supply = < 0x74 >;
3214		phandle = < 0x75 >;
3215	};
3216
3217	vcc5v0-host-regulator {
3218		compatible = "regulator-fixed";
3219		enable-active-high;
3220		gpio = < 0xb2 0x1a 0x00 >;
3221		pinctrl-names = "default";
3222		pinctrl-0 = < 0xb3 >;
3223		regulator-name = "vcc5v0_host";
3224		regulator-always-on;
3225		vin-supply = < 0xb4 >;
3226		phandle = < 0x85 >;
3227	};
3228
3229	vcc5v0-typec-regulator {
3230		compatible = "regulator-fixed";
3231		enable-active-high;
3232		gpio = < 0x72 0x03 0x00 >;
3233		pinctrl-names = "default";
3234		pinctrl-0 = < 0xb5 >;
3235		regulator-name = "vcc5v0_typec";
3236		regulator-always-on;
3237		vin-supply = < 0xb4 >;
3238		phandle = < 0x7b >;
3239	};
3240
3241	vcc5v0-sys {
3242		compatible = "regulator-fixed";
3243		regulator-name = "vcc5v0_sys";
3244		regulator-always-on;
3245		regulator-boot-on;
3246		regulator-min-microvolt = < 0x4c4b40 >;
3247		regulator-max-microvolt = < 0x4c4b40 >;
3248		vin-supply = < 0xb1 >;
3249		phandle = < 0x74 >;
3250	};
3251
3252	vcc5v0-usb {
3253		compatible = "regulator-fixed";
3254		regulator-name = "vcc5v0_usb";
3255		regulator-always-on;
3256		regulator-boot-on;
3257		regulator-min-microvolt = < 0x4c4b40 >;
3258		regulator-max-microvolt = < 0x4c4b40 >;
3259		vin-supply = < 0xb1 >;
3260		phandle = < 0xb4 >;
3261	};
3262
3263	vdd-log {
3264		compatible = "pwm-regulator";
3265		pwms = < 0xb6 0x00 0x61a8 0x01 >;
3266		regulator-name = "vdd_log";
3267		regulator-always-on;
3268		regulator-boot-on;
3269		regulator-min-microvolt = < 0xc3500 >;
3270		regulator-max-microvolt = < 0x155cc0 >;
3271		vin-supply = < 0x74 >;
3272	};
3273};
3274