1/* SPDX-License-Identifier: GPL-2.0-only or MIT */ 2/* Copyright (c) 2019-2020 Microchip Technology Inc. */ 3 4/dts-v1/; 5/ { 6 #address-cells = <2>; 7 #size-cells = <2>; 8 compatible = "SiFive,FU540G-dev", "fu540-dev", "sifive-dev"; 9 model = "SiFive,FU540G"; 10 L45: cpus { 11 #address-cells = <1>; 12 #size-cells = <0>; 13 timebase-frequency = <1000000>; 14 L8: cpu@0 { 15 clock-frequency = <0>; 16 compatible = "sifive,rocket0", "riscv"; 17 device_type = "cpu"; 18 i-cache-block-size = <64>; 19 i-cache-sets = <128>; 20 i-cache-size = <16384>; 21 next-level-cache = <&L0 &L26>; 22 reg = <0>; 23 riscv,isa = "rv64imac"; 24 sifive,dtim = <&L6>; 25 sifive,itim = <&L5>; 26 status = "okay"; 27 L4: interrupt-controller { 28 #interrupt-cells = <1>; 29 compatible = "riscv,cpu-intc"; 30 interrupt-controller; 31 }; 32 }; 33 L12: cpu@1 { 34 clock-frequency = <0>; 35 compatible = "sifive,rocket0", "riscv"; 36 d-cache-block-size = <64>; 37 d-cache-sets = <64>; 38 d-cache-size = <32768>; 39 d-tlb-sets = <1>; 40 d-tlb-size = <32>; 41 device_type = "cpu"; 42 i-cache-block-size = <64>; 43 i-cache-sets = <64>; 44 i-cache-size = <32768>; 45 i-tlb-sets = <1>; 46 i-tlb-size = <32>; 47 mmu-type = "riscv,sv39"; 48 next-level-cache = <&L0 &L26>; 49 reg = <1>; 50 riscv,isa = "rv64imafdc"; 51 sifive,itim = <&L10>; 52 status = "okay"; 53 tlb-split; 54 L9: interrupt-controller { 55 #interrupt-cells = <1>; 56 compatible = "riscv,cpu-intc"; 57 interrupt-controller; 58 }; 59 }; 60 L16: cpu@2 { 61 clock-frequency = <0>; 62 compatible = "sifive,rocket0", "riscv"; 63 d-cache-block-size = <64>; 64 d-cache-sets = <64>; 65 d-cache-size = <32768>; 66 d-tlb-sets = <1>; 67 d-tlb-size = <32>; 68 device_type = "cpu"; 69 i-cache-block-size = <64>; 70 i-cache-sets = <64>; 71 i-cache-size = <32768>; 72 i-tlb-sets = <1>; 73 i-tlb-size = <32>; 74 mmu-type = "riscv,sv39"; 75 next-level-cache = <&L0 &L26>; 76 reg = <2>; 77 riscv,isa = "rv64imafdc"; 78 sifive,itim = <&L14>; 79 status = "okay"; 80 tlb-split; 81 L13: interrupt-controller { 82 #interrupt-cells = <1>; 83 compatible = "riscv,cpu-intc"; 84 interrupt-controller; 85 }; 86 }; 87 L20: cpu@3 { 88 clock-frequency = <0>; 89 compatible = "sifive,rocket0", "riscv"; 90 d-cache-block-size = <64>; 91 d-cache-sets = <64>; 92 d-cache-size = <32768>; 93 d-tlb-sets = <1>; 94 d-tlb-size = <32>; 95 device_type = "cpu"; 96 i-cache-block-size = <64>; 97 i-cache-sets = <64>; 98 i-cache-size = <32768>; 99 i-tlb-sets = <1>; 100 i-tlb-size = <32>; 101 mmu-type = "riscv,sv39"; 102 next-level-cache = <&L0 &L26>; 103 reg = <3>; 104 riscv,isa = "rv64imafdc"; 105 sifive,itim = <&L18>; 106 status = "okay"; 107 tlb-split; 108 L17: interrupt-controller { 109 #interrupt-cells = <1>; 110 compatible = "riscv,cpu-intc"; 111 interrupt-controller; 112 }; 113 }; 114 L24: cpu@4 { 115 clock-frequency = <0>; 116 compatible = "sifive,rocket0", "riscv"; 117 d-cache-block-size = <64>; 118 d-cache-sets = <64>; 119 d-cache-size = <32768>; 120 d-tlb-sets = <1>; 121 d-tlb-size = <32>; 122 device_type = "cpu"; 123 i-cache-block-size = <64>; 124 i-cache-sets = <64>; 125 i-cache-size = <32768>; 126 i-tlb-sets = <1>; 127 i-tlb-size = <32>; 128 mmu-type = "riscv,sv39"; 129 next-level-cache = <&L0 &L26>; 130 reg = <4>; 131 riscv,isa = "rv64imafdc"; 132 sifive,itim = <&L22>; 133 status = "okay"; 134 tlb-split; 135 L21: interrupt-controller { 136 #interrupt-cells = <1>; 137 compatible = "riscv,cpu-intc"; 138 interrupt-controller; 139 }; 140 }; 141 }; 142 L40: memory@80000000 { 143 device_type = "memory"; 144 reg = <0x0 0x80000000 0x0 0x40000000>; 145 clocks = <&clkcfg 26>; 146 }; 147 L44: soc { 148 #address-cells = <2>; 149 #size-cells = <2>; 150 compatible = "SiFive,FU540G-soc", "fu540-soc", "sifive-soc", "simple-bus"; 151 ranges; 152 L7: bus-error-unit@1700000 { 153 compatible = "sifive,buserror0"; 154 interrupt-parent = <&L1>; 155 interrupts = <182>; 156 reg = <0x0 0x1700000 0x0 0x1000>; 157 reg-names = "control"; 158 }; 159 L11: bus-error-unit@1701000 { 160 compatible = "sifive,buserror0"; 161 interrupt-parent = <&L1>; 162 interrupts = <183>; 163 reg = <0x0 0x1701000 0x0 0x1000>; 164 reg-names = "control"; 165 }; 166 L15: bus-error-unit@1702000 { 167 compatible = "sifive,buserror0"; 168 interrupt-parent = <&L1>; 169 interrupts = <184>; 170 reg = <0x0 0x1702000 0x0 0x1000>; 171 reg-names = "control"; 172 }; 173 L19: bus-error-unit@1703000 { 174 compatible = "sifive,buserror0"; 175 interrupt-parent = <&L1>; 176 interrupts = <185>; 177 reg = <0x0 0x1703000 0x0 0x1000>; 178 reg-names = "control"; 179 }; 180 L23: bus-error-unit@1704000 { 181 compatible = "sifive,buserror0"; 182 interrupt-parent = <&L1>; 183 interrupts = <186>; 184 reg = <0x0 0x1704000 0x0 0x1000>; 185 reg-names = "control"; 186 }; 187 L0: cache-controller@2010000 { 188 cache-block-size = <64>; 189 cache-level = <2>; 190 cache-sets = <2048>; 191 cache-size = <2097152>; 192 cache-unified; 193 compatible = "sifive,ccache0", "cache"; 194 interrupt-parent = <&L1>; 195 interrupts = <1 2 3 4>; 196 next-level-cache = <&L40 &L42>; 197 reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x200000>; 198 reg-names = "control", "sideband"; 199 }; 200 L2: clint@2000000 { 201 compatible = "riscv,clint0"; 202 interrupts-extended = <&L4 3 &L4 7 &L9 3 &L9 7 &L13 3 &L13 7 &L17 3 &L17 7 &L21 3 &L21 7>; 203 reg = <0x0 0x2000000 0x0 0x10000>; 204 reg-names = "control"; 205 }; 206 L35: cplex_d0@20000000 { 207 #address-cells = <1>; 208 #size-cells = <1>; 209 compatible = "simple-bus"; 210 ranges = <0x20000000 0x0 0x20000000 0x8000000 0x30000000 0x0 0x30000000 0x30000000>; 211 }; 212 L36: cplex_d1@28000000 { 213 #address-cells = <1>; 214 #size-cells = <1>; 215 compatible = "simple-bus"; 216 ranges = <0x28000000 0x0 0x28000000 0x8000000>; 217 }; 218 L37: cplex_f0@60000000 { 219 #address-cells = <2>; 220 #size-cells = <2>; 221 compatible = "simple-bus"; 222 ranges = <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000 0x20 0x0 0x20 0x0 0x10 0x0>; 223 }; 224 L38: cplex_f1@e0000000 { 225 #address-cells = <2>; 226 #size-cells = <2>; 227 compatible = "simple-bus"; 228 ranges = <0x0 0xe0000000 0x0 0xe0000000 0x0 0x20000000 0x30 0x0 0x30 0x0 0x10 0x0>; 229 }; 230 L39: cplex_ncache@c0000000 { 231 #address-cells = <2>; 232 #size-cells = <2>; 233 compatible = "simple-bus"; 234 ranges = <0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000 0x14 0x0 0x14 0x0 0x8 0x0>; 235 }; 236 L3: debug-controller@0 { 237 compatible = "sifive,debug-013", "riscv,debug-013"; 238 interrupts-extended = <&L4 65535 &L9 65535 &L13 65535 &L17 65535 &L21 65535>; 239 reg = <0x0 0x0 0x0 0x1000>; 240 reg-names = "control"; 241 }; 242 L27: dma@3000000 { 243 #dma-cells = <1>; 244 compatible = "riscv,dma0"; 245 dma-channels = <4>; 246 dma-requests = <0>; 247 interrupt-parent = <&L1>; 248 interrupts = <5 6 7 8 9 10 11 12>; 249 reg = <0x0 0x3000000 0x0 0x100000>; 250 reg-names = "control"; 251 riscv,dma-pools = <1>; 252 }; 253 L6: dtim@1000000 { 254 compatible = "sifive,dtim0"; 255 reg = <0x0 0x1000000 0x0 0x2000>; 256 reg-names = "mem"; 257 }; 258 L26: error-device@18000000 { 259 compatible = "sifive,error0"; 260 reg = <0x0 0x18000000 0x0 0x8000000>; 261 reg-names = "mem"; 262 }; 263 L28: global-external-interrupts { 264 interrupt-parent = <&L1>; 265 interrupts = <13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181>; 266 }; 267 L1: interrupt-controller@c000000 { 268 #interrupt-cells = <1>; 269 compatible = "riscv,plic0"; 270 interrupt-controller; 271 interrupts-extended = <&L4 11 &L9 11 &L9 9 &L13 11 &L13 9 &L17 11 &L17 9 &L21 11 &L21 9>; 272 reg = <0x0 0xc000000 0x0 0x4000000>; 273 reg-names = "control"; 274 riscv,max-priority = <7>; 275 riscv,ndev = <186>; 276 }; 277 L5: itim@1800000 { 278 compatible = "sifive,itim0"; 279 reg = <0x0 0x1800000 0x0 0x4000>; 280 reg-names = "mem"; 281 }; 282 L10: itim@1808000 { 283 compatible = "sifive,itim0"; 284 reg = <0x0 0x1808000 0x0 0x8000>; 285 reg-names = "mem"; 286 }; 287 L14: itim@1810000 { 288 compatible = "sifive,itim0"; 289 reg = <0x0 0x1810000 0x0 0x8000>; 290 reg-names = "mem"; 291 }; 292 L18: itim@1818000 { 293 compatible = "sifive,itim0"; 294 reg = <0x0 0x1818000 0x0 0x8000>; 295 reg-names = "mem"; 296 }; 297 L22: itim@1820000 { 298 compatible = "sifive,itim0"; 299 reg = <0x0 0x1820000 0x0 0x8000>; 300 reg-names = "mem"; 301 }; 302 L29: local-external-interrupts-0 { 303 interrupt-parent = <&L4>; 304 interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63>; 305 }; 306 L30: local-external-interrupts-1 { 307 interrupt-parent = <&L9>; 308 interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63>; 309 }; 310 L31: local-external-interrupts-2 { 311 interrupt-parent = <&L13>; 312 interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63>; 313 }; 314 L32: local-external-interrupts-3 { 315 interrupt-parent = <&L17>; 316 interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63>; 317 }; 318 L33: local-external-interrupts-4 { 319 interrupt-parent = <&L21>; 320 interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63>; 321 }; 322 L42: rom@a000000 { 323 compatible = "ucbbar,cacheable-zero0"; 324 reg = <0x0 0xa000000 0x0 0x2000000>; 325 reg-names = "mem"; 326 }; 327 L25: teststatus@4000 { 328 compatible = "sifive,test0"; 329 reg = <0x0 0x4000 0x0 0x1000>; 330 reg-names = "control"; 331 }; 332 L41: wcb@2020000 { 333 compatible = "sifive,wcb0"; 334 reg = <0x0 0x2020000 0x0 0x1000>; 335 reg-names = "control"; 336 }; 337 }; 338 339 chosen { 340 stdout-path = "/serial@20000000:115200n8"; 341 bootargs = "console=ttyS0,115200n8 "; 342 }; 343 344 refclk: refclk { 345 compatible = "fixed-clock"; 346 #clock-cells = <0>; 347 clock-frequency = <600000000>; 348 clock-output-names = "msspllclk"; 349 }; 350 351 clkcfg: clkcfg@20002000 { 352 compatible = "microchip,pfsoc-clkcfg"; 353 reg = <0x0 0x20002000 0x0 0x1000>; 354 reg-names = "mss_sysreg"; 355 clocks = <&refclk>; 356 #clock-cells = <1>; 357 clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", "MMUART2clk", "MMUART3clk", "MMUART4clk", "SPI0clk", "SPI1clk", "I2C0clk", "I2C1clk", "CAN0clk", "CAN1clk", "USBclk", "RESERVED", "RTCclk", "QSPIclk", "GPIO0clk", "GPIO1clk", "GPIO2clk", "DDRCclk", "FIC0clk", "FIC1clk", "FIC2clk", "FIC3clk", "ATHENAclk", "CFMclk"; 358 }; 359 360 serial0: serial@20000000 { 361 compatible = "ns16550a"; 362 reg = <0x0 0x20000000 0x0 0x400>; 363 reg-io-width = <4>; 364 reg-shift = <2>; 365 interrupt-parent = <&L1>; 366 interrupts = <90>; 367 current-speed = <115200>; 368 clock-frequency = <150000000>; 369 clocks = <&clkcfg 8>; 370 status = "okay"; 371 }; 372 373 serial1: serial@20100000 { 374 compatible = "ns16550a"; 375 reg = <0x0 0x20100000 0x0 0x400>; 376 reg-io-width = <4>; 377 reg-shift = <2>; 378 interrupt-parent = <&L1>; 379 interrupts = <91>; 380 current-speed = <115200>; 381 clocks = <&clkcfg 9>; 382 status = "okay"; 383 }; 384 serial2: serial@20102000 { 385 compatible = "ns16550a"; 386 reg = <0x0 0x20102000 0x0 0x400>; 387 reg-io-width = <4>; 388 reg-shift = <2>; 389 interrupt-parent = <&L1>; 390 interrupts = <92>; 391 current-speed = <115200>; 392 clocks = <&clkcfg 10>; 393 status = "okay"; 394 }; 395 serial3: serial@20104000 { 396 compatible = "ns16550a"; 397 reg = <0x0 0x20104000 0x0 0x400>; 398 reg-io-width = <4>; 399 reg-shift = <2>; 400 interrupt-parent = <&L1>; 401 interrupts = <93>; 402 current-speed = <115200>; 403 clocks = <&clkcfg 11>; 404 status = "okay"; 405 }; 406 407/* emmc: sdhc@20008000 { 408 compatible = "cdns,sd4hc"; 409 reg = <0x0 0x20008000 0x0 0x1000>; 410 interrupt-parent = <&L1>; 411 interrupts = <88>; 412 pinctrl-names = "default"; 413 clocks = <&clkcfg 6>; 414 bus-width = <4>; 415 cap-mmc-highspeed; 416 max-frequency = <200000000>; 417 };*/ 418/* 419 sdcard: sdhc@20008000 { 420 compatible = "cdns,sd4hc"; 421 reg = <0x0 0x20008000 0x0 0x1000>; 422 interrupt-parent = <&L1>; 423 interrupts = <88>; 424 pinctrl-names = "default"; 425 clocks = <&clkcfg 6>; 426 bus-width = <4>; 427 cap-sd-highspeed; 428 max-frequency = <200000000>; 429 }; 430*/ 431 432/* emac0: ethernet@20110000 { 433 compatible = "cdns,macb"; 434 reg = <0x0 0x20110000 0x0 0x2000>; 435 interrupt-parent = <&L1>; 436 interrupts = <64 65 66 67>; 437 mac-address = [56 34 12 00 FC 00]; 438 phy-mode = "sgmii"; 439 clocks = <&clkcfg 4>, <&clkcfg 1>; 440 clock-names = "pclk", "hclk"; 441 #address-cells = <1>; 442 #size-cells = <0>; 443 phy1: ethernet-phy@8 { 444 reg = <8>; 445 ti,fifo-depth = <0x01>; 446 }; 447 }; 448*/ 449 emac1: ethernet@20112000 { 450 compatible = "cdns,macb"; 451 reg = <0x0 0x20112000 0x0 0x2000>; 452 interrupt-parent = <&L1>; 453 interrupts = <70 71 72 73>; 454 mac-address = [56 34 12 00 FC 00]; 455 phy-mode = "sgmii"; 456 clocks = <&clkcfg 5>, <&clkcfg 2>; 457 clock-names = "pclk", "hclk"; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 phy1: ethernet-phy@9 { 461 reg = <9>; 462 ti,fifo-depth = <0x01>; 463 }; 464 }; 465 466 timer0: timer@20125000 { 467 compatible = "timer"; 468 reg = <0x0 20125000 0x0 0x400>; 469 interrupt-parent = <&L1>; 470 interrupts = <82 83>; 471 timer-width = < 0x20 >; 472 }; 473 474}; 475