1/* 2 * Copyright Linux Kernel Team 3 * 4 * SPDX-License-Identifier: GPL-2.0-only 5 * 6 * This file is derived from an intermediate build stage of the 7 * Linux kernel. The licenses of all input files to this process 8 * are compatible with GPL-2.0-only. 9 */ 10 11/dts-v1/; 12 13/ { 14 #address-cells = < 0x01 >; 15 #size-cells = < 0x01 >; 16 model = "Freescale i.MX7 SabreSD Board"; 17 compatible = "fsl,imx7d-sdb\0fsl,imx7d"; 18 19 chosen { 20 stdout-path = "/soc/aips-bus@30800000/spba-bus@30800000/serial@30860000"; 21 }; 22 23 memory { 24 device_type = "memory"; 25 }; 26 27 aliases { 28 gpio0 = "/soc/aips-bus@30000000/gpio@30200000"; 29 gpio1 = "/soc/aips-bus@30000000/gpio@30210000"; 30 gpio2 = "/soc/aips-bus@30000000/gpio@30220000"; 31 gpio3 = "/soc/aips-bus@30000000/gpio@30230000"; 32 gpio4 = "/soc/aips-bus@30000000/gpio@30240000"; 33 gpio5 = "/soc/aips-bus@30000000/gpio@30250000"; 34 gpio6 = "/soc/aips-bus@30000000/gpio@30260000"; 35 i2c0 = "/soc/aips-bus@30800000/i2c@30a20000"; 36 i2c1 = "/soc/aips-bus@30800000/i2c@30a30000"; 37 i2c2 = "/soc/aips-bus@30800000/i2c@30a40000"; 38 i2c3 = "/soc/aips-bus@30800000/i2c@30a50000"; 39 mmc0 = "/soc/aips-bus@30800000/usdhc@30b40000"; 40 mmc1 = "/soc/aips-bus@30800000/usdhc@30b50000"; 41 mmc2 = "/soc/aips-bus@30800000/usdhc@30b60000"; 42 serial0 = "/soc/aips-bus@30800000/spba-bus@30800000/serial@30860000"; 43 serial1 = "/soc/aips-bus@30800000/spba-bus@30800000/serial@30890000"; 44 serial2 = "/soc/aips-bus@30800000/spba-bus@30800000/serial@30880000"; 45 serial3 = "/soc/aips-bus@30800000/serial@30a60000"; 46 serial4 = "/soc/aips-bus@30800000/serial@30a70000"; 47 serial5 = "/soc/aips-bus@30800000/serial@30a80000"; 48 serial6 = "/soc/aips-bus@30800000/serial@30a90000"; 49 spi0 = "/soc/aips-bus@30800000/spba-bus@30800000/spi@30820000"; 50 spi1 = "/soc/aips-bus@30800000/spba-bus@30800000/spi@30830000"; 51 spi2 = "/soc/aips-bus@30800000/spba-bus@30800000/spi@30840000"; 52 spi3 = "/soc/aips-bus@30400000/spi@30630000"; 53 }; 54 55 cpus { 56 #address-cells = < 0x01 >; 57 #size-cells = < 0x00 >; 58 59 idle-states { 60 entry-method = "psci"; 61 62 cpu-sleep-wait { 63 compatible = "arm,idle-state"; 64 arm,psci-suspend-param = < 0x10000 >; 65 local-timer-stop; 66 entry-latency-us = < 0x64 >; 67 exit-latency-us = < 0x32 >; 68 min-residency-us = < 0x3e8 >; 69 phandle = < 0x02 >; 70 }; 71 }; 72 73 cpu@0 { 74 compatible = "arm,cortex-a7"; 75 device_type = "cpu"; 76 reg = < 0x00 >; 77 clock-frequency = < 0x3b5dc100 >; 78 clock-latency = < 0xee6c >; 79 clocks = < 0x01 0x1b5 >; 80 cpu-idle-states = < 0x02 >; 81 operating-points-v2 = < 0x03 >; 82 #cooling-cells = < 0x02 >; 83 cpu-supply = < 0x04 >; 84 phandle = < 0x06 >; 85 }; 86 87 cpu@1 { 88 compatible = "arm,cortex-a7"; 89 device_type = "cpu"; 90 reg = < 0x01 >; 91 clock-frequency = < 0x3b5dc100 >; 92 operating-points-v2 = < 0x03 >; 93 cpu-idle-states = < 0x02 >; 94 phandle = < 0x49 >; 95 }; 96 }; 97 98 clock-cki { 99 compatible = "fixed-clock"; 100 #clock-cells = < 0x00 >; 101 clock-frequency = < 0x8000 >; 102 clock-output-names = "ckil"; 103 phandle = < 0x1d >; 104 }; 105 106 clock-osc { 107 compatible = "fixed-clock"; 108 #clock-cells = < 0x00 >; 109 clock-frequency = < 0x16e3600 >; 110 clock-output-names = "osc"; 111 phandle = < 0x1e >; 112 }; 113 114 usbphynop1 { 115 compatible = "usb-nop-xceiv"; 116 clocks = < 0x01 0x1a7 >; 117 clock-names = "main_clk"; 118 #phy-cells = < 0x00 >; 119 phandle = < 0x31 >; 120 }; 121 122 usbphynop3 { 123 compatible = "usb-nop-xceiv"; 124 clocks = < 0x01 0x6e >; 125 clock-names = "main_clk"; 126 #phy-cells = < 0x00 >; 127 phandle = < 0x34 >; 128 }; 129 130 pmu { 131 compatible = "arm,cortex-a7-pmu"; 132 interrupt-parent = < 0x05 >; 133 interrupts = < 0x00 0x5c 0x04 >; 134 interrupt-affinity = < 0x06 >; 135 }; 136 137 replicator { 138 compatible = "arm,coresight-replicator"; 139 140 out-ports { 141 #address-cells = < 0x01 >; 142 #size-cells = < 0x00 >; 143 144 port@0 { 145 reg = < 0x00 >; 146 147 endpoint { 148 remote-endpoint = < 0x07 >; 149 phandle = < 0x17 >; 150 }; 151 }; 152 153 port@1 { 154 reg = < 0x01 >; 155 156 endpoint { 157 remote-endpoint = < 0x08 >; 158 phandle = < 0x16 >; 159 }; 160 }; 161 }; 162 163 in-ports { 164 165 port { 166 167 endpoint { 168 remote-endpoint = < 0x09 >; 169 phandle = < 0x15 >; 170 }; 171 }; 172 }; 173 }; 174 175 tempmon { 176 compatible = "fsl,imx7d-tempmon"; 177 interrupt-parent = < 0x05 >; 178 interrupts = < 0x00 0x31 0x04 >; 179 fsl,tempmon = < 0x0a >; 180 nvmem-cells = < 0x0b 0x0c >; 181 nvmem-cell-names = "calib\0temp_grade"; 182 clocks = < 0x01 0x06 >; 183 }; 184 185 timer { 186 compatible = "arm,armv7-timer"; 187 interrupt-parent = < 0x0d >; 188 interrupts = < 0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08 0x01 0x0a 0xf08 >; 189 }; 190 191 soc { 192 #address-cells = < 0x01 >; 193 #size-cells = < 0x01 >; 194 compatible = "simple-bus"; 195 interrupt-parent = < 0x05 >; 196 ranges; 197 198 funnel@30041000 { 199 compatible = "arm,coresight-funnel\0arm,primecell"; 200 reg = < 0x30041000 0x1000 >; 201 clocks = < 0x01 0x4a >; 202 clock-names = "apb_pclk"; 203 204 in-ports { 205 #address-cells = < 0x01 >; 206 #size-cells = < 0x00 >; 207 208 port { 209 210 endpoint { 211 remote-endpoint = < 0x0e >; 212 phandle = < 0x11 >; 213 }; 214 }; 215 216 port@1 { 217 reg = < 0x01 >; 218 219 endpoint { 220 remote-endpoint = < 0x0f >; 221 phandle = < 0x4a >; 222 }; 223 }; 224 }; 225 226 out-ports { 227 228 port { 229 230 endpoint { 231 remote-endpoint = < 0x10 >; 232 phandle = < 0x12 >; 233 }; 234 }; 235 }; 236 }; 237 238 etm@3007c000 { 239 compatible = "arm,coresight-etm3x\0arm,primecell"; 240 reg = < 0x3007c000 0x1000 >; 241 cpu = < 0x06 >; 242 clocks = < 0x01 0x4a >; 243 clock-names = "apb_pclk"; 244 245 out-ports { 246 247 port { 248 249 endpoint { 250 remote-endpoint = < 0x11 >; 251 phandle = < 0x0e >; 252 }; 253 }; 254 }; 255 }; 256 257 funnel@30083000 { 258 compatible = "arm,coresight-funnel\0arm,primecell"; 259 reg = < 0x30083000 0x1000 >; 260 clocks = < 0x01 0x4a >; 261 clock-names = "apb_pclk"; 262 263 in-ports { 264 #address-cells = < 0x01 >; 265 #size-cells = < 0x00 >; 266 267 port@0 { 268 reg = < 0x00 >; 269 270 endpoint { 271 remote-endpoint = < 0x12 >; 272 phandle = < 0x10 >; 273 }; 274 }; 275 276 port@1 { 277 reg = < 0x01 >; 278 279 endpoint { 280 }; 281 }; 282 }; 283 284 out-ports { 285 286 port { 287 288 endpoint { 289 remote-endpoint = < 0x13 >; 290 phandle = < 0x14 >; 291 }; 292 }; 293 }; 294 }; 295 296 etf@30084000 { 297 compatible = "arm,coresight-tmc\0arm,primecell"; 298 reg = < 0x30084000 0x1000 >; 299 clocks = < 0x01 0x4a >; 300 clock-names = "apb_pclk"; 301 302 in-ports { 303 304 port { 305 306 endpoint { 307 remote-endpoint = < 0x14 >; 308 phandle = < 0x13 >; 309 }; 310 }; 311 }; 312 313 out-ports { 314 315 port { 316 317 endpoint { 318 remote-endpoint = < 0x15 >; 319 phandle = < 0x09 >; 320 }; 321 }; 322 }; 323 }; 324 325 etr@30086000 { 326 compatible = "arm,coresight-tmc\0arm,primecell"; 327 reg = < 0x30086000 0x1000 >; 328 clocks = < 0x01 0x4a >; 329 clock-names = "apb_pclk"; 330 331 in-ports { 332 333 port { 334 335 endpoint { 336 remote-endpoint = < 0x16 >; 337 phandle = < 0x08 >; 338 }; 339 }; 340 }; 341 }; 342 343 tpiu@30087000 { 344 compatible = "arm,coresight-tpiu\0arm,primecell"; 345 reg = < 0x30087000 0x1000 >; 346 clocks = < 0x01 0x4a >; 347 clock-names = "apb_pclk"; 348 349 in-ports { 350 351 port { 352 353 endpoint { 354 remote-endpoint = < 0x17 >; 355 phandle = < 0x07 >; 356 }; 357 }; 358 }; 359 }; 360 361 interrupt-controller@31001000 { 362 compatible = "arm,cortex-a7-gic"; 363 interrupts = < 0x01 0x09 0xf04 >; 364 #interrupt-cells = < 0x03 >; 365 interrupt-controller; 366 interrupt-parent = < 0x0d >; 367 reg = < 0x31001000 0x1000 0x31002000 0x2000 0x31004000 0x2000 0x31006000 0x2000 >; 368 phandle = < 0x0d >; 369 }; 370 371 aips-bus@30000000 { 372 compatible = "fsl,aips-bus\0simple-bus"; 373 #address-cells = < 0x01 >; 374 #size-cells = < 0x01 >; 375 reg = < 0x30000000 0x400000 >; 376 ranges; 377 378 gpio@30200000 { 379 compatible = "fsl,imx7d-gpio\0fsl,imx35-gpio"; 380 reg = < 0x30200000 0x10000 >; 381 interrupts = < 0x00 0x40 0x04 0x00 0x41 0x04 >; 382 gpio-controller; 383 #gpio-cells = < 0x02 >; 384 interrupt-controller; 385 #interrupt-cells = < 0x02 >; 386 gpio-ranges = < 0x18 0x00 0x00 0x08 0x19 0x08 0x05 0x08 >; 387 phandle = < 0x4d >; 388 }; 389 390 gpio@30210000 { 391 compatible = "fsl,imx7d-gpio\0fsl,imx35-gpio"; 392 reg = < 0x30210000 0x10000 >; 393 interrupts = < 0x00 0x42 0x04 0x00 0x43 0x04 >; 394 gpio-controller; 395 #gpio-cells = < 0x02 >; 396 interrupt-controller; 397 #interrupt-cells = < 0x02 >; 398 gpio-ranges = < 0x19 0x00 0x0d 0x20 >; 399 phandle = < 0x27 >; 400 }; 401 402 gpio@30220000 { 403 compatible = "fsl,imx7d-gpio\0fsl,imx35-gpio"; 404 reg = < 0x30220000 0x10000 >; 405 interrupts = < 0x00 0x44 0x04 0x00 0x45 0x04 >; 406 gpio-controller; 407 #gpio-cells = < 0x02 >; 408 interrupt-controller; 409 #interrupt-cells = < 0x02 >; 410 gpio-ranges = < 0x19 0x00 0x2d 0x1d >; 411 }; 412 413 gpio@30230000 { 414 compatible = "fsl,imx7d-gpio\0fsl,imx35-gpio"; 415 reg = < 0x30230000 0x10000 >; 416 interrupts = < 0x00 0x46 0x04 0x00 0x47 0x04 >; 417 gpio-controller; 418 #gpio-cells = < 0x02 >; 419 interrupt-controller; 420 #interrupt-cells = < 0x02 >; 421 gpio-ranges = < 0x19 0x00 0x4a 0x18 >; 422 phandle = < 0x4e >; 423 }; 424 425 gpio@30240000 { 426 compatible = "fsl,imx7d-gpio\0fsl,imx35-gpio"; 427 reg = < 0x30240000 0x10000 >; 428 interrupts = < 0x00 0x48 0x04 0x00 0x49 0x04 >; 429 gpio-controller; 430 #gpio-cells = < 0x02 >; 431 interrupt-controller; 432 #interrupt-cells = < 0x02 >; 433 gpio-ranges = < 0x19 0x00 0x62 0x12 >; 434 phandle = < 0x25 >; 435 }; 436 437 gpio@30250000 { 438 compatible = "fsl,imx7d-gpio\0fsl,imx35-gpio"; 439 reg = < 0x30250000 0x10000 >; 440 interrupts = < 0x00 0x4a 0x04 0x00 0x4b 0x04 >; 441 gpio-controller; 442 #gpio-cells = < 0x02 >; 443 interrupt-controller; 444 #interrupt-cells = < 0x02 >; 445 gpio-ranges = < 0x19 0x00 0x74 0x17 >; 446 }; 447 448 gpio@30260000 { 449 compatible = "fsl,imx7d-gpio\0fsl,imx35-gpio"; 450 reg = < 0x30260000 0x10000 >; 451 interrupts = < 0x00 0x4c 0x04 0x00 0x4d 0x04 >; 452 gpio-controller; 453 #gpio-cells = < 0x02 >; 454 interrupt-controller; 455 #interrupt-cells = < 0x02 >; 456 gpio-ranges = < 0x19 0x00 0x8b 0x10 >; 457 }; 458 459 wdog@30280000 { 460 compatible = "fsl,imx7d-wdt\0fsl,imx21-wdt"; 461 reg = < 0x30280000 0x10000 >; 462 interrupts = < 0x00 0x4e 0x04 >; 463 clocks = < 0x01 0x142 >; 464 pinctrl-names = "default"; 465 pinctrl-0 = < 0x1a >; 466 fsl,ext-reset-output; 467 }; 468 469 wdog@30290000 { 470 compatible = "fsl,imx7d-wdt\0fsl,imx21-wdt"; 471 reg = < 0x30290000 0x10000 >; 472 interrupts = < 0x00 0x4f 0x04 >; 473 clocks = < 0x01 0x1a1 >; 474 status = "disabled"; 475 }; 476 477 wdog@302a0000 { 478 compatible = "fsl,imx7d-wdt\0fsl,imx21-wdt"; 479 reg = < 0x302a0000 0x10000 >; 480 interrupts = < 0x00 0x0a 0x04 >; 481 clocks = < 0x01 0x1a2 >; 482 status = "disabled"; 483 }; 484 485 wdog@302b0000 { 486 compatible = "fsl,imx7d-wdt\0fsl,imx21-wdt"; 487 reg = < 0x302b0000 0x10000 >; 488 interrupts = < 0x00 0x6d 0x04 >; 489 clocks = < 0x01 0x1a3 >; 490 status = "disabled"; 491 }; 492 493 iomuxc-lpsr@302c0000 { 494 compatible = "fsl,imx7d-iomuxc-lpsr"; 495 reg = < 0x302c0000 0x10000 >; 496 fsl,input-sel = < 0x19 >; 497 phandle = < 0x18 >; 498 499 wdoggrp { 500 fsl,pins = < 0x00 0x30 0x00 0x03 0x00 0x74 >; 501 phandle = < 0x1a >; 502 }; 503 504 pwm1grp { 505 fsl,pins = < 0x04 0x34 0x00 0x01 0x00 0x30 >; 506 phandle = < 0x21 >; 507 }; 508 }; 509 510 gpt@302d0000 { 511 compatible = "fsl,imx7d-gpt\0fsl,imx6sx-gpt"; 512 reg = < 0x302d0000 0x10000 >; 513 interrupts = < 0x00 0x37 0x04 >; 514 clocks = < 0x01 0x19d 0x01 0x12e >; 515 clock-names = "ipg\0per"; 516 }; 517 518 gpt@302e0000 { 519 compatible = "fsl,imx7d-gpt\0fsl,imx6sx-gpt"; 520 reg = < 0x302e0000 0x10000 >; 521 interrupts = < 0x00 0x36 0x04 >; 522 clocks = < 0x01 0x19d 0x01 0x132 >; 523 clock-names = "ipg\0per"; 524 status = "disabled"; 525 }; 526 527 gpt@302f0000 { 528 compatible = "fsl,imx7d-gpt\0fsl,imx6sx-gpt"; 529 reg = < 0x302f0000 0x10000 >; 530 interrupts = < 0x00 0x35 0x04 >; 531 clocks = < 0x01 0x19d 0x01 0x136 >; 532 clock-names = "ipg\0per"; 533 status = "disabled"; 534 }; 535 536 gpt@30300000 { 537 compatible = "fsl,imx7d-gpt\0fsl,imx6sx-gpt"; 538 reg = < 0x30300000 0x10000 >; 539 interrupts = < 0x00 0x34 0x04 >; 540 clocks = < 0x01 0x19d 0x01 0x13a >; 541 clock-names = "ipg\0per"; 542 status = "disabled"; 543 }; 544 545 kpp@30320000 { 546 compatible = "fsl,imx7d-kpp\0fsl,imx21-kpp"; 547 reg = < 0x30320000 0x10000 >; 548 interrupts = < 0x00 0x50 0x04 >; 549 clocks = < 0x01 0x1bc >; 550 status = "disabled"; 551 }; 552 553 iomuxc@30330000 { 554 compatible = "fsl,imx7d-iomuxc"; 555 reg = < 0x30330000 0x10000 >; 556 pinctrl-names = "default"; 557 pinctrl-0 = < 0x1b >; 558 phandle = < 0x19 >; 559 560 imx7d-sdb { 561 562 brcmreggrp { 563 fsl,pins = < 0x17c 0x3ec 0x00 0x05 0x00 0x14 >; 564 phandle = < 0x4f >; 565 }; 566 567 ecspi3grp { 568 fsl,pins = < 0x21c 0x48c 0x548 0x01 0x01 0x02 0x220 0x490 0x54c 0x01 0x01 0x02 0x224 0x494 0x544 0x01 0x01 0x02 0x1ac 0x41c 0x00 0x05 0x00 0x59 >; 569 phandle = < 0x24 >; 570 }; 571 572 enet1grp { 573 fsl,pins = < 0x1c 0x274 0x568 0x02 0x00 0x03 0x20 0x278 0x00 0x02 0x00 0x03 0x258 0x4c8 0x00 0x00 0x00 0x01 0x244 0x4b4 0x00 0x00 0x00 0x01 0x248 0x4b8 0x00 0x00 0x00 0x01 0x24c 0x4bc 0x00 0x00 0x00 0x01 0x250 0x4c0 0x00 0x00 0x00 0x01 0x254 0x4c4 0x00 0x00 0x00 0x01 0x240 0x4b0 0x00 0x00 0x00 0x01 0x22c 0x49c 0x00 0x00 0x00 0x01 0x230 0x4a0 0x00 0x00 0x00 0x01 0x234 0x4a4 0x00 0x00 0x00 0x01 0x238 0x4a8 0x00 0x00 0x00 0x01 0x23c 0x4ac 0x00 0x00 0x00 0x01 >; 574 phandle = < 0x3e >; 575 }; 576 577 enet2grp { 578 fsl,pins = < 0xa0 0x310 0x00 0x02 0x00 0x01 0x8c 0x2fc 0x00 0x02 0x00 0x01 0x90 0x300 0x00 0x02 0x00 0x01 0x94 0x304 0x00 0x02 0x00 0x01 0x98 0x308 0x00 0x02 0x00 0x01 0x9c 0x30c 0x00 0x02 0x00 0x01 0x88 0x2f8 0x578 0x02 0x00 0x01 0x74 0x2e4 0x00 0x02 0x00 0x01 0x78 0x2e8 0x00 0x02 0x00 0x01 0x7c 0x2ec 0x00 0x02 0x00 0x01 0x80 0x2f0 0x00 0x02 0x00 0x01 0x84 0x2f4 0x00 0x02 0x00 0x01 >; 579 phandle = < 0x44 >; 580 }; 581 582 flexcan2grp { 583 fsl,pins = < 0x2c 0x284 0x4e0 0x03 0x00 0x59 0x30 0x288 0x00 0x03 0x00 0x59 >; 584 phandle = < 0x2a >; 585 }; 586 587 flexcan2reggrp { 588 fsl,pins = < 0x6c 0x2dc 0x00 0x05 0x00 0x59 >; 589 phandle = < 0x50 >; 590 }; 591 592 gpio_keysgrp { 593 fsl,pins = < 0x1b4 0x424 0x00 0x05 0x00 0x59 0x1b0 0x420 0x00 0x05 0x00 0x59 >; 594 phandle = < 0x4b >; 595 }; 596 597 hoggrp { 598 fsl,pins = < 0x144 0x3b4 0x00 0x05 0x00 0x14 0x184 0x3f4 0x00 0x05 0x00 0x34 >; 599 phandle = < 0x1b >; 600 }; 601 602 i2c1grp { 603 fsl,pins = < 0x14c 0x3bc 0x5d8 0x00 0x01 0x4000007f 0x148 0x3b8 0x5d4 0x00 0x01 0x4000007f >; 604 phandle = < 0x2c >; 605 }; 606 607 i2c2grp { 608 fsl,pins = < 0x154 0x3c4 0x5e0 0x00 0x01 0x4000007f 0x150 0x3c0 0x5dc 0x00 0x01 0x4000007f >; 609 phandle = < 0x2d >; 610 }; 611 612 i2c3grp { 613 fsl,pins = < 0x15c 0x3cc 0x5e8 0x00 0x02 0x4000007f 0x158 0x3c8 0x5e4 0x00 0x02 0x4000007f >; 614 phandle = < 0x2e >; 615 }; 616 617 i2c4grp { 618 fsl,pins = < 0x214 0x484 0x5f0 0x03 0x03 0x4000007f 0x210 0x480 0x5ec 0x03 0x03 0x4000007f >; 619 phandle = < 0x2f >; 620 }; 621 622 lcdifgrp { 623 fsl,pins = < 0xc8 0x338 0x638 0x00 0x02 0x79 0xcc 0x33c 0x63c 0x00 0x02 0x79 0xd0 0x340 0x640 0x00 0x02 0x79 0xd4 0x344 0x644 0x00 0x02 0x79 0xd8 0x348 0x648 0x00 0x02 0x79 0xdc 0x34c 0x64c 0x00 0x02 0x79 0xe0 0x350 0x650 0x00 0x02 0x79 0xe4 0x354 0x654 0x00 0x02 0x79 0xe8 0x358 0x658 0x00 0x02 0x79 0xec 0x35c 0x65c 0x00 0x02 0x79 0xf0 0x360 0x660 0x00 0x02 0x79 0xf4 0x364 0x664 0x00 0x02 0x79 0xf8 0x368 0x668 0x00 0x02 0x79 0xfc 0x36c 0x66c 0x00 0x01 0x79 0x100 0x370 0x670 0x00 0x01 0x79 0x104 0x374 0x674 0x00 0x01 0x79 0x108 0x378 0x678 0x00 0x02 0x79 0x10c 0x37c 0x67c 0x00 0x02 0x79 0x110 0x380 0x680 0x00 0x02 0x79 0x114 0x384 0x684 0x00 0x02 0x79 0x118 0x388 0x688 0x00 0x02 0x79 0x11c 0x38c 0x68c 0x00 0x02 0x79 0x120 0x390 0x690 0x00 0x02 0x79 0x124 0x394 0x694 0x00 0x02 0x79 0xb4 0x324 0x00 0x00 0x00 0x79 0xb8 0x328 0x00 0x00 0x00 0x79 0xc0 0x330 0x698 0x00 0x02 0x79 0xbc 0x32c 0x00 0x00 0x00 0x79 0xc4 0x334 0x00 0x00 0x00 0x79 >; 624 phandle = < 0x22 >; 625 }; 626 627 spi4grp { 628 fsl,pins = < 0x18 0x270 0x00 0x00 0x00 0x59 0x24 0x27c 0x00 0x00 0x00 0x59 0x28 0x280 0x00 0x00 0x00 0x59 >; 629 phandle = < 0x4c >; 630 }; 631 632 tsc2046_pendown { 633 fsl,pins = < 0xa8 0x318 0x00 0x05 0x00 0x59 >; 634 phandle = < 0x26 >; 635 }; 636 637 uart1grp { 638 fsl,pins = < 0x12c 0x39c 0x00 0x00 0x00 0x79 0x128 0x398 0x6f4 0x00 0x00 0x79 >; 639 phandle = < 0x28 >; 640 }; 641 642 uart5grp { 643 fsl,pins = < 0x204 0x474 0x00 0x02 0x00 0x79 0x200 0x470 0x714 0x02 0x02 0x79 0x208 0x478 0x00 0x02 0x00 0x79 0x20c 0x47c 0x710 0x02 0x03 0x79 >; 644 }; 645 646 uart6grp { 647 fsl,pins = < 0x16c 0x3dc 0x00 0x01 0x00 0x79 0x168 0x3d8 0x71c 0x01 0x02 0x79 0x174 0x3e4 0x00 0x01 0x00 0x79 0x170 0x3e0 0x718 0x01 0x02 0x79 >; 648 phandle = < 0x30 >; 649 }; 650 651 usdhc1grp { 652 fsl,pins = < 0x198 0x408 0x00 0x00 0x00 0x59 0x194 0x404 0x00 0x00 0x00 0x19 0x19c 0x40c 0x00 0x00 0x00 0x59 0x1a0 0x410 0x00 0x00 0x00 0x59 0x1a4 0x414 0x00 0x00 0x00 0x59 0x1a8 0x418 0x00 0x00 0x00 0x59 0x188 0x3f8 0x00 0x05 0x00 0x59 0x18c 0x3fc 0x00 0x05 0x00 0x59 0x190 0x400 0x00 0x05 0x00 0x59 >; 653 phandle = < 0x36 >; 654 }; 655 656 usdhc2grp { 657 fsl,pins = < 0x1bc 0x42c 0x00 0x00 0x00 0x59 0x1b8 0x428 0x00 0x00 0x00 0x19 0x1c0 0x430 0x00 0x00 0x00 0x59 0x1c4 0x434 0x00 0x00 0x00 0x59 0x1c8 0x438 0x00 0x00 0x00 0x59 0x1cc 0x43c 0x00 0x00 0x00 0x59 >; 658 phandle = < 0x37 >; 659 }; 660 661 usdhc2grp_100mhz { 662 fsl,pins = < 0x1bc 0x42c 0x00 0x00 0x00 0x5a 0x1b8 0x428 0x00 0x00 0x00 0x1a 0x1c0 0x430 0x00 0x00 0x00 0x5a 0x1c4 0x434 0x00 0x00 0x00 0x5a 0x1c8 0x438 0x00 0x00 0x00 0x5a 0x1cc 0x43c 0x00 0x00 0x00 0x5a >; 663 phandle = < 0x38 >; 664 }; 665 666 usdhc2grp_200mhz { 667 fsl,pins = < 0x1bc 0x42c 0x00 0x00 0x00 0x5b 0x1b8 0x428 0x00 0x00 0x00 0x1b 0x1c0 0x430 0x00 0x00 0x00 0x5b 0x1c4 0x434 0x00 0x00 0x00 0x5b 0x1c8 0x438 0x00 0x00 0x00 0x5b 0x1cc 0x43c 0x00 0x00 0x00 0x5b >; 668 phandle = < 0x39 >; 669 }; 670 671 usdhc3grp { 672 fsl,pins = < 0x1d4 0x444 0x00 0x00 0x00 0x59 0x1d0 0x440 0x00 0x00 0x00 0x19 0x1d8 0x448 0x00 0x00 0x00 0x59 0x1dc 0x44c 0x00 0x00 0x00 0x59 0x1e0 0x450 0x00 0x00 0x00 0x59 0x1e4 0x454 0x00 0x00 0x00 0x59 0x1e8 0x458 0x00 0x00 0x00 0x59 0x1ec 0x45c 0x00 0x00 0x00 0x59 0x1f0 0x460 0x00 0x00 0x00 0x59 0x1f4 0x464 0x00 0x00 0x00 0x59 0x1f8 0x468 0x00 0x00 0x00 0x19 >; 673 phandle = < 0x3b >; 674 }; 675 676 usdhc3grp_100mhz { 677 fsl,pins = < 0x1d4 0x444 0x00 0x00 0x00 0x5a 0x1d0 0x440 0x00 0x00 0x00 0x1a 0x1d8 0x448 0x00 0x00 0x00 0x5a 0x1dc 0x44c 0x00 0x00 0x00 0x5a 0x1e0 0x450 0x00 0x00 0x00 0x5a 0x1e4 0x454 0x00 0x00 0x00 0x5a 0x1e8 0x458 0x00 0x00 0x00 0x5a 0x1ec 0x45c 0x00 0x00 0x00 0x5a 0x1f0 0x460 0x00 0x00 0x00 0x5a 0x1f4 0x464 0x00 0x00 0x00 0x5a 0x1f8 0x468 0x00 0x00 0x00 0x1a >; 678 phandle = < 0x3c >; 679 }; 680 681 usdhc3grp_200mhz { 682 fsl,pins = < 0x1d4 0x444 0x00 0x00 0x00 0x5b 0x1d0 0x440 0x00 0x00 0x00 0x1b 0x1d8 0x448 0x00 0x00 0x00 0x5b 0x1dc 0x44c 0x00 0x00 0x00 0x5b 0x1e0 0x450 0x00 0x00 0x00 0x5b 0x1e4 0x454 0x00 0x00 0x00 0x5b 0x1e8 0x458 0x00 0x00 0x00 0x5b 0x1ec 0x45c 0x00 0x00 0x00 0x5b 0x1f0 0x460 0x00 0x00 0x00 0x5b 0x1f4 0x464 0x00 0x00 0x00 0x5b 0x1f8 0x468 0x00 0x00 0x00 0x1b >; 683 phandle = < 0x3d >; 684 }; 685 }; 686 }; 687 688 iomuxc-gpr@30340000 { 689 compatible = "fsl,imx7d-iomuxc-gpr\0fsl,imx6q-iomuxc-gpr\0syscon"; 690 reg = < 0x30340000 0x10000 >; 691 }; 692 693 ocotp-ctrl@30350000 { 694 #address-cells = < 0x01 >; 695 #size-cells = < 0x01 >; 696 compatible = "fsl,imx7d-ocotp\0syscon"; 697 reg = < 0x30350000 0x10000 >; 698 clocks = < 0x01 0x1b7 >; 699 700 calib@3c { 701 reg = < 0x3c 0x04 >; 702 phandle = < 0x0b >; 703 }; 704 705 temp-grade@10 { 706 reg = < 0x10 0x04 >; 707 phandle = < 0x0c >; 708 }; 709 }; 710 711 anatop@30360000 { 712 compatible = "fsl,imx7d-anatop\0fsl,imx6q-anatop\0syscon\0simple-bus"; 713 reg = < 0x30360000 0x10000 >; 714 interrupts = < 0x00 0x31 0x04 0x00 0x33 0x04 >; 715 phandle = < 0x0a >; 716 717 regulator-vdd1p0d { 718 compatible = "fsl,anatop-regulator"; 719 regulator-name = "vdd1p0d"; 720 regulator-min-microvolt = < 0xc3500 >; 721 regulator-max-microvolt = < 0x124f80 >; 722 anatop-reg-offset = < 0x210 >; 723 anatop-vol-bit-shift = < 0x08 >; 724 anatop-vol-bit-width = < 0x05 >; 725 anatop-min-bit-val = < 0x08 >; 726 anatop-min-voltage = < 0xc3500 >; 727 anatop-max-voltage = < 0x124f80 >; 728 anatop-enable-bit = < 0x00 >; 729 phandle = < 0x1f >; 730 }; 731 732 regulator-vdd1p2 { 733 compatible = "fsl,anatop-regulator"; 734 regulator-name = "vdd1p2"; 735 regulator-min-microvolt = < 0x10c8e0 >; 736 regulator-max-microvolt = < 0x13d620 >; 737 anatop-reg-offset = < 0x220 >; 738 anatop-vol-bit-shift = < 0x08 >; 739 anatop-vol-bit-width = < 0x05 >; 740 anatop-min-bit-val = < 0x14 >; 741 anatop-min-voltage = < 0x10c8e0 >; 742 anatop-max-voltage = < 0x13d620 >; 743 anatop-enable-bit = < 0x00 >; 744 }; 745 }; 746 747 snvs@30370000 { 748 compatible = "fsl,sec-v4.0-mon\0syscon\0simple-mfd"; 749 reg = < 0x30370000 0x10000 >; 750 phandle = < 0x1c >; 751 752 snvs-rtc-lp { 753 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 754 regmap = < 0x1c >; 755 offset = < 0x34 >; 756 interrupts = < 0x00 0x13 0x04 0x00 0x14 0x04 >; 757 clocks = < 0x01 0x1ba >; 758 clock-names = "snvs-rtc"; 759 }; 760 761 snvs-powerkey { 762 compatible = "fsl,sec-v4.0-pwrkey"; 763 regmap = < 0x1c >; 764 interrupts = < 0x00 0x04 0x04 >; 765 linux,keycode = < 0x74 >; 766 wakeup-source; 767 }; 768 }; 769 770 ccm@30380000 { 771 compatible = "fsl,imx7d-ccm"; 772 reg = < 0x30380000 0x10000 >; 773 interrupts = < 0x00 0x55 0x04 0x00 0x56 0x04 >; 774 #clock-cells = < 0x01 >; 775 clocks = < 0x1d 0x1e >; 776 clock-names = "ckil\0osc"; 777 phandle = < 0x01 >; 778 }; 779 780 src@30390000 { 781 compatible = "fsl,imx7d-src\0syscon"; 782 reg = < 0x30390000 0x10000 >; 783 interrupts = < 0x00 0x59 0x04 >; 784 #reset-cells = < 0x01 >; 785 phandle = < 0x47 >; 786 }; 787 788 gpc@303a0000 { 789 compatible = "fsl,imx7d-gpc"; 790 reg = < 0x303a0000 0x10000 >; 791 interrupt-controller; 792 interrupts = < 0x00 0x57 0x04 >; 793 #interrupt-cells = < 0x03 >; 794 interrupt-parent = < 0x0d >; 795 #power-domain-cells = < 0x01 >; 796 phandle = < 0x05 >; 797 798 pgc { 799 #address-cells = < 0x01 >; 800 #size-cells = < 0x00 >; 801 802 pgc-power-domain@1 { 803 #power-domain-cells = < 0x00 >; 804 reg = < 0x01 >; 805 power-supply = < 0x1f >; 806 phandle = < 0x46 >; 807 }; 808 }; 809 }; 810 }; 811 812 aips-bus@30400000 { 813 compatible = "fsl,aips-bus\0simple-bus"; 814 #address-cells = < 0x01 >; 815 #size-cells = < 0x01 >; 816 reg = < 0x30400000 0x400000 >; 817 ranges; 818 819 adc@30610000 { 820 compatible = "fsl,imx7d-adc"; 821 reg = < 0x30610000 0x10000 >; 822 interrupts = < 0x00 0x62 0x04 >; 823 clocks = < 0x01 0x1b4 >; 824 clock-names = "adc"; 825 status = "okay"; 826 vref-supply = < 0x20 >; 827 }; 828 829 adc@30620000 { 830 compatible = "fsl,imx7d-adc"; 831 reg = < 0x30620000 0x10000 >; 832 interrupts = < 0x00 0x63 0x04 >; 833 clocks = < 0x01 0x1b4 >; 834 clock-names = "adc"; 835 status = "okay"; 836 vref-supply = < 0x20 >; 837 }; 838 839 spi@30630000 { 840 #address-cells = < 0x01 >; 841 #size-cells = < 0x00 >; 842 compatible = "fsl,imx7d-ecspi\0fsl,imx51-ecspi"; 843 reg = < 0x30630000 0x10000 >; 844 interrupts = < 0x00 0x22 0x04 >; 845 clocks = < 0x01 0x10a 0x01 0x10a >; 846 clock-names = "ipg\0per"; 847 status = "disabled"; 848 }; 849 850 pwm@30660000 { 851 compatible = "fsl,imx7d-pwm\0fsl,imx27-pwm"; 852 reg = < 0x30660000 0x10000 >; 853 interrupts = < 0x00 0x51 0x04 >; 854 clocks = < 0x01 0x10e 0x01 0x10e >; 855 clock-names = "ipg\0per"; 856 #pwm-cells = < 0x03 >; 857 status = "okay"; 858 pinctrl-names = "default"; 859 pinctrl-0 = < 0x21 >; 860 phandle = < 0x51 >; 861 }; 862 863 pwm@30670000 { 864 compatible = "fsl,imx7d-pwm\0fsl,imx27-pwm"; 865 reg = < 0x30670000 0x10000 >; 866 interrupts = < 0x00 0x52 0x04 >; 867 clocks = < 0x01 0x112 0x01 0x112 >; 868 clock-names = "ipg\0per"; 869 #pwm-cells = < 0x03 >; 870 status = "disabled"; 871 }; 872 873 pwm@30680000 { 874 compatible = "fsl,imx7d-pwm\0fsl,imx27-pwm"; 875 reg = < 0x30680000 0x10000 >; 876 interrupts = < 0x00 0x53 0x04 >; 877 clocks = < 0x01 0x116 0x01 0x116 >; 878 clock-names = "ipg\0per"; 879 #pwm-cells = < 0x03 >; 880 status = "disabled"; 881 }; 882 883 pwm@30690000 { 884 compatible = "fsl,imx7d-pwm\0fsl,imx27-pwm"; 885 reg = < 0x30690000 0x10000 >; 886 interrupts = < 0x00 0x54 0x04 >; 887 clocks = < 0x01 0x11a 0x01 0x11a >; 888 clock-names = "ipg\0per"; 889 #pwm-cells = < 0x03 >; 890 status = "disabled"; 891 }; 892 893 lcdif@30730000 { 894 compatible = "fsl,imx7d-lcdif\0fsl,imx28-lcdif"; 895 reg = < 0x30730000 0x10000 >; 896 interrupts = < 0x00 0x05 0x04 >; 897 clocks = < 0x01 0x7e 0x01 0x7e >; 898 clock-names = "pix\0axi"; 899 status = "okay"; 900 pinctrl-names = "default"; 901 pinctrl-0 = < 0x22 >; 902 903 port { 904 905 endpoint { 906 remote-endpoint = < 0x23 >; 907 phandle = < 0x54 >; 908 }; 909 }; 910 }; 911 }; 912 913 aips-bus@30800000 { 914 compatible = "fsl,aips-bus\0simple-bus"; 915 #address-cells = < 0x01 >; 916 #size-cells = < 0x01 >; 917 reg = < 0x30800000 0x400000 >; 918 ranges; 919 920 spba-bus@30800000 { 921 compatible = "fsl,spba-bus\0simple-bus"; 922 #address-cells = < 0x01 >; 923 #size-cells = < 0x01 >; 924 reg = < 0x30800000 0x100000 >; 925 ranges; 926 927 spi@30820000 { 928 #address-cells = < 0x01 >; 929 #size-cells = < 0x00 >; 930 compatible = "fsl,imx7d-ecspi\0fsl,imx51-ecspi"; 931 reg = < 0x30820000 0x10000 >; 932 interrupts = < 0x00 0x1f 0x04 >; 933 clocks = < 0x01 0xfe 0x01 0xfe >; 934 clock-names = "ipg\0per"; 935 status = "disabled"; 936 }; 937 938 spi@30830000 { 939 #address-cells = < 0x01 >; 940 #size-cells = < 0x00 >; 941 compatible = "fsl,imx7d-ecspi\0fsl,imx51-ecspi"; 942 reg = < 0x30830000 0x10000 >; 943 interrupts = < 0x00 0x20 0x04 >; 944 clocks = < 0x01 0x102 0x01 0x102 >; 945 clock-names = "ipg\0per"; 946 status = "disabled"; 947 }; 948 949 spi@30840000 { 950 #address-cells = < 0x01 >; 951 #size-cells = < 0x00 >; 952 compatible = "fsl,imx7d-ecspi\0fsl,imx51-ecspi"; 953 reg = < 0x30840000 0x10000 >; 954 interrupts = < 0x00 0x21 0x04 >; 955 clocks = < 0x01 0x106 0x01 0x106 >; 956 clock-names = "ipg\0per"; 957 status = "okay"; 958 pinctrl-names = "default"; 959 pinctrl-0 = < 0x24 >; 960 cs-gpios = < 0x25 0x09 0x00 >; 961 962 tsc2046@0 { 963 compatible = "ti,tsc2046"; 964 reg = < 0x00 >; 965 spi-max-frequency = < 0xf4240 >; 966 pinctrl-names = "default"; 967 pinctrl-0 = < 0x26 >; 968 interrupt-parent = < 0x27 >; 969 interrupts = < 0x1d 0x00 >; 970 pendown-gpio = < 0x27 0x1d 0x00 >; 971 ti,x-min = [ 00 00 ]; 972 ti,x-max = [ 00 00 ]; 973 ti,y-min = [ 00 00 ]; 974 ti,y-max = [ 00 00 ]; 975 ti,pressure-max = [ 00 00 ]; 976 ti,x-plate-ohms = [ 01 90 ]; 977 wakeup-source; 978 }; 979 }; 980 981 serial@30860000 { 982 compatible = "fsl,imx7d-uart\0fsl,imx6q-uart"; 983 reg = < 0x30860000 0x10000 >; 984 interrupts = < 0x00 0x1a 0x04 >; 985 clocks = < 0x01 0xe2 0x01 0xe2 >; 986 clock-names = "ipg\0per"; 987 status = "okay"; 988 pinctrl-names = "default"; 989 pinctrl-0 = < 0x28 >; 990 assigned-clocks = < 0x01 0xe3 >; 991 assigned-clock-parents = < 0x01 0x0d >; 992 }; 993 994 serial@30890000 { 995 compatible = "fsl,imx7d-uart\0fsl,imx6q-uart"; 996 reg = < 0x30890000 0x10000 >; 997 interrupts = < 0x00 0x1b 0x04 >; 998 clocks = < 0x01 0xe6 0x01 0xe6 >; 999 clock-names = "ipg\0per"; 1000 status = "disabled"; 1001 }; 1002 1003 serial@30880000 { 1004 compatible = "fsl,imx7d-uart\0fsl,imx6q-uart"; 1005 reg = < 0x30880000 0x10000 >; 1006 interrupts = < 0x00 0x1c 0x04 >; 1007 clocks = < 0x01 0xea 0x01 0xea >; 1008 clock-names = "ipg\0per"; 1009 status = "disabled"; 1010 }; 1011 1012 sai@308a0000 { 1013 #sound-dai-cells = < 0x00 >; 1014 compatible = "fsl,imx7d-sai\0fsl,imx6sx-sai"; 1015 reg = < 0x308a0000 0x10000 >; 1016 interrupts = < 0x00 0x5f 0x04 >; 1017 clocks = < 0x01 0x1aa 0x01 0x8e 0x01 0x19d 0x01 0x19d >; 1018 clock-names = "bus\0mclk1\0mclk2\0mclk3"; 1019 dma-names = "rx\0tx"; 1020 dmas = < 0x29 0x08 0x18 0x00 0x29 0x09 0x18 0x00 >; 1021 status = "disabled"; 1022 }; 1023 1024 sai@308b0000 { 1025 #sound-dai-cells = < 0x00 >; 1026 compatible = "fsl,imx7d-sai\0fsl,imx6sx-sai"; 1027 reg = < 0x308b0000 0x10000 >; 1028 interrupts = < 0x00 0x60 0x04 >; 1029 clocks = < 0x01 0x1ab 0x01 0x92 0x01 0x19d 0x01 0x19d >; 1030 clock-names = "bus\0mclk1\0mclk2\0mclk3"; 1031 dma-names = "rx\0tx"; 1032 dmas = < 0x29 0x0a 0x18 0x00 0x29 0x0b 0x18 0x00 >; 1033 status = "disabled"; 1034 }; 1035 1036 sai@308c0000 { 1037 #sound-dai-cells = < 0x00 >; 1038 compatible = "fsl,imx7d-sai\0fsl,imx6sx-sai"; 1039 reg = < 0x308c0000 0x10000 >; 1040 interrupts = < 0x00 0x32 0x04 >; 1041 clocks = < 0x01 0x1ac 0x01 0x96 0x01 0x19d 0x01 0x19d >; 1042 clock-names = "bus\0mclk1\0mclk2\0mclk3"; 1043 dma-names = "rx\0tx"; 1044 dmas = < 0x29 0x0c 0x18 0x00 0x29 0x0d 0x18 0x00 >; 1045 status = "disabled"; 1046 }; 1047 }; 1048 1049 caam@30900000 { 1050 compatible = "fsl,sec-v4.0"; 1051 #address-cells = < 0x01 >; 1052 #size-cells = < 0x01 >; 1053 reg = < 0x30900000 0x40000 >; 1054 ranges = < 0x00 0x30900000 0x40000 >; 1055 interrupts = < 0x00 0x5b 0x04 >; 1056 clocks = < 0x01 0x1bb 0x01 0x5a >; 1057 clock-names = "ipg\0aclk"; 1058 1059 jr0@1000 { 1060 compatible = "fsl,sec-v4.0-job-ring"; 1061 reg = < 0x1000 0x1000 >; 1062 interrupts = < 0x00 0x69 0x04 >; 1063 }; 1064 1065 jr1@2000 { 1066 compatible = "fsl,sec-v4.0-job-ring"; 1067 reg = < 0x2000 0x1000 >; 1068 interrupts = < 0x00 0x6a 0x04 >; 1069 }; 1070 1071 jr1@3000 { 1072 compatible = "fsl,sec-v4.0-job-ring"; 1073 reg = < 0x3000 0x1000 >; 1074 interrupts = < 0x00 0x72 0x04 >; 1075 }; 1076 }; 1077 1078 can@30a00000 { 1079 compatible = "fsl,imx7d-flexcan\0fsl,imx6q-flexcan"; 1080 reg = < 0x30a00000 0x10000 >; 1081 interrupts = < 0x00 0x6e 0x04 >; 1082 clocks = < 0x01 0x19d 0x01 0xca >; 1083 clock-names = "ipg\0per"; 1084 status = "disabled"; 1085 }; 1086 1087 can@30a10000 { 1088 compatible = "fsl,imx7d-flexcan\0fsl,imx6q-flexcan"; 1089 reg = < 0x30a10000 0x10000 >; 1090 interrupts = < 0x00 0x6f 0x04 >; 1091 clocks = < 0x01 0x19d 0x01 0xce >; 1092 clock-names = "ipg\0per"; 1093 status = "okay"; 1094 pinctrl-names = "default"; 1095 pinctrl-0 = < 0x2a >; 1096 xceiver-supply = < 0x2b >; 1097 }; 1098 1099 i2c@30a20000 { 1100 #address-cells = < 0x01 >; 1101 #size-cells = < 0x00 >; 1102 compatible = "fsl,imx7d-i2c\0fsl,imx21-i2c"; 1103 reg = < 0x30a20000 0x10000 >; 1104 interrupts = < 0x00 0x23 0x04 >; 1105 clocks = < 0x01 0xd2 >; 1106 status = "okay"; 1107 pinctrl-names = "default"; 1108 pinctrl-0 = < 0x2c >; 1109 1110 pfuze3000@8 { 1111 compatible = "fsl,pfuze3000"; 1112 reg = < 0x08 >; 1113 1114 regulators { 1115 1116 sw1a { 1117 regulator-min-microvolt = < 0xaae60 >; 1118 regulator-max-microvolt = < 0x1681b8 >; 1119 regulator-boot-on; 1120 regulator-always-on; 1121 regulator-ramp-delay = < 0x186a >; 1122 phandle = < 0x04 >; 1123 }; 1124 1125 sw1b { 1126 regulator-min-microvolt = < 0xaae60 >; 1127 regulator-max-microvolt = < 0x1681b8 >; 1128 regulator-boot-on; 1129 regulator-always-on; 1130 regulator-ramp-delay = < 0x186a >; 1131 }; 1132 1133 sw2 { 1134 regulator-min-microvolt = < 0x16e360 >; 1135 regulator-max-microvolt = < 0x1c3a90 >; 1136 regulator-boot-on; 1137 regulator-always-on; 1138 }; 1139 1140 sw3 { 1141 regulator-min-microvolt = < 0xdbba0 >; 1142 regulator-max-microvolt = < 0x192d50 >; 1143 regulator-boot-on; 1144 regulator-always-on; 1145 }; 1146 1147 swbst { 1148 regulator-min-microvolt = < 0x4c4b40 >; 1149 regulator-max-microvolt = < 0x4e9530 >; 1150 }; 1151 1152 vsnvs { 1153 regulator-min-microvolt = < 0xf4240 >; 1154 regulator-max-microvolt = < 0x2dc6c0 >; 1155 regulator-boot-on; 1156 regulator-always-on; 1157 }; 1158 1159 vrefddr { 1160 regulator-boot-on; 1161 regulator-always-on; 1162 }; 1163 1164 vldo1 { 1165 regulator-min-microvolt = < 0x1b7740 >; 1166 regulator-max-microvolt = < 0x325aa0 >; 1167 regulator-always-on; 1168 }; 1169 1170 vldo2 { 1171 regulator-min-microvolt = < 0xc3500 >; 1172 regulator-max-microvolt = < 0x17a6b0 >; 1173 }; 1174 1175 vccsd { 1176 regulator-min-microvolt = < 0x2b7cd0 >; 1177 regulator-max-microvolt = < 0x325aa0 >; 1178 regulator-always-on; 1179 }; 1180 1181 v33 { 1182 regulator-min-microvolt = < 0x2b7cd0 >; 1183 regulator-max-microvolt = < 0x325aa0 >; 1184 regulator-always-on; 1185 }; 1186 1187 vldo3 { 1188 regulator-min-microvolt = < 0x1b7740 >; 1189 regulator-max-microvolt = < 0x325aa0 >; 1190 regulator-always-on; 1191 }; 1192 1193 vldo4 { 1194 regulator-min-microvolt = < 0x2ab980 >; 1195 regulator-max-microvolt = < 0x2ab980 >; 1196 regulator-always-on; 1197 }; 1198 }; 1199 }; 1200 }; 1201 1202 i2c@30a30000 { 1203 #address-cells = < 0x01 >; 1204 #size-cells = < 0x00 >; 1205 compatible = "fsl,imx7d-i2c\0fsl,imx21-i2c"; 1206 reg = < 0x30a30000 0x10000 >; 1207 interrupts = < 0x00 0x24 0x04 >; 1208 clocks = < 0x01 0xd6 >; 1209 status = "okay"; 1210 pinctrl-names = "default"; 1211 pinctrl-0 = < 0x2d >; 1212 1213 mpl3115@60 { 1214 compatible = "fsl,mpl3115"; 1215 reg = < 0x60 >; 1216 }; 1217 }; 1218 1219 i2c@30a40000 { 1220 #address-cells = < 0x01 >; 1221 #size-cells = < 0x00 >; 1222 compatible = "fsl,imx7d-i2c\0fsl,imx21-i2c"; 1223 reg = < 0x30a40000 0x10000 >; 1224 interrupts = < 0x00 0x25 0x04 >; 1225 clocks = < 0x01 0xda >; 1226 status = "okay"; 1227 pinctrl-names = "default"; 1228 pinctrl-0 = < 0x2e >; 1229 }; 1230 1231 i2c@30a50000 { 1232 #address-cells = < 0x01 >; 1233 #size-cells = < 0x00 >; 1234 compatible = "fsl,imx7d-i2c\0fsl,imx21-i2c"; 1235 reg = < 0x30a50000 0x10000 >; 1236 interrupts = < 0x00 0x26 0x04 >; 1237 clocks = < 0x01 0xde >; 1238 status = "okay"; 1239 pinctrl-names = "default"; 1240 pinctrl-0 = < 0x2f >; 1241 1242 wm8960@1a { 1243 compatible = "wlf,wm8960"; 1244 reg = < 0x1a >; 1245 clocks = < 0x01 0x14a >; 1246 clock-names = "mclk"; 1247 wlf,shared-lrclk; 1248 }; 1249 }; 1250 1251 serial@30a60000 { 1252 compatible = "fsl,imx7d-uart\0fsl,imx6q-uart"; 1253 reg = < 0x30a60000 0x10000 >; 1254 interrupts = < 0x00 0x1d 0x04 >; 1255 clocks = < 0x01 0xee 0x01 0xee >; 1256 clock-names = "ipg\0per"; 1257 status = "disabled"; 1258 }; 1259 1260 serial@30a70000 { 1261 compatible = "fsl,imx7d-uart\0fsl,imx6q-uart"; 1262 reg = < 0x30a70000 0x10000 >; 1263 interrupts = < 0x00 0x1e 0x04 >; 1264 clocks = < 0x01 0xf2 0x01 0xf2 >; 1265 clock-names = "ipg\0per"; 1266 status = "disabled"; 1267 }; 1268 1269 serial@30a80000 { 1270 compatible = "fsl,imx7d-uart\0fsl,imx6q-uart"; 1271 reg = < 0x30a80000 0x10000 >; 1272 interrupts = < 0x00 0x10 0x04 >; 1273 clocks = < 0x01 0xf6 0x01 0xf6 >; 1274 clock-names = "ipg\0per"; 1275 status = "okay"; 1276 pinctrl-names = "default"; 1277 pinctrl-0 = < 0x30 >; 1278 assigned-clocks = < 0x01 0xf7 >; 1279 assigned-clock-parents = < 0x01 0x0d >; 1280 uart-has-rtscts; 1281 }; 1282 1283 serial@30a90000 { 1284 compatible = "fsl,imx7d-uart\0fsl,imx6q-uart"; 1285 reg = < 0x30a90000 0x10000 >; 1286 interrupts = < 0x00 0x7e 0x04 >; 1287 clocks = < 0x01 0xfa 0x01 0xfa >; 1288 clock-names = "ipg\0per"; 1289 status = "disabled"; 1290 }; 1291 1292 mailbox@30aa0000 { 1293 compatible = "fsl,imx7s-mu\0fsl,imx6sx-mu"; 1294 reg = < 0x30aa0000 0x10000 >; 1295 interrupts = < 0x00 0x58 0x04 >; 1296 clocks = < 0x01 0x1b1 >; 1297 #mbox-cells = < 0x02 >; 1298 status = "disabled"; 1299 }; 1300 1301 mailbox@30ab0000 { 1302 compatible = "fsl,imx7s-mu\0fsl,imx6sx-mu"; 1303 reg = < 0x30ab0000 0x10000 >; 1304 interrupts = < 0x00 0x61 0x04 >; 1305 clocks = < 0x01 0x1b1 >; 1306 #mbox-cells = < 0x02 >; 1307 fsl,mu-side-b; 1308 status = "disabled"; 1309 }; 1310 1311 usb@30b10000 { 1312 compatible = "fsl,imx7d-usb\0fsl,imx27-usb"; 1313 reg = < 0x30b10000 0x200 >; 1314 interrupts = < 0x00 0x2b 0x04 >; 1315 clocks = < 0x01 0x1a6 >; 1316 fsl,usbphy = < 0x31 >; 1317 fsl,usbmisc = < 0x32 0x00 >; 1318 phy-clkgate-delay-us = < 0x190 >; 1319 status = "okay"; 1320 vbus-supply = < 0x33 >; 1321 }; 1322 1323 usb@30b30000 { 1324 compatible = "fsl,imx7d-usb\0fsl,imx27-usb"; 1325 reg = < 0x30b30000 0x200 >; 1326 interrupts = < 0x00 0x28 0x04 >; 1327 clocks = < 0x01 0x1a6 >; 1328 fsl,usbphy = < 0x34 >; 1329 fsl,usbmisc = < 0x35 0x00 >; 1330 phy_type = "hsic"; 1331 dr_mode = "host"; 1332 phy-clkgate-delay-us = < 0x190 >; 1333 status = "disabled"; 1334 }; 1335 1336 usbmisc@30b10200 { 1337 #index-cells = < 0x01 >; 1338 compatible = "fsl,imx7d-usbmisc\0fsl,imx6q-usbmisc"; 1339 reg = < 0x30b10200 0x200 >; 1340 phandle = < 0x32 >; 1341 }; 1342 1343 usbmisc@30b30200 { 1344 #index-cells = < 0x01 >; 1345 compatible = "fsl,imx7d-usbmisc\0fsl,imx6q-usbmisc"; 1346 reg = < 0x30b30200 0x200 >; 1347 phandle = < 0x35 >; 1348 }; 1349 1350 usdhc@30b40000 { 1351 compatible = "fsl,imx7d-usdhc\0fsl,imx6sl-usdhc"; 1352 reg = < 0x30b40000 0x10000 >; 1353 interrupts = < 0x00 0x16 0x04 >; 1354 clocks = < 0x01 0x1a9 0x01 0x56 0x01 0xbe >; 1355 clock-names = "ipg\0ahb\0per"; 1356 bus-width = < 0x04 >; 1357 status = "okay"; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = < 0x36 >; 1360 cd-gpios = < 0x25 0x00 0x01 >; 1361 wp-gpios = < 0x25 0x01 0x00 >; 1362 wakeup-source; 1363 keep-power-in-suspend; 1364 }; 1365 1366 usdhc@30b50000 { 1367 compatible = "fsl,imx7d-usdhc\0fsl,imx6sl-usdhc"; 1368 reg = < 0x30b50000 0x10000 >; 1369 interrupts = < 0x00 0x17 0x04 >; 1370 clocks = < 0x01 0x1a9 0x01 0x56 0x01 0xc2 >; 1371 clock-names = "ipg\0ahb\0per"; 1372 bus-width = < 0x04 >; 1373 status = "okay"; 1374 pinctrl-names = "default\0state_100mhz\0state_200mhz"; 1375 pinctrl-0 = < 0x37 >; 1376 pinctrl-1 = < 0x38 >; 1377 pinctrl-2 = < 0x39 >; 1378 wakeup-source; 1379 keep-power-in-suspend; 1380 non-removable; 1381 vmmc-supply = < 0x3a >; 1382 fsl,tuning-step = < 0x02 >; 1383 }; 1384 1385 usdhc@30b60000 { 1386 compatible = "fsl,imx7d-usdhc\0fsl,imx6sl-usdhc"; 1387 reg = < 0x30b60000 0x10000 >; 1388 interrupts = < 0x00 0x18 0x04 >; 1389 clocks = < 0x01 0x1a9 0x01 0x56 0x01 0xc6 >; 1390 clock-names = "ipg\0ahb\0per"; 1391 bus-width = < 0x08 >; 1392 status = "okay"; 1393 pinctrl-names = "default\0state_100mhz\0state_200mhz"; 1394 pinctrl-0 = < 0x3b >; 1395 pinctrl-1 = < 0x3c >; 1396 pinctrl-2 = < 0x3d >; 1397 assigned-clocks = < 0x01 0xc6 >; 1398 assigned-clock-rates = < 0x17d78400 >; 1399 fsl,tuning-step = < 0x02 >; 1400 non-removable; 1401 }; 1402 1403 sdma@30bd0000 { 1404 compatible = "fsl,imx7d-sdma\0fsl,imx35-sdma"; 1405 reg = < 0x30bd0000 0x10000 >; 1406 interrupts = < 0x00 0x02 0x04 >; 1407 clocks = < 0x01 0x1a4 0x01 0x5a >; 1408 clock-names = "ipg\0ahb"; 1409 #dma-cells = < 0x03 >; 1410 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1411 phandle = < 0x29 >; 1412 }; 1413 1414 ethernet@30be0000 { 1415 compatible = "fsl,imx7d-fec\0fsl,imx6sx-fec"; 1416 reg = < 0x30be0000 0x10000 >; 1417 interrupt-names = "int0\0int1\0int2\0pps"; 1418 interrupts = < 0x00 0x78 0x04 0x00 0x76 0x04 0x00 0x77 0x04 0x00 0x79 0x04 >; 1419 clocks = < 0x01 0x9e 0x01 0x52 0x01 0xa2 0x01 0x2a 0x01 0xae >; 1420 clock-names = "ipg\0ahb\0ptp\0enet_clk_ref\0enet_out"; 1421 fsl,num-tx-queues = < 0x03 >; 1422 fsl,num-rx-queues = < 0x03 >; 1423 status = "okay"; 1424 pinctrl-names = "default"; 1425 pinctrl-0 = < 0x3e >; 1426 assigned-clocks = < 0x01 0xa3 0x01 0xa2 >; 1427 assigned-clock-parents = < 0x01 0x2b >; 1428 assigned-clock-rates = < 0x00 0x5f5e100 >; 1429 phy-mode = "rgmii"; 1430 phy-handle = < 0x3f >; 1431 fsl,magic-packet; 1432 phy-reset-gpios = < 0x40 0x05 0x01 >; 1433 1434 mdio { 1435 #address-cells = < 0x01 >; 1436 #size-cells = < 0x00 >; 1437 1438 ethernet-phy@0 { 1439 reg = < 0x00 >; 1440 phandle = < 0x3f >; 1441 }; 1442 1443 ethernet-phy@1 { 1444 reg = < 0x01 >; 1445 phandle = < 0x45 >; 1446 }; 1447 }; 1448 }; 1449 1450 usb@30b20000 { 1451 compatible = "fsl,imx7d-usb\0fsl,imx27-usb"; 1452 reg = < 0x30b20000 0x200 >; 1453 interrupts = < 0x00 0x2a 0x04 >; 1454 clocks = < 0x01 0x1a6 >; 1455 fsl,usbphy = < 0x41 >; 1456 fsl,usbmisc = < 0x42 0x00 >; 1457 phy-clkgate-delay-us = < 0x190 >; 1458 status = "okay"; 1459 vbus-supply = < 0x43 >; 1460 dr_mode = "host"; 1461 }; 1462 1463 usbmisc@30b20200 { 1464 #index-cells = < 0x01 >; 1465 compatible = "fsl,imx7d-usbmisc\0fsl,imx6q-usbmisc"; 1466 reg = < 0x30b20200 0x200 >; 1467 phandle = < 0x42 >; 1468 }; 1469 1470 ethernet@30bf0000 { 1471 compatible = "fsl,imx7d-fec\0fsl,imx6sx-fec"; 1472 reg = < 0x30bf0000 0x10000 >; 1473 interrupt-names = "int0\0int1\0int2\0pps"; 1474 interrupts = < 0x00 0x66 0x04 0x00 0x64 0x04 0x00 0x65 0x04 0x00 0x67 0x04 >; 1475 clocks = < 0x01 0xa6 0x01 0x52 0x01 0xaa 0x01 0x2a 0x01 0xae >; 1476 clock-names = "ipg\0ahb\0ptp\0enet_clk_ref\0enet_out"; 1477 fsl,num-tx-queues = < 0x03 >; 1478 fsl,num-rx-queues = < 0x03 >; 1479 status = "okay"; 1480 pinctrl-names = "default"; 1481 pinctrl-0 = < 0x44 >; 1482 assigned-clocks = < 0x01 0xab 0x01 0xaa >; 1483 assigned-clock-parents = < 0x01 0x2b >; 1484 assigned-clock-rates = < 0x00 0x5f5e100 >; 1485 phy-mode = "rgmii"; 1486 phy-handle = < 0x45 >; 1487 fsl,magic-packet; 1488 }; 1489 1490 pcie@33800000 { 1491 compatible = "fsl,imx7d-pcie\0snps,dw-pcie"; 1492 reg = < 0x33800000 0x4000 0x4ff00000 0x80000 >; 1493 reg-names = "dbi\0config"; 1494 #address-cells = < 0x03 >; 1495 #size-cells = < 0x02 >; 1496 device_type = "pci"; 1497 bus-range = < 0x00 0xff >; 1498 ranges = < 0x81000000 0x00 0x00 0x4ff80000 0x00 0x10000 0x82000000 0x00 0x40000000 0x40000000 0x00 0xff00000 >; 1499 num-lanes = < 0x01 >; 1500 interrupts = < 0x00 0x7a 0x04 >; 1501 interrupt-names = "msi"; 1502 #interrupt-cells = < 0x01 >; 1503 interrupt-map-mask = < 0x00 0x00 0x00 0x07 >; 1504 interrupt-map = < 0x00 0x00 0x00 0x01 0x0d 0x00 0x7d 0x04 0x00 0x00 0x00 0x02 0x0d 0x00 0x7c 0x04 0x00 0x00 0x00 0x03 0x0d 0x00 0x7b 0x04 0x00 0x00 0x00 0x04 0x0d 0x00 0x7a 0x04 >; 1505 clocks = < 0x01 0x72 0x01 0x2b 0x01 0x76 >; 1506 clock-names = "pcie\0pcie_bus\0pcie_phy"; 1507 assigned-clocks = < 0x01 0x73 0x01 0x77 >; 1508 assigned-clock-parents = < 0x01 0x29 0x01 0x2b >; 1509 fsl,max-link-speed = < 0x02 >; 1510 power-domains = < 0x46 >; 1511 resets = < 0x47 0x14 0x47 0x16 0x47 0x19 >; 1512 reset-names = "pciephy\0apps\0turnoff"; 1513 status = "okay"; 1514 reset-gpio = < 0x40 0x01 0x01 >; 1515 }; 1516 }; 1517 1518 dma-apbh@33000000 { 1519 compatible = "fsl,imx7d-dma-apbh\0fsl,imx28-dma-apbh"; 1520 reg = < 0x33000000 0x2000 >; 1521 interrupts = < 0x00 0x0c 0x04 0x00 0x0c 0x04 0x00 0x0c 0x04 0x00 0x0c 0x04 >; 1522 interrupt-names = "gpmi0\0gpmi1\0gpmi2\0gpmi3"; 1523 #dma-cells = < 0x01 >; 1524 dma-channels = < 0x04 >; 1525 clocks = < 0x01 0x1b9 >; 1526 phandle = < 0x48 >; 1527 }; 1528 1529 gpmi-nand@33002000 { 1530 compatible = "fsl,imx7d-gpmi-nand"; 1531 #address-cells = < 0x01 >; 1532 #size-cells = < 0x01 >; 1533 reg = < 0x33002000 0x2000 0x33004000 0x4000 >; 1534 reg-names = "gpmi-nand\0bch"; 1535 interrupts = < 0x00 0x0e 0x04 >; 1536 interrupt-names = "bch"; 1537 clocks = < 0x01 0x1b8 0x01 0x1b9 >; 1538 clock-names = "gpmi_io\0gpmi_bch_apb"; 1539 dmas = < 0x48 0x00 >; 1540 dma-names = "rx-tx"; 1541 status = "disabled"; 1542 assigned-clocks = < 0x01 0xb7 >; 1543 assigned-clock-parents = < 0x01 0x28 >; 1544 }; 1545 1546 etm@3007d000 { 1547 compatible = "arm,coresight-etm3x\0arm,primecell"; 1548 reg = < 0x3007d000 0x1000 >; 1549 arm,primecell-periphid = < 0xbb956 >; 1550 cpu = < 0x49 >; 1551 clocks = < 0x01 0x4a >; 1552 clock-names = "apb_pclk"; 1553 1554 out-ports { 1555 1556 port { 1557 1558 endpoint { 1559 remote-endpoint = < 0x4a >; 1560 phandle = < 0x0f >; 1561 }; 1562 }; 1563 }; 1564 }; 1565 }; 1566 1567 opp-table { 1568 compatible = "operating-points-v2"; 1569 opp-shared; 1570 phandle = < 0x03 >; 1571 1572 opp-792000000 { 1573 opp-hz = < 0x00 0x2f34f600 >; 1574 opp-microvolt = < 0xee098 >; 1575 clock-latency-ns = < 0x249f0 >; 1576 }; 1577 1578 opp-996000000 { 1579 opp-hz = < 0x00 0x3b5dc100 >; 1580 opp-microvolt = < 0x106738 >; 1581 clock-latency-ns = < 0x249f0 >; 1582 opp-suspend; 1583 }; 1584 }; 1585 1586 usbphynop2 { 1587 compatible = "usb-nop-xceiv"; 1588 clocks = < 0x01 0x1a8 >; 1589 clock-names = "main_clk"; 1590 #phy-cells = < 0x00 >; 1591 phandle = < 0x41 >; 1592 }; 1593 1594 memory@80000000 { 1595 reg = < 0x80000000 0x80000000 >; 1596 }; 1597 1598 gpio-keys { 1599 compatible = "gpio-keys"; 1600 pinctrl-names = "default"; 1601 pinctrl-0 = < 0x4b >; 1602 1603 volume-up { 1604 label = "Volume Up"; 1605 gpios = < 0x25 0x0b 0x01 >; 1606 linux,code = < 0x73 >; 1607 wakeup-source; 1608 }; 1609 1610 volume-down { 1611 label = "Volume Down"; 1612 gpios = < 0x25 0x0a 0x01 >; 1613 linux,code = < 0x72 >; 1614 wakeup-source; 1615 }; 1616 }; 1617 1618 spi4 { 1619 compatible = "spi-gpio"; 1620 pinctrl-names = "default"; 1621 pinctrl-0 = < 0x4c >; 1622 gpio-sck = < 0x4d 0x0d 0x00 >; 1623 gpio-mosi = < 0x4d 0x09 0x00 >; 1624 cs-gpios = < 0x4d 0x0c 0x00 >; 1625 num-chipselects = < 0x01 >; 1626 #address-cells = < 0x01 >; 1627 #size-cells = < 0x00 >; 1628 1629 gpio-expander@0 { 1630 compatible = "fairchild,74hc595"; 1631 gpio-controller; 1632 #gpio-cells = < 0x02 >; 1633 reg = < 0x00 >; 1634 registers-number = < 0x01 >; 1635 spi-max-frequency = < 0x186a0 >; 1636 phandle = < 0x40 >; 1637 }; 1638 }; 1639 1640 regulator-usb-otg1-vbus { 1641 compatible = "regulator-fixed"; 1642 regulator-name = "usb_otg1_vbus"; 1643 regulator-min-microvolt = < 0x4c4b40 >; 1644 regulator-max-microvolt = < 0x4c4b40 >; 1645 gpio = < 0x4d 0x05 0x00 >; 1646 enable-active-high; 1647 phandle = < 0x33 >; 1648 }; 1649 1650 regulator-usb-otg2-vbus { 1651 compatible = "regulator-fixed"; 1652 regulator-name = "usb_otg2_vbus"; 1653 regulator-min-microvolt = < 0x4c4b40 >; 1654 regulator-max-microvolt = < 0x4c4b40 >; 1655 gpio = < 0x4e 0x07 0x00 >; 1656 enable-active-high; 1657 phandle = < 0x43 >; 1658 }; 1659 1660 regulator-vref-1v8 { 1661 compatible = "regulator-fixed"; 1662 regulator-name = "vref-1v8"; 1663 regulator-min-microvolt = < 0x1b7740 >; 1664 regulator-max-microvolt = < 0x1b7740 >; 1665 phandle = < 0x20 >; 1666 }; 1667 1668 regulator-brcm { 1669 compatible = "regulator-fixed"; 1670 gpio = < 0x4e 0x15 0x00 >; 1671 enable-active-high; 1672 regulator-name = "brcm_reg"; 1673 pinctrl-names = "default"; 1674 pinctrl-0 = < 0x4f >; 1675 regulator-min-microvolt = < 0x325aa0 >; 1676 regulator-max-microvolt = < 0x325aa0 >; 1677 startup-delay-us = < 0x30d40 >; 1678 phandle = < 0x3a >; 1679 }; 1680 1681 regulator-lcd-3v3 { 1682 compatible = "regulator-fixed"; 1683 regulator-name = "lcd-3v3"; 1684 regulator-min-microvolt = < 0x325aa0 >; 1685 regulator-max-microvolt = < 0x325aa0 >; 1686 gpio = < 0x40 0x07 0x01 >; 1687 phandle = < 0x53 >; 1688 }; 1689 1690 regulator-can2-3v3 { 1691 compatible = "regulator-fixed"; 1692 regulator-name = "can2-3v3"; 1693 pinctrl-names = "default"; 1694 pinctrl-0 = < 0x50 >; 1695 regulator-min-microvolt = < 0x325aa0 >; 1696 regulator-max-microvolt = < 0x325aa0 >; 1697 gpio = < 0x27 0x0e 0x01 >; 1698 phandle = < 0x2b >; 1699 }; 1700 1701 backlight { 1702 compatible = "pwm-backlight"; 1703 pwms = < 0x51 0x00 0x4c4b40 0x00 >; 1704 brightness-levels = < 0x00 0x04 0x08 0x10 0x20 0x40 0x80 0xff >; 1705 default-brightness-level = < 0x06 >; 1706 status = "okay"; 1707 phandle = < 0x52 >; 1708 }; 1709 1710 panel { 1711 compatible = "innolux,at043tn24"; 1712 backlight = < 0x52 >; 1713 power-supply = < 0x53 >; 1714 1715 port { 1716 1717 endpoint { 1718 remote-endpoint = < 0x54 >; 1719 phandle = < 0x23 >; 1720 }; 1721 }; 1722 }; 1723}; 1724