1# 2# Copyright 2020, Data61, CSIRO (ABN 41 687 119 230) 3# 4# SPDX-License-Identifier: GPL-2.0-only 5# 6 7cmake_minimum_required(VERSION 3.7.2) 8 9if(KernelArchARM) 10 set_property(TARGET kernel_config_target APPEND PROPERTY TOPLEVELTYPES pde_C) 11endif() 12 13set(KernelArmPASizeBits40 OFF) 14set(KernelArmPASizeBits44 OFF) 15if(KernelArmCortexA53) 16 set(KernelArmPASizeBits40 ON) 17 math(EXPR KernelPaddrUserTop "(1 << 40) - 1") 18elseif(KernelArmCortexA57) 19 set(KernelArmPASizeBits44 ON) 20 math(EXPR KernelPaddrUserTop "(1 << 44) - 1") 21endif() 22config_set(KernelArmPASizeBits40 ARM_PA_SIZE_BITS_40 "${KernelArmPASizeBits40}") 23config_set(KernelArmPASizeBits44 ARM_PA_SIZE_BITS_44 "${KernelArmPASizeBits44}") 24 25if(KernelSel4ArchAarch32) 26 # 64-bit targets may be building in 32-bit mode, 27 # so make sure maximum paddr is 32-bit. 28 math(EXPR KernelPaddrUserTop "(1 << 32) - 1") 29endif() 30 31include(src/arch/arm/armv/armv6/config.cmake) 32include(src/arch/arm/armv/armv7-a/config.cmake) 33include(src/arch/arm/armv/armv8-a/config.cmake) 34 35config_option( 36 KernelDangerousCodeInjectionOnUndefInstr DANGEROUS_CODE_INJECTION_ON_UNDEF_INSTR 37 "Replaces the undefined instruction handler with a call to a function pointer in r8. \ 38 This is an alternative mechanism to the code injection syscall. On ARMv6 the syscall \ 39 interferes with the caches and branch predictor in such a way that it is unsuitable \ 40 for benchmarking. This option has no effect on non-ARMv6 platforms." 41 DEFAULT OFF 42 DEPENDS "KernelArchArmV6;NOT KernelVerificationBuild" 43) 44 45config_option( 46 KernelDebugDisableL2Cache DEBUG_DISABLE_L2_CACHE 47 "Do not enable the L2 cache on startup for debugging purposes." 48 DEFAULT OFF 49 DEPENDS "KernelArchARM" 50) 51config_option( 52 KernelDebugDisableL1ICache DEBUG_DISABLE_L1_ICACHE 53 "Do not enable the L1 instruction cache on startup for debugging purposes." 54 DEFAULT OFF 55 DEPENDS "KernelArchARM;KernelDebugDisableL2Cache" 56) 57config_option( 58 KernelDebugDisableL1DCache DEBUG_DISABLE_L1_DCACHE 59 "Do not enable the L1 data cache on startup for debugging purposes." 60 DEFAULT OFF 61 DEPENDS "KernelArchARM;KernelDebugDisableL2Cache" 62) 63config_option( 64 KernelDebugDisableBranchPrediction DEBUG_DISABLE_BRANCH_PREDICTION 65 "Do not enable branch prediction (also called program flow control) on startup. \ 66 This makes execution time more deterministic at the expense of dramatically decreasing \ 67 performance. Primary use is for debugging." 68 DEFAULT OFF 69 DEPENDS "KernelArchARM" 70) 71if(KernelSel4ArchArmHyp) 72 set(default_hyp_support ON) 73else() 74 set(default_hyp_support OFF) 75endif() 76config_option( 77 KernelArmHypervisorSupport ARM_HYPERVISOR_SUPPORT 78 "Build as Hypervisor. Utilise ARM virtualisation extensions to build the kernel as a hypervisor" 79 DEFAULT ${default_hyp_support} 80 DEPENDS "KernelArmCortexA15 OR KernelArmCortexA57 OR KernelArmCortexA53" 81) 82 83config_option( 84 KernelArmHypEnableVCPUCP14SaveAndRestore ARM_HYP_ENABLE_VCPU_CP14_SAVE_AND_RESTORE 85 "Trap, but don't save/restore VCPUs' CP14 accesses \ 86 This allows us to turn off the save and restore of VCPU threads' CP14 \ 87 context for performance (or other) reasons, we can just turn them off \ 88 and trap them instead, and have the VCPUs' accesses to CP14 \ 89 intercepted and delivered to the VM Monitor as fault messages" 90 DEFAULT ON 91 DEPENDS "KernelSel4ArmHypAarch32;NOT KernelVerificationBuild" 92 DEFAULT_DISABLED OFF 93) 94 95config_option( 96 KernelArmErrata430973 ARM_ERRATA_430973 97 "Enable workaround for 430973 Cortex-A8 (r1p0..r1p2) erratum \ 98 Enables a workaround for the 430973 Cortex-A8 (r1p0..r1p2) erratum. Error occurs \ 99 if code containing ARM/Thumb interworking branch is replaced by different code \ 100 at the same virtual address." 101 DEFAULT OFF 102 DEPENDS "KernelArchARM;KernelArmCortexA8" 103) 104 105config_option( 106 KernelArmErrata773022 ARM_ERRATA_773022 107 "Enable workaround for 773022 Cortex-A15 (r0p0..r0p4) erratum \ 108 Enables a workaround for the 773022 Cortex-A15 (r0p0..r0p4) erratum. Error occurs \ 109 on rare sequences of instructions and results in the loop buffer delivering \ 110 incorrect instructions. The work around is to disable the loop buffer" 111 DEFAULT ON 112 DEPENDS "KernelArchARM;KernelArmCortexA15" 113 DEFAULT_DISABLED OFF 114) 115 116config_option(KernelArmSMMU ARM_SMMU "Enable SystemMMU" DEFAULT OFF DEPENDS "KernelPlatformTx2") 117 118config_option( 119 KernelTk1SMMU TK1_SMMU "Enable SystemMMU for the Tegra TK1 SoC" 120 DEFAULT OFF 121 DEPENDS "KernelPlatformTK1" 122) 123 124config_option(KernelArmEnableA9Prefetcher ENABLE_A9_PREFETCHER "Enable Cortex-A9 prefetcher \ 125 Cortex-A9 has an L1 and L2 prefetcher. By default \ 126 they are disabled. This config options allows \ 127 them to be turned on. Enabling the prefetchers \ 128 requires that the kernel be in secure mode. ARM \ 129 documents indicate that as of r4p1 version of \ 130 Cortex-A9 the bits used to enable the prefetchers \ 131 no longer exist, it is not clear if this is just \ 132 a document error or not." DEFAULT OFF DEPENDS "KernelArmCortexA9") 133 134config_option( 135 KernelArmExportPMUUser EXPORT_PMU_USER "PL0 access to PMU. \ 136 Grant user access to Performance Monitoring Unit. \ 137 WARNING: While useful for evaluating performance, \ 138 this option opens timing and covert channels." 139 DEFAULT OFF 140 DEPENDS "KernelArchArmV7a OR KernelArchArmV8a;NOT KernelArmCortexA8" 141) 142 143config_option( 144 KernelArmDisableWFIWFETraps DISABLE_WFI_WFE_TRAPS "Disable the trapping of WFI \ 145 and WFE instructions when configuring the \ 146 Hyp Configuration Registor (HCR) of a VCPU" 147 DEFAULT OFF 148 DEPENDS "KernelArchArmV7a OR KernelArchArmV8a;KernelArmHypervisorSupport" 149) 150config_option(KernelTk1SMMUInterruptEnable SMMU_INTERRUPT_ENABLE "Enable SMMU interrupts. \ 151 SMMU interrupts currently only serve a debug purpose as \ 152 they are not forwarded to user level. Enabling this will \ 153 cause some fault types to print out a message in the kernel. \ 154 WARNING: Printing fault information is slow and rapid faults \ 155 can result in all time spent in the kernel printing fault \ 156 messages" DEFAULT "${KernelDebugBuild}" DEPENDS "KernelTk1SMMU" DEFAULT_DISABLED OFF) 157 158config_option( 159 KernelAArch32FPUEnableContextSwitch AARCH32_FPU_ENABLE_CONTEXT_SWITCH 160 "Enable hardware VFP and SIMD context switch \ 161 This enables the VFP and SIMD context switch on platforms with \ 162 hardware support, allowing the user to execute hardware VFP and SIMD \ 163 operations in a multithreading environment, instead of relying on \ 164 software emulation of FPU/VFP from the C library (e.g. mfloat-abi=soft)." 165 DEFAULT ON 166 DEPENDS "KernelSel4ArchAarch32;NOT KernelArchArmV6;NOT KernelVerificationBuild" 167 DEFAULT_DISABLED OFF 168) 169 170if(KernelAArch32FPUEnableContextSwitch OR KernelSel4ArchAarch64) 171 set(KernelHaveFPU ON) 172endif() 173 174if(KernelSel4ArchAarch64) 175 set(KernelHardwareDebugAPIUnsupported ON CACHE INTERNAL "") 176endif() 177 178if( 179 KernelArmCortexA7 180 OR KernelArmCortexA8 181 OR KernelArmCortexA15 182 OR KernelArmCortexA53 183 OR KernelArmCortexA57 184) 185 config_set(KernelArmCacheLineSizeBits L1_CACHE_LINE_SIZE_BITS "6") 186elseif(KernelArmCortexA9 OR KernelArm1136JF_S) 187 config_set(KernelArmCacheLineSizeBits L1_CACHE_LINE_SIZE_BITS "5") 188endif() 189 190if(KernelArchArmV6) 191 # This is currently needed in ARMv6 to provide thread IDs via the 192 # globals frame. The globals frame should be removed along with this 193 # in favour of reserving r9 as a thread ID register. 194 # 195 # See SELFOUR-2253 196 set(KernelSetTLSBaseSelf ON) 197endif() 198 199# Provides a 4K region of read-only memory mapped into every vspace to 200# provide a virtual thread-id register not otherwise provided by the 201# platform. 202config_set(KernelGlobalsFrame KERNEL_GLOBALS_FRAME ${KernelArchArmV6}) 203 204add_sources( 205 DEP "KernelArchARM" 206 PREFIX src/arch/arm 207 CFILES 208 c_traps.c 209 api/faults.c 210 benchmark/benchmark.c 211 kernel/boot.c 212 kernel/thread.c 213 machine/cache.c 214 machine/errata.c 215 machine/debug.c 216 machine/hardware.c 217 object/interrupt.c 218 object/tcb.c 219 object/iospace.c 220 object/vcpu.c 221 object/smmu.c 222 smp/ipi.c 223) 224 225add_bf_source_old("KernelArchARM" "structures.bf" "include/arch/arm" "arch/object") 226 227include(src/arch/arm/${KernelWordSize}/config.cmake) 228