1/*
2 * Copyright 2017, Data61
3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
4 * ABN 41 687 119 230.
5 *
6 * This software may be distributed and modified according to the terms of
7 * the BSD 2-Clause license. Note that NO WARRANTY is provided.
8 * See "LICENSE_BSD2.txt" for details.
9 *
10 * @TAG(DATA61_BSD)
11 */
12#include <platsupport/plat/mux.h>
13
14#include "mux_gpio_priv.h"
15
16/* This table has the bitshift and mask values for the pingroup drive-strength
17 * bits. Each group has potentially different shifts and masks, so it's easier
18 * to just use a table.
19 */
20const mux_group_bitoff_mapping_t mux_group_bitinfo_mapping_table[] = {
21    { TK1MUX_GROUP_OFFSET_GMACFG, 14, 20, 0x1F, 0x1F },
22    { TK1MUX_GROUP_OFFSET_SDIO1CFG, 12, 20, 0x7F, 0x7F },
23    { TK1MUX_GROUP_OFFSET_SDIO3CFG, 12, 20, 0x7F, 0x7F },
24    { TK1MUX_GROUP_OFFSET_SDIO4CFG, 12, 20, 0x1F, 0x1F },
25    { TK1MUX_GROUP_OFFSET_AOCFG0, 12, 20, 0x1F, 0x1F },
26    { TK1MUX_GROUP_OFFSET_AOCFG1, 12, 20, 0x1F, 0x1F },
27    { TK1MUX_GROUP_OFFSET_AOCFG2, 12, 20, 0x1F, 0x1F },
28    { TK1MUX_GROUP_OFFSET_AOCFG3, 12, 0, 0x1F, 0 },
29    { TK1MUX_GROUP_OFFSET_AOCFG4, 12, 20, 0x7F, 0x7F },
30    { TK1MUX_GROUP_OFFSET_CDEV1CFG, 12, 20, 0x1F, 0x1F },
31    { TK1MUX_GROUP_OFFSET_CDEV2CFG, 12, 20, 0x1F, 0x1F },
32    { TK1MUX_GROUP_OFFSET_CECCFG, 12, 20, 0x1F, 0x1F },
33    { TK1MUX_GROUP_OFFSET_DAP1CFG, 12, 20, 0x1F, 0x1F },
34    { TK1MUX_GROUP_OFFSET_DAP2CFG, 12, 20, 0x1F, 0x1F },
35    { TK1MUX_GROUP_OFFSET_DAP3CFG, 12, 20, 0x1F, 0x1F },
36    { TK1MUX_GROUP_OFFSET_DAP4CFG, 12, 20, 0x1F, 0x1F },
37    { TK1MUX_GROUP_OFFSET_DAP5CFG, 12, 20, 0x1F, 0x1F },
38    { TK1MUX_GROUP_OFFSET_DBGCFG, 12, 20, 0x1F, 0x1F },
39    { TK1MUX_GROUP_OFFSET_DDCCFG, 12, 20, 0x1F, 0x1F },
40    { TK1MUX_GROUP_OFFSET_DEV3CFG, 12, 20, 0x1F, 0x1F },
41    { TK1MUX_GROUP_OFFSET_OWRCFG, 12, 20, 0x1F, 0x1F },
42    { TK1MUX_GROUP_OFFSET_SPICFG, 12, 20, 0x1F, 0x1F },
43    { TK1MUX_GROUP_OFFSET_UAACFG, 12, 20, 0x1F, 0x1F },
44    { TK1MUX_GROUP_OFFSET_UABCFG, 12, 20, 0x1F, 0x1F },
45    { TK1MUX_GROUP_OFFSET_UART2CFG, 12, 20, 0x1F, 0x1F },
46    { TK1MUX_GROUP_OFFSET_UART3CFG, 12, 20, 0x1F, 0x1F },
47    { TK1MUX_GROUP_OFFSET_UDACFG, 12, 20, 0x1F, 0x1F },
48    { TK1MUX_GROUP_OFFSET_ATCFG1, 12, 20, 0x7F, 0x7F },
49    { TK1MUX_GROUP_OFFSET_ATCFG2, 12, 20, 0x7F, 0x7F },
50    { TK1MUX_GROUP_OFFSET_ATCFG3, 12, 20, 0x7F, 0x7F },
51    { TK1MUX_GROUP_OFFSET_ATCFG4, 12, 20, 0x7F, 0x7F },
52    { TK1MUX_GROUP_OFFSET_ATCFG5, 14, 19, 0x1F, 0x1F },
53    { TK1MUX_GROUP_OFFSET_ATCFG6, 12, 20, 0x7F, 0x7F },
54    { TK1MUX_GROUP_OFFSET_GMECFG, 14, 19, 0x1F, 0x1F },
55    { TK1MUX_GROUP_OFFSET_GMFCFG, 14, 19, 0x1F, 0x1F },
56    { TK1MUX_GROUP_OFFSET_GMGCFG, 14, 19, 0x1F, 0x1F },
57    { TK1MUX_GROUP_OFFSET_GMHCFG, 14, 19, 0x1F, 0x1F },
58    { TK1MUX_GROUP_OFFSET_HVCFG0, 12, 0, 0x1F, 0 },
59    { TK1MUX_GROUP_OFFSET_GPVCFG, 21, 20, 0x1F, 0x1F },
60    { TK1MUX_GROUP_OFFSET_USB_VBUS_EN_CFG, 12, 20, 0x1F, 0x1F }
61};
62
63int
64array_size_bitinfo_mapping_table(void)
65{
66    return ARRAY_SIZE(mux_group_bitinfo_mapping_table);
67}
68
69/* This table maps each mux pin to its group control register. Each pin is part
70 * of a group, such that you can configure these groups with common settings.
71 *
72 * Later on, this table might be updated with wakeup information and pin type
73 * information as well.
74 */
75const mux_pin_group_mapping_t mux_pin_group_mapping_table[] = {
76    { MUX_PAD_ULPI_DATA0_PO1, UAACFG },
77    { MUX_PAD_ULPI_DATA1_PO2, UAACFG },
78    { MUX_PAD_ULPI_DATA2_PO3, UAACFG },
79    { MUX_PAD_ULPI_DATA3_PO4, UAACFG },
80    { MUX_PAD_ULPI_DATA4_PO5, UABCFG },
81    { MUX_PAD_ULPI_DATA5_PO6, UABCFG },
82    { MUX_PAD_ULPI_DATA6_PO7, UABCFG },
83    { MUX_PAD_ULPI_DATA7_PO0, UABCFG },
84    { MUX_PAD_ULPI_CLK_PY0, UDACFG },
85    { MUX_PAD_ULPI_DIR_PY1, UDACFG },
86    { MUX_PAD_ULPI_NXT_PY2, UDACFG },
87    { MUX_PAD_ULPI_STP_PY3, UDACFG },
88    { MUX_PAD_DAP3_FS_PP0, DAP3CFG },
89    { MUX_PAD_DAP3_DIN_PP1, DAP3CFG },
90    { MUX_PAD_DAP3_DOUT_PP2, DAP3CFG },
91    { MUX_PAD_DAP3_SCLK_PP3, DAP3CFG },
92    { MUX_PAD_PV0, UABCFG },
93    { MUX_PAD_PV1, UABCFG },
94    { MUX_PAD_SDMMC1_CLK_PZ0, SDIO1CFG },
95    { MUX_PAD_SDMMC1_CMD_PZ1, SDIO1CFG },
96    { MUX_PAD_SDMMC1_DAT3_PY4, SDIO1CFG },
97    { MUX_PAD_SDMMC1_DAT2_PY5, SDIO1CFG },
98    { MUX_PAD_SDMMC1_DAT1_PY6, SDIO1CFG },
99    { MUX_PAD_SDMMC1_DAT0_PY7, SDIO1CFG },
100    { MUX_PAD_CLK2_OUT_PW5, CDEV2CFG },
101    { MUX_PAD_CLK2_REQ_PCC5, CDEV2CFG },
102    { MUX_PAD_HDMI_INT_PN7, HVCFG0 },
103    { MUX_PAD_DDC_SCL_PV4, DDCCFG },
104    { MUX_PAD_DDC_SDA_PV5, DDCCFG },
105    { MUX_PAD_UART2_RXD_PC3, UART2CFG },
106    { MUX_PAD_UART2_TXD_PC2, UART2CFG },
107    { MUX_PAD_UART2_RTS_N_PJ6, UART2CFG },
108    { MUX_PAD_UART2_CTS_N_PJ5, UART2CFG },
109    { MUX_PAD_UART3_TXD_PW6, UART3CFG },
110    { MUX_PAD_UART3_RXD_PW7, UART3CFG },
111    { MUX_PAD_UART3_CTS_N_PA1, UART3CFG },
112    { MUX_PAD_UART3_RTS_N_PC0, UART3CFG },
113    { MUX_PAD_PU0, DBGCFG },
114    { MUX_PAD_PU1, DBGCFG },
115    { MUX_PAD_PU2, DBGCFG },
116    { MUX_PAD_PU3, DBGCFG },
117    { MUX_PAD_PU4, DBGCFG },
118    { MUX_PAD_PU5, DBGCFG },
119    { MUX_PAD_PU6, DBGCFG },
120    { MUX_PAD_GEN1_I2C_SDA_PC5, TK1MUX_GROUP_OFFSET_DBGCFG },
121    { MUX_PAD_GEN1_I2C_SCL_PC4, TK1MUX_GROUP_OFFSET_DBGCFG },
122    { MUX_PAD_DAP4_FS_PP4, DAP4CFG },
123    { MUX_PAD_DAP4_DIN_PP5, DAP4CFG },
124    { MUX_PAD_DAP4_DOUT_PP6, DAP4CFG },
125    { MUX_PAD_DAP4_SCLK_PP7, DAP4CFG },
126    { MUX_PAD_CLK3_OUT_PEE0, DEV3CFG },
127    { MUX_PAD_CLK3_REQ_PEE1, DEV3CFG },
128    { MUX_PAD_PC7, ATCFG3 },
129    { MUX_PAD_PI5, ATCFG6 },
130    { MUX_PAD_PI7, ATCFG2 },
131    { MUX_PAD_PK0, ATCFG2 },
132    { MUX_PAD_PK1, ATCFG6 },
133    { MUX_PAD_PJ0, ATCFG3 },
134    { MUX_PAD_PJ2, ATCFG4 },
135    { MUX_PAD_PK3, ATCFG6 },
136    { MUX_PAD_PK4, ATCFG6 },
137    { MUX_PAD_PK2, ATCFG2 },
138    { MUX_PAD_PI3, ATCFG2 },
139    { MUX_PAD_PI6, ATCFG6 },
140    { MUX_PAD_PG0, ATCFG2 },
141    { MUX_PAD_PG1, ATCFG2 },
142    { MUX_PAD_PG2, ATCFG2 },
143    { MUX_PAD_PG3, ATCFG2 },
144    { MUX_PAD_PG4, ATCFG2 },
145    { MUX_PAD_PG5, ATCFG2 },
146    { MUX_PAD_PG6, ATCFG2 },
147    { MUX_PAD_PG7, ATCFG2 },
148    { MUX_PAD_PH0, ATCFG1 },
149    { MUX_PAD_PH1, ATCFG1 },
150    { MUX_PAD_PH2, ATCFG1 },
151    { MUX_PAD_PH3, ATCFG1 },
152    { MUX_PAD_PH4, ATCFG6 },
153    { MUX_PAD_PH5, ATCFG6 },
154    { MUX_PAD_PH6, ATCFG6 },
155    { MUX_PAD_PH7, ATCFG6 },
156    { MUX_PAD_PJ7, ATCFG4 },
157    { MUX_PAD_PB0, ATCFG4 },
158    { MUX_PAD_PB1, ATCFG4 },
159    { MUX_PAD_PK7, ATCFG4 },
160    { MUX_PAD_PI0, ATCFG2 },
161    { MUX_PAD_PI1, ATCFG2 },
162    { MUX_PAD_PI2, ATCFG6 },
163    { MUX_PAD_PI4, ATCFG2 },
164    { MUX_PAD_GEN2_I2C_SCL_PT5, ATCFG5 },
165    { MUX_PAD_GEN2_I2C_SDA_PT6, ATCFG5 },
166    { MUX_PAD_SDMMC4_CLK_PCC4, GMACFG },
167    { MUX_PAD_SDMMC4_CMD_PT7, GMACFG },
168    { MUX_PAD_SDMMC4_DAT0_PAA0, GMACFG },
169    { MUX_PAD_SDMMC4_DAT1_PAA1, GMACFG },
170    { MUX_PAD_SDMMC4_DAT2_PAA2, GMACFG },
171    { MUX_PAD_SDMMC4_DAT3_PAA3, GMACFG },
172    { MUX_PAD_SDMMC4_DAT4_PAA4, GMACFG },
173    { MUX_PAD_SDMMC4_DAT5_PAA5, GMACFG },
174    { MUX_PAD_SDMMC4_DAT6_PAA6, GMACFG },
175    { MUX_PAD_SDMMC4_DAT7_PAA7, GMACFG },
176    { MUX_PAD_CAM_MCLK_PCC0, GMGCFG },
177    { MUX_PAD_PCC1, GMHCFG },
178    { MUX_PAD_PBB0, GMECFG },
179    { MUX_PAD_CAM_I2C_SCL_PBB1, TK1MUX_GROUP_OFFSET_GMECFG },
180    { MUX_PAD_CAM_I2C_SDA_PBB2, TK1MUX_GROUP_OFFSET_GMECFG },
181    { MUX_PAD_PBB3, GMECFG },
182    { MUX_PAD_PBB4, GMFCFG },
183    { MUX_PAD_PBB5, GMFCFG },
184    { MUX_PAD_PBB6, GMFCFG },
185    { MUX_PAD_PBB7, GMFCFG },
186    { MUX_PAD_PCC2, GMECFG },
187    { MUX_PAD_JTAG_RTCK, AOCFG0 },
188    { MUX_PAD_PWR_I2C_SCL_PZ6, AOCFG1 },
189    { MUX_PAD_PWR_I2C_SDA_PZ7, AOCFG1 },
190    { MUX_PAD_KB_ROW0_PR0, AOCFG1 },
191    { MUX_PAD_KB_ROW1_PR1, AOCFG1 },
192    { MUX_PAD_KB_ROW2_PR2, AOCFG1 },
193    { MUX_PAD_KB_ROW3_PR3, AOCFG1 },
194    { MUX_PAD_KB_ROW4_PR4, AOCFG1 },
195    { MUX_PAD_KB_ROW5_PR5, AOCFG1 },
196    { MUX_PAD_KB_ROW6_PR6, AOCFG1 },
197    { MUX_PAD_KB_ROW7_PR7, AOCFG1 },
198    { MUX_PAD_KB_ROW8_PS0, AOCFG2 },
199    { MUX_PAD_KB_ROW9_PS1, AOCFG2 },
200    { MUX_PAD_KB_ROW10_PS2, AOCFG2 },
201    { MUX_PAD_KB_ROW11_PS3, AOCFG2 },
202    { MUX_PAD_KB_ROW12_PS4, AOCFG2 },
203    { MUX_PAD_KB_ROW13_PS5, AOCFG2 },
204    { MUX_PAD_KB_ROW14_PS6, AOCFG2 },
205    { MUX_PAD_KB_ROW15_PS7, AOCFG2 },
206    { MUX_PAD_KB_COL0_PQ0, AOCFG2 },
207    { MUX_PAD_KB_COL1_PQ1, AOCFG2 },
208    { MUX_PAD_KB_COL2_PQ2, AOCFG2 },
209    { MUX_PAD_KB_COL3_PQ3, AOCFG2 },
210    { MUX_PAD_KB_COL4_PQ4, AOCFG2 },
211    { MUX_PAD_KB_COL5_PQ5, AOCFG2 },
212    { MUX_PAD_KB_COL6_PQ6, AOCFG2 },
213    { MUX_PAD_KB_COL7_PQ7, AOCFG2 },
214    { MUX_PAD_CLK_32K_OUT_PA0, AOCFG2 },
215    { MUX_PAD_CORE_PWR_REQ, 0 },
216    { MUX_PAD_CPU_PWR_REQ, 0 },
217    { MUX_PAD_PWR_INT_N, 0 },
218    { MUX_PAD_CLK_32K_IN, AOCFG2 },
219    { MUX_PAD_OWR, OWRCFG },
220    { MUX_PAD_DAP1_FS_PN0, DAP1CFG },
221    { MUX_PAD_DAP1_DIN_PN1, DAP1CFG },
222    { MUX_PAD_DAP1_DOUT_PN2, DAP1CFG },
223    { MUX_PAD_DAP1_SCLK_PN3, DAP1CFG },
224    { MUX_PAD_DAP_MCLK1_REQ_PEE2, CDEV1CFG },
225    { MUX_PAD_DAP_MCLK1_PW4, CDEV1CFG },
226    { MUX_PAD_SPDIF_IN_PK6, DAP5CFG },
227    { MUX_PAD_SPDIF_OUT_PK5, DAP5CFG },
228    { MUX_PAD_DAP2_FS_PA2, DAP2CFG },
229    { MUX_PAD_DAP2_DIN_PA4, DAP2CFG },
230    { MUX_PAD_DAP2_DOUT_PA5, DAP2CFG },
231    { MUX_PAD_DAP2_SCLK_PA3, DAP2CFG },
232    { MUX_PAD_DVFS_PWM_PX0, SPICFG },
233    { MUX_PAD_GPIO_X1_AUD_PX1, SPICFG },
234    { MUX_PAD_GPIO_X3_AUD_PX3, SPICFG },
235    { MUX_PAD_DVFS_CLK_PX2, SPICFG },
236    { MUX_PAD_GPIO_X4_AUD_PX4, SPICFG },
237    { MUX_PAD_GPIO_X5_AUD_PX5, SPICFG },
238    { MUX_PAD_GPIO_X6_AUD_PX6, SPICFG },
239    { MUX_PAD_GPIO_X7_AUD_PX7, SPICFG },
240    { MUX_PAD_SDMMC3_CLK_PA6, SDIO3CFG },
241    { MUX_PAD_SDMMC3_CMD_PA7, SDIO3CFG },
242    { MUX_PAD_SDMMC3_DAT0_PB7, SDIO3CFG },
243    { MUX_PAD_SDMMC3_DAT1_PB6, SDIO3CFG },
244    { MUX_PAD_SDMMC3_DAT2_PB5, SDIO3CFG },
245    { MUX_PAD_SDMMC3_DAT3_PB4, SDIO3CFG },
246    { MUX_PAD_PEX_L0_RST_N_PDD1, GPVCFG },
247    { MUX_PAD_PEX_L0_CLKREQ_N_PDD2, GPVCFG },
248    { MUX_PAD_PEX_WAKE_N_PDD3, GPVCFG },
249    { MUX_PAD_PEX_L1_RST_N_PDD5, GPVCFG },
250    { MUX_PAD_PEX_L1_CLKREQ_N_PDD6, GPVCFG },
251    { MUX_PAD_HDMI_CEC_PEE3, CECCFG },
252    { MUX_PAD_SDMMC1_WP_N_PV3, SDIO4CFG },
253    { MUX_PAD_SDMMC3_CD_N_PV2, AOCFG2 },
254    { MUX_PAD_GPIO_W2_AUD_PW2, SPICFG },
255    { MUX_PAD_GPIO_W3_AUD_PW3, SPICFG },
256    { MUX_PAD_USB_VBUS_EN0_PN4, USB_VBUS_EN_CFG },
257    { MUX_PAD_USB_VBUS_EN1_PN5, USB_VBUS_EN_CFG },
258    { MUX_PAD_SDMMC3_CLK_LB_IN_PEE5, SDIO3CFG },
259    { MUX_PAD_SDMMC3_CLK_LB_OUT_PEE4, SDIO3CFG },
260    { MUX_PAD_GMI_CLK_LB, 0 },
261    { MUX_PAD_RESET_OUT_N, 0 },
262    { MUX_PAD_KB_ROW16_PT0, AOCFG2 },
263    { MUX_PAD_KB_ROW17_PT1, AOCFG2 },
264    { MUX_PAD_USB_VBUS_EN2_PFF1, GPVCFG },
265    { MUX_PAD_PFF2, GPVCFG },
266    { MUX_PAD_DP_HPD_PFF0, DAP5CFG }
267};
268
269int
270array_size_pin_group_mapping_table(void)
271{
272    return ARRAY_SIZE(mux_pin_group_mapping_table);
273}
274