1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 8 * See "LICENSE_BSD2.txt" for details. 9 * 10 * @TAG(DATA61_BSD) 11 */ 12 13#include <stdio.h> 14#include <assert.h> 15#include <errno.h> 16#include <stdlib.h> 17#include <utils/util.h> 18 19#include <platsupport/clock.h> 20#include <platsupport/plat/clock.h> 21 22#include "../../services.h" 23 24/* Register information sourced from "NVIDIA Tegra K1 Mobile Processor TECHNICAL REFERENCE MANUAL" */ 25 26#define CLK_REGISTER_ENTRY(a) {.reg_type = a} 27#define CLK_REGISTER_ENTRY_SOURCE(b) {.reg_type = CLK_SOURCE, .st = {.clks = b}} 28#define CLK_REGISTER_ENTRY_ENBRST(a,b) {.reg_type = CLK_ENBRST_DEVICES, .eb = {.rb = a, .at = b}} 29#define NULL_CLK_REGISTER_ENTRY CLK_REGISTER_ENTRY(CLK_RESERVED) 30 31/* Struct that describes register layout. 32 this was done for quick lookup from device address to register type and info 33 An array is used, sizeof(clk_register_t) is about 3 words (3 enums) because 34 it is easier to declare everything inline using #defines, and the number of 35 NULL_CLK_REGISTER_ENTRYs is about 30-35% of the array. 36 */ 37const clk_register_t tk1_clk_registers[] = { 38 // 0x0 39 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_RST_SOURCE_0 40 CLK_REGISTER_ENTRY_ENBRST(REG_L, RST_VAL), // CLK_RST_CONTROLLER_RST_DEVICES_L_0 41 CLK_REGISTER_ENTRY_ENBRST(REG_H, RST_VAL), // CLK_RST_CONTROLLER_RST_DEVICES_H_0 42 CLK_REGISTER_ENTRY_ENBRST(REG_U, RST_VAL), // CLK_RST_CONTROLLER_RST_DEVICES_U_0 43 // 0x10 44 CLK_REGISTER_ENTRY_ENBRST(REG_L, ENB_VAL), // CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0 45 CLK_REGISTER_ENTRY_ENBRST(REG_H, ENB_VAL), // CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0 46 CLK_REGISTER_ENTRY_ENBRST(REG_U, ENB_VAL), // CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0 47 NULL_CLK_REGISTER_ENTRY, // Reserved 48 // 0x20 49 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0 50 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0 51 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0 52 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0 53 // 0x30 54 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0 55 NULL_CLK_REGISTER_ENTRY, // Reserved 56 NULL_CLK_REGISTER_ENTRY, // Reserved 57 NULL_CLK_REGISTER_ENTRY, // Reserved 58 // 0x40 59 NULL_CLK_REGISTER_ENTRY, // Reserved 60 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CLK_MASK_ARM_0 61 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_MISC_CLK_ENB_0 62 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 63 // 0x50 64 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_OSC_CTRL_0 65 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_PLL_LFSR_0 66 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_OSC_FREQ_DET_0 67 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0 68 // 0x60 69 NULL_CLK_REGISTER_ENTRY, // Reserved 70 NULL_CLK_REGISTER_ENTRY, // Reserved 71 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLE_SS_CNTL_0 72 NULL_CLK_REGISTER_ENTRY, // Reserved 73 // 0x70 74 NULL_CLK_REGISTER_ENTRY, // Reserved 75 NULL_CLK_REGISTER_ENTRY, // Reserved 76 NULL_CLK_REGISTER_ENTRY, // Reserved 77 NULL_CLK_REGISTER_ENTRY, // Reserved 78 // 0x80 79 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLC_BASE_0 80 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLC_OUT_0 81 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLC_MISC2_0 82 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLC_MISC_0 83 // 0x90 84 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLM_BASE_0 85 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLM_OUT_0 86 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLM_MISC1_0 87 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLM_MISC2_0 88 // 0xa0 89 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLP_BASE_0 90 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLP_OUTA_0 91 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLP_OUTB_0 92 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLP_MISC_0 93 // 0xb0 94 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLA_BASE_0 95 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLA_OUT_0 96 NULL_CLK_REGISTER_ENTRY, // Reserved 97 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLA_MISC_0 98 // 0xc0 99 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLU_BASE_0 100 NULL_CLK_REGISTER_ENTRY, // Reserved 101 NULL_CLK_REGISTER_ENTRY, // Reserved 102 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLU_MISC_0 103 // 0xd0 104 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLD_BASE_0 105 NULL_CLK_REGISTER_ENTRY, // Reserved 106 NULL_CLK_REGISTER_ENTRY, // Reserved 107 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLD_MISC_0 108 // 0xe0 109 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLX_BASE_0 110 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLX_MISC_0 111 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLE_BASE_0 112 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLE_MISC_0 113 // 0xf0 114 NULL_CLK_REGISTER_ENTRY, // Reserved 115 NULL_CLK_REGISTER_ENTRY, // Reserved 116 NULL_CLK_REGISTER_ENTRY, // Reserved 117 NULL_CLK_REGISTER_ENTRY, // Reserved 118 // 0x100 119 CLK_REGISTER_ENTRY_SOURCE(i2s1_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0 120 CLK_REGISTER_ENTRY_SOURCE(i2s2_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0 121 CLK_REGISTER_ENTRY_SOURCE(spdif_out_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0 122 CLK_REGISTER_ENTRY_SOURCE(spdif_in_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0 123 // 0x110 124 CLK_REGISTER_ENTRY_SOURCE(pwm_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0 125 NULL_CLK_REGISTER_ENTRY, // Reserved 126 CLK_REGISTER_ENTRY_SOURCE(spi2_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0 127 CLK_REGISTER_ENTRY_SOURCE(spi3_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0 128 // 0x120 129 NULL_CLK_REGISTER_ENTRY, // Reserved 130 CLK_REGISTER_ENTRY_SOURCE(i2c1_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0 131 CLK_REGISTER_ENTRY_SOURCE(i2c5_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0 132 NULL_CLK_REGISTER_ENTRY, // Reserved 133 // 0x130 134 NULL_CLK_REGISTER_ENTRY, // Reserved 135 CLK_REGISTER_ENTRY_SOURCE(spi1_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0 136 CLK_REGISTER_ENTRY_SOURCE(display_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0 137 CLK_REGISTER_ENTRY_SOURCE(displayb_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0 138 // 0x140 139 NULL_CLK_REGISTER_ENTRY, // Reserved 140 CLK_REGISTER_ENTRY_SOURCE(isp_r_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0 141 CLK_REGISTER_ENTRY_SOURCE(vi_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_VI_0 142 NULL_CLK_REGISTER_ENTRY, // Reserved 143 // 0x150 144 CLK_REGISTER_ENTRY_SOURCE(sdmmc1_r_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0 145 CLK_REGISTER_ENTRY_SOURCE(sdmmc2_r_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0 146 NULL_CLK_REGISTER_ENTRY, // Reserved 147 NULL_CLK_REGISTER_ENTRY, // Reserved 148 // 0x160 149 NULL_CLK_REGISTER_ENTRY, // Reserved 150 CLK_REGISTER_ENTRY_SOURCE(sdmmc4_r_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0 151 CLK_REGISTER_ENTRY_SOURCE(vfir_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0 152 NULL_CLK_REGISTER_ENTRY, // Reserved 153 // 0x170 154 NULL_CLK_REGISTER_ENTRY, // Reserved 155 CLK_REGISTER_ENTRY_SOURCE(hsi_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_HSI_0 156 CLK_REGISTER_ENTRY_SOURCE(uarta_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0 157 CLK_REGISTER_ENTRY_SOURCE(uartb_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0 158 // 0x180 159 CLK_REGISTER_ENTRY_SOURCE(host1x_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0 160 NULL_CLK_REGISTER_ENTRY, // Reserved 161 NULL_CLK_REGISTER_ENTRY, // Reserved 162 CLK_REGISTER_ENTRY_SOURCE(hdmi_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0 163 // 0x190 164 NULL_CLK_REGISTER_ENTRY, // Reserved 165 NULL_CLK_REGISTER_ENTRY, // Reserved 166 CLK_REGISTER_ENTRY_SOURCE(i2c2_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0 167 CLK_REGISTER_ENTRY_SOURCE(NUM_OTHER_CLOCKS), // TODO CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0 168 // 0x1a0 169 CLK_REGISTER_ENTRY_SOURCE(uartc_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0 170 NULL_CLK_REGISTER_ENTRY, // Reserved 171 CLK_REGISTER_ENTRY_SOURCE(vi_sensor_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0 172 NULL_CLK_REGISTER_ENTRY, // Reserved 173 // 0x1b0 174 NULL_CLK_REGISTER_ENTRY, // Reserved 175 CLK_REGISTER_ENTRY_SOURCE(spi4_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0 176 CLK_REGISTER_ENTRY_SOURCE(i2c3_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0 177 CLK_REGISTER_ENTRY_SOURCE(sdmmc3_r_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0 178 // 0x1c0 179 CLK_REGISTER_ENTRY_SOURCE(uartd_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0 180 NULL_CLK_REGISTER_ENTRY, // Reserved 181 CLK_REGISTER_ENTRY_SOURCE(vde_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0 182 CLK_REGISTER_ENTRY_SOURCE(owr_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0 183 // 0x1d0 184 CLK_REGISTER_ENTRY_SOURCE(nor_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0 185 CLK_REGISTER_ENTRY_SOURCE(csite_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0 186 CLK_REGISTER_ENTRY_SOURCE(i2s0_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_I2S0_0 187 CLK_REGISTER_ENTRY_SOURCE(NUM_OTHER_CLOCKS), // TODO CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0 188 // 0x1e0 189 NULL_CLK_REGISTER_ENTRY, // Reserved 190 NULL_CLK_REGISTER_ENTRY, // Reserved 191 NULL_CLK_REGISTER_ENTRY, // Reserved 192 NULL_CLK_REGISTER_ENTRY, // Reserved 193 // 0x1f0 194 CLK_REGISTER_ENTRY_SOURCE(msenc_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_MSENC_0 195 CLK_REGISTER_ENTRY_SOURCE(tsec_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0 196 NULL_CLK_REGISTER_ENTRY, // Reserved 197 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CLK_SPARE2_0 198 // 0x200 199 NULL_CLK_REGISTER_ENTRY, // Reserved 200 NULL_CLK_REGISTER_ENTRY, // Reserved 201 NULL_CLK_REGISTER_ENTRY, // Reserved 202 NULL_CLK_REGISTER_ENTRY, // Reserved 203 // 0x210 204 NULL_CLK_REGISTER_ENTRY, // Reserved 205 NULL_CLK_REGISTER_ENTRY, // Reserved 206 NULL_CLK_REGISTER_ENTRY, // Reserved 207 NULL_CLK_REGISTER_ENTRY, // Reserved 208 // 0x220 209 NULL_CLK_REGISTER_ENTRY, // Reserved 210 NULL_CLK_REGISTER_ENTRY, // Reserved 211 NULL_CLK_REGISTER_ENTRY, // Reserved 212 NULL_CLK_REGISTER_ENTRY, // Reserved 213 // 0x230 214 NULL_CLK_REGISTER_ENTRY, // Reserved 215 NULL_CLK_REGISTER_ENTRY, // Reserved 216 NULL_CLK_REGISTER_ENTRY, // Reserved 217 NULL_CLK_REGISTER_ENTRY, // Reserved 218 // 0x240 219 NULL_CLK_REGISTER_ENTRY, // Reserved 220 NULL_CLK_REGISTER_ENTRY, // Reserved 221 NULL_CLK_REGISTER_ENTRY, // Reserved 222 NULL_CLK_REGISTER_ENTRY, // Reserved 223 // 0x250 224 NULL_CLK_REGISTER_ENTRY, // Reserved 225 NULL_CLK_REGISTER_ENTRY, // Reserved 226 NULL_CLK_REGISTER_ENTRY, // Reserved 227 NULL_CLK_REGISTER_ENTRY, // Reserved 228 // 0x260 229 NULL_CLK_REGISTER_ENTRY, // Reserved 230 NULL_CLK_REGISTER_ENTRY, // Reserved 231 NULL_CLK_REGISTER_ENTRY, // Reserved 232 NULL_CLK_REGISTER_ENTRY, // Reserved 233 // 0x270 234 NULL_CLK_REGISTER_ENTRY, // Reserved 235 NULL_CLK_REGISTER_ENTRY, // Reserved 236 NULL_CLK_REGISTER_ENTRY, // Reserved 237 NULL_CLK_REGISTER_ENTRY, // Reserved 238 // 0x280 239 CLK_REGISTER_ENTRY_ENBRST(REG_X, ENB_VAL), // CLK_RST_CONTROLLER_CLK_OUT_ENB_X_0 240 CLK_REGISTER_ENTRY_ENBRST(REG_X, ENB_SET), // CLK_RST_CONTROLLER_CLK_ENB_X_SET_0 241 CLK_REGISTER_ENTRY_ENBRST(REG_X, ENB_CLR), // CLK_RST_CONTROLLER_CLK_ENB_X_CLR_0 242 CLK_REGISTER_ENTRY_ENBRST(REG_X, RST_VAL), // CLK_RST_CONTROLLER_RST_DEVICES_X_0 243 // 0x290 244 CLK_REGISTER_ENTRY_ENBRST(REG_X, RST_SET), // CLK_RST_CONTROLLER_RST_DEV_X_SET_0 245 CLK_REGISTER_ENTRY_ENBRST(REG_X, RST_CLR), // CLK_RST_CONTROLLER_RST_DEV_X_CLR_0 246 NULL_CLK_REGISTER_ENTRY, // Reserved 247 NULL_CLK_REGISTER_ENTRY, // Reserved 248 // 0x2a0 249 NULL_CLK_REGISTER_ENTRY, // Reserved 250 NULL_CLK_REGISTER_ENTRY, // Reserved 251 NULL_CLK_REGISTER_ENTRY, // Reserved 252 NULL_CLK_REGISTER_ENTRY, // Reserved 253 // 0x2b0 254 NULL_CLK_REGISTER_ENTRY, // Reserved 255 NULL_CLK_REGISTER_ENTRY, // Reserved 256 NULL_CLK_REGISTER_ENTRY, // Reserved 257 NULL_CLK_REGISTER_ENTRY, // Reserved 258 // 0x2c0 259 NULL_CLK_REGISTER_ENTRY, // Reserved 260 NULL_CLK_REGISTER_ENTRY, // Reserved 261 NULL_CLK_REGISTER_ENTRY, // Reserved 262 NULL_CLK_REGISTER_ENTRY, // Reserved 263 // 0x2d0 264 NULL_CLK_REGISTER_ENTRY, // Reserved 265 NULL_CLK_REGISTER_ENTRY, // Reserved 266 NULL_CLK_REGISTER_ENTRY, // Reserved 267 NULL_CLK_REGISTER_ENTRY, // Reserved 268 // 0x2e0 269 NULL_CLK_REGISTER_ENTRY, // Reserved 270 NULL_CLK_REGISTER_ENTRY, // Reserved 271 NULL_CLK_REGISTER_ENTRY, // Reserved 272 NULL_CLK_REGISTER_ENTRY, // Reserved 273 // 0x2f0 274 NULL_CLK_REGISTER_ENTRY, // Reserved 275 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_DFLL_BASE_0 276 NULL_CLK_REGISTER_ENTRY, // Reserved 277 NULL_CLK_REGISTER_ENTRY, // Reserved 278 // 0x300 279 CLK_REGISTER_ENTRY_ENBRST(REG_L, RST_SET), // CLK_RST_CONTROLLER_RST_DEV_L_SET_0 280 CLK_REGISTER_ENTRY_ENBRST(REG_L, RST_CLR), // CLK_RST_CONTROLLER_RST_DEV_L_CLR_0 281 CLK_REGISTER_ENTRY_ENBRST(REG_H, RST_SET), // CLK_RST_CONTROLLER_RST_DEV_H_SET_0 282 CLK_REGISTER_ENTRY_ENBRST(REG_H, RST_CLR), // CLK_RST_CONTROLLER_RST_DEV_H_CLR_0 283 // 0x310 284 CLK_REGISTER_ENTRY_ENBRST(REG_U, RST_SET), // CLK_RST_CONTROLLER_RST_DEV_U_SET_0 285 CLK_REGISTER_ENTRY_ENBRST(REG_U, RST_CLR), // CLK_RST_CONTROLLER_RST_DEV_U_CLR_0 286 NULL_CLK_REGISTER_ENTRY, // Reserved 287 NULL_CLK_REGISTER_ENTRY, // Reserved 288 // 0x320 289 CLK_REGISTER_ENTRY_ENBRST(REG_L, ENB_SET), // CLK_RST_CONTROLLER_CLK_ENB_L_SET_0 290 CLK_REGISTER_ENTRY_ENBRST(REG_L, ENB_CLR), // CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0 291 CLK_REGISTER_ENTRY_ENBRST(REG_H, ENB_SET), // CLK_RST_CONTROLLER_CLK_ENB_H_SET_0 292 CLK_REGISTER_ENTRY_ENBRST(REG_H, ENB_CLR), // CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0 293 // 0x330 294 CLK_REGISTER_ENTRY_ENBRST(REG_U, ENB_SET), // CLK_RST_CONTROLLER_CLK_ENB_U_SET_0 295 CLK_REGISTER_ENTRY_ENBRST(REG_U, ENB_CLR), // CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0 296 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CCPLEX_PG_SM_OVRD_0 297 NULL_CLK_REGISTER_ENTRY, // Reserved 298 // 0x340 299 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0 300 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0 301 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CLK_CPU_CMPLX_SET_0 302 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR_0 303 // 0x350 304 NULL_CLK_REGISTER_ENTRY, // Reserved 305 NULL_CLK_REGISTER_ENTRY, // Reserved 306 CLK_REGISTER_ENTRY_ENBRST(REG_V, RST_VAL), // CLK_RST_CONTROLLER_RST_DEVICES_V_0 307 CLK_REGISTER_ENTRY_ENBRST(REG_W, RST_VAL), // CLK_RST_CONTROLLER_RST_DEVICES_W_0 308 // 0x360 309 CLK_REGISTER_ENTRY_ENBRST(REG_V, ENB_VAL), // CLK_RST_CONTROLLER_CLK_OUT_ENB_V_0 310 CLK_REGISTER_ENTRY_ENBRST(REG_W, ENB_VAL), // CLK_RST_CONTROLLER_CLK_OUT_ENB_W_0 311 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CCLKG_BURST_POLICY_0 312 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_SUPER_CCLKG_DIVIDER_0 313 // 0x370 314 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CCLKLP_BURST_POLICY_0 315 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_SUPER_CCLKLP_DIVIDER_0 316 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CLK_CPUG_CMPLX_0 317 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CLK_CPULP_CMPLX_0 318 // 0x380 319 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL_0 320 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL1_0 321 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0 322 NULL_CLK_REGISTER_ENTRY, // Reserved 323 // 0x390 324 NULL_CLK_REGISTER_ENTRY, // Reserved 325 NULL_CLK_REGISTER_ENTRY, // Reserved 326 NULL_CLK_REGISTER_ENTRY, // Reserved 327 NULL_CLK_REGISTER_ENTRY, // Reserved 328 // 0x3a0 329 NULL_CLK_REGISTER_ENTRY, // Reserved 330 NULL_CLK_REGISTER_ENTRY, // Reserved 331 NULL_CLK_REGISTER_ENTRY, // Reserved 332 NULL_CLK_REGISTER_ENTRY, // Reserved 333 // 0x3b0 334 NULL_CLK_REGISTER_ENTRY, // Reserved 335 CLK_REGISTER_ENTRY_SOURCE(mselect_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT_0 336 CLK_REGISTER_ENTRY_SOURCE(tsensor_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0 337 CLK_REGISTER_ENTRY_SOURCE(i2s3_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0 338 // 0x3c0 339 CLK_REGISTER_ENTRY_SOURCE(i2s4_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0 340 CLK_REGISTER_ENTRY_SOURCE(i2c4_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0 341 CLK_REGISTER_ENTRY_SOURCE(spi5_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_SPI5_0 342 CLK_REGISTER_ENTRY_SOURCE(spi6_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_SPI6_0 343 // 0x3d0 344 CLK_REGISTER_ENTRY_SOURCE(audio_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_AUDIO_0 345 NULL_CLK_REGISTER_ENTRY, // Reserved 346 CLK_REGISTER_ENTRY_SOURCE(dam0_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_DAM0_0 347 CLK_REGISTER_ENTRY_SOURCE(dam1_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_DAM1_0 348 // 0x3e0 349 CLK_REGISTER_ENTRY_SOURCE(dam2_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_DAM2_0 350 CLK_REGISTER_ENTRY_SOURCE(NUM_OTHER_CLOCKS), // TODO CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0 351 CLK_REGISTER_ENTRY_SOURCE(actmon_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0 352 CLK_REGISTER_ENTRY_SOURCE(extperiph1_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0 353 // 0x3f0 354 CLK_REGISTER_ENTRY_SOURCE(extperiph2_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0 355 CLK_REGISTER_ENTRY_SOURCE(extperiph3_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0 356 NULL_CLK_REGISTER_ENTRY, // Reserved 357 CLK_REGISTER_ENTRY_SOURCE(i2c_slow_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0 358 // 0x400 359 CLK_REGISTER_ENTRY_SOURCE(NUM_OTHER_CLOCKS), // TODO CLK_RST_CONTROLLER_CLK_SOURCE_SYS_0 360 NULL_CLK_REGISTER_ENTRY, // Reserved 361 NULL_CLK_REGISTER_ENTRY, // Reserved 362 NULL_CLK_REGISTER_ENTRY, // Reserved 363 // 0x410 364 NULL_CLK_REGISTER_ENTRY, // Reserved 365 CLK_REGISTER_ENTRY_SOURCE(NUM_OTHER_CLOCKS), // TODO CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 366 NULL_CLK_REGISTER_ENTRY, // Reserved 367 NULL_CLK_REGISTER_ENTRY, // Reserved 368 // 0x420 369 CLK_REGISTER_ENTRY_SOURCE(sata_oob_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0 370 CLK_REGISTER_ENTRY_SOURCE(NUM_OTHER_CLOCKS), // TODO CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0 371 CLK_REGISTER_ENTRY_SOURCE(hda_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0 372 NULL_CLK_REGISTER_ENTRY, // Reserved 373 // 0x430 374 CLK_REGISTER_ENTRY_ENBRST(REG_V, RST_SET), // CLK_RST_CONTROLLER_RST_DEV_V_SET_0 375 CLK_REGISTER_ENTRY_ENBRST(REG_V, RST_CLR), // CLK_RST_CONTROLLER_RST_DEV_V_CLR_0 376 CLK_REGISTER_ENTRY_ENBRST(REG_W, RST_SET), // CLK_RST_CONTROLLER_RST_DEV_W_SET_0 377 CLK_REGISTER_ENTRY_ENBRST(REG_W, RST_CLR), // CLK_RST_CONTROLLER_RST_DEV_W_CLR_0 378 // 0x440 379 CLK_REGISTER_ENTRY_ENBRST(REG_V, ENB_SET), // CLK_RST_CONTROLLER_CLK_ENB_V_SET_0 380 CLK_REGISTER_ENTRY_ENBRST(REG_V, ENB_CLR), // CLK_RST_CONTROLLER_CLK_ENB_V_CLR_0 381 CLK_REGISTER_ENTRY_ENBRST(REG_W, ENB_SET), // CLK_RST_CONTROLLER_CLK_ENB_W_SET_0 382 CLK_REGISTER_ENTRY_ENBRST(REG_W, ENB_CLR), // CLK_RST_CONTROLLER_CLK_ENB_W_CLR_0 383 // 0x450 384 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET_0 385 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR_0 386 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_RST_CPULP_CMPLX_SET_0 387 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_RST_CPULP_CMPLX_CLR_0 388 // 0x460 389 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CLK_CPUG_CMPLX_SET_0 390 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CLK_CPUG_CMPLX_CLR_0 391 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CLK_CPULP_CMPLX_SET_0 392 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CLK_CPULP_CMPLX_CLR_0 393 // 0x470 394 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CPU_CMPLX_STATUS_0 395 NULL_CLK_REGISTER_ENTRY, // Reserved 396 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_INTSTATUS_0 397 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_INTMASK_0 398 // 0x480 399 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0 400 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 401 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 402 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLE_AUX_0 403 // 0x490 404 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_SATA_PLL_CFG0_0 405 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_SATA_PLL_CFG1_0 406 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_PCIE_PLL_CFG_0 407 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0 408 // 0x4a0 409 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S0_0 410 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0 411 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0 412 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0 413 // 0x4b0 414 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0 415 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0 416 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLD2_BASE_0 417 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLD2_MISC_0 418 // 0x4c0 419 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0 420 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLREFE_BASE_0 421 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLREFE_MISC_0 422 NULL_CLK_REGISTER_ENTRY, // Reserved 423 // 0x4d0 424 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CPU_FINETRIM_BYP_0 425 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CPU_FINETRIM_SELECT_0 426 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CPU_FINETRIM_DR_0 427 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CPU_FINETRIM_DF_0 428 // 0x4e0 429 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CPU_FINETRIM_F_0 430 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CPU_FINETRIM_R_0 431 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLC2_BASE_0 432 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLC2_MISC_0_0 433 // 0x4f0 434 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLC2_MISC_1_0 435 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLC2_MISC_2_0 436 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLC2_MISC_3_0 437 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLC3_BASE_0 438 // 0x500 439 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLC3_MISC_0_0 440 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLC3_MISC_1_0 441 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLC3_MISC_2_0 442 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLC3_MISC_3_0 443 // 0x510 444 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLX_MISC_1_0 445 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLX_MISC_2_0 446 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLX_MISC_3_0 447 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0 448 // 0x520 449 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0 450 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLE_AUX1_0 451 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLP_RESHIFT_0 452 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0 453 // 0x530 454 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_0 455 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0 456 NULL_CLK_REGISTER_ENTRY, // Reserved 457 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CLK_CPU_MISC_0 458 // 0x540 459 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CLK_CPUG_MISC_0 460 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CLK_CPULP_MISC_0 461 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLX_HW_CTRL_CFG_0 462 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLX_SW_RAMP_CFG_0 463 // 0x550 464 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLX_HW_CTRL_STATUS_0 465 NULL_CLK_REGISTER_ENTRY, // Reserved 466 NULL_CLK_REGISTER_ENTRY, // Reserved 467 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_SPARE_REG0_0 468 // 0x560 469 NULL_CLK_REGISTER_ENTRY, // Reserved 470 NULL_CLK_REGISTER_ENTRY, // Reserved 471 NULL_CLK_REGISTER_ENTRY, // Reserved 472 NULL_CLK_REGISTER_ENTRY, // Reserved 473 // 0x570 474 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLD2_SS_CFG_0 475 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0 476 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0 477 NULL_CLK_REGISTER_ENTRY, // Reserved 478 // 0x580 479 NULL_CLK_REGISTER_ENTRY, // Reserved 480 NULL_CLK_REGISTER_ENTRY, // Reserved 481 NULL_CLK_REGISTER_ENTRY, // Reserved 482 NULL_CLK_REGISTER_ENTRY, // Reserved 483 // 0x590 484 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLDP_BASE_0 485 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLDP_MISC_0 486 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLDP_SS_CFG_0 487 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0 488 // 0x5a0 489 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0 490 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLC4_BASE_0 491 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLC4_MISC_0 492 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLC4_SS_CFG_0 493 // 0x5b0 494 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0 495 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0 496 NULL_CLK_REGISTER_ENTRY, // Reserved 497 NULL_CLK_REGISTER_ENTRY, // Reserved 498 // 0x5c0 499 NULL_CLK_REGISTER_ENTRY, // Reserved 500 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CLK_SPARE0_0 501 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_CLK_SPARE1_0 502 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0 503 // 0x5d0 504 NULL_CLK_REGISTER_ENTRY, // Reserved 505 NULL_CLK_REGISTER_ENTRY, // Reserved 506 NULL_CLK_REGISTER_ENTRY, // Reserved 507 NULL_CLK_REGISTER_ENTRY, // Reserved 508 // 0x5e0 509 NULL_CLK_REGISTER_ENTRY, // Reserved 510 NULL_CLK_REGISTER_ENTRY, // Reserved 511 NULL_CLK_REGISTER_ENTRY, // Reserved 512 NULL_CLK_REGISTER_ENTRY, // Reserved 513 // 0x5f0 514 NULL_CLK_REGISTER_ENTRY, // Reserved 515 NULL_CLK_REGISTER_ENTRY, // Reserved 516 NULL_CLK_REGISTER_ENTRY, // Reserved 517 NULL_CLK_REGISTER_ENTRY, // Reserved 518 // 0x600 519 CLK_REGISTER_ENTRY_SOURCE(xusb_core_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0 520 CLK_REGISTER_ENTRY_SOURCE(xusb_falcon_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0 521 CLK_REGISTER_ENTRY_SOURCE(xusb_fs_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0 522 CLK_REGISTER_ENTRY_SOURCE(xusb_core_dev_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0 523 // 0x610 524 CLK_REGISTER_ENTRY_SOURCE(NUM_OTHER_CLOCKS), // TODO CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0 525 CLK_REGISTER_ENTRY_SOURCE(cilab_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_CILAB_0 526 CLK_REGISTER_ENTRY_SOURCE(cilcd_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_CILCD_0 527 CLK_REGISTER_ENTRY_SOURCE(cile_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_CILE_0 528 // 0x620 529 CLK_REGISTER_ENTRY_SOURCE(dsia_lp_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0 530 CLK_REGISTER_ENTRY_SOURCE(dsib_lp_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0 531 CLK_REGISTER_ENTRY_SOURCE(entropy_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0 532 CLK_REGISTER_ENTRY_SOURCE(dvfs_ref_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0 533 // 0x630 534 CLK_REGISTER_ENTRY_SOURCE(dvfs_soc_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_SOC_0 535 CLK_REGISTER_ENTRY_SOURCE(traceclkin_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_TRACECLKIN_0 536 CLK_REGISTER_ENTRY_SOURCE(adx0_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_ADX0_0 537 CLK_REGISTER_ENTRY_SOURCE(amx0_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_AMX0_0 538 // 0x640 539 CLK_REGISTER_ENTRY_SOURCE(emc_latency_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0 540 CLK_REGISTER_ENTRY_SOURCE(soc_therm_t), // CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0 541 NULL_CLK_REGISTER_ENTRY, // Reserved 542 NULL_CLK_REGISTER_ENTRY, // Reserved 543 // 0x650 544 NULL_CLK_REGISTER_ENTRY, // Reserved 545 NULL_CLK_REGISTER_ENTRY, // Reserved 546 CLK_REGISTER_ENTRY_SOURCE(vi_sensor2_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR2_0 547 CLK_REGISTER_ENTRY_SOURCE(i2c6_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0 548 // 0x660 549 NULL_CLK_REGISTER_ENTRY, // Reserved 550 CLK_REGISTER_ENTRY_SOURCE(emc_dll_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0 551 CLK_REGISTER_ENTRY_SOURCE(hdmi_audio_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_AUDIO_0 552 CLK_REGISTER_ENTRY_SOURCE(clk72mhz_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_CLK72MHZ_0 553 // 0x670 554 CLK_REGISTER_ENTRY_SOURCE(adx1_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_ADX1_0 555 CLK_REGISTER_ENTRY_SOURCE(amx1_r_clk), // CLK_RST_CONTROLLER_CLK_SOURCE_AMX1_0 556 CLK_REGISTER_ENTRY_SOURCE(vic_clk_t), // CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0 557 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLP_OUTC_0 558 // 0x680 559 CLK_REGISTER_ENTRY(CLK_PLL), // CLK_RST_CONTROLLER_PLLP_MISC1_0 560 NULL_CLK_REGISTER_ENTRY, // Reserved 561 NULL_CLK_REGISTER_ENTRY, // Reserved 562 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0 563 // 0x690 564 CLK_REGISTER_ENTRY(CLK_MISC), // CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0 565}; 566 567static clk_t * 568tk1_car_get_clock(clock_sys_t *cs, enum clk_id id) 569{ 570 assert(cs != NULL); 571 return NULL; 572} 573 574static int 575tk1_car_gate_enable(clock_sys_t* clock_sys, 576 enum clock_gate gate, enum clock_gate_mode mode) 577{ 578 /* The TK1 CAR controller only supports enabling and disabling the clock 579 * signal to a device: there are no idle/sleep clock modes, so we ignore 580 * CLKGATE_IDLE and CLKGATE_SLEEP. 581 */ 582 if (clock_sys == NULL) { 583 ZF_LOGE("Invalid driver instance handle!"); 584 return -EINVAL; 585 } 586 if (mode != CLKGATE_ON && mode != CLKGATE_OFF) { 587 ZF_LOGE("Invalid clock gate mode %d!", mode); 588 return -EINVAL; 589 } 590 591 return 0; 592} 593 594int 595tegra_car_init(void *regs_vaddr, clock_sys_t *cs) 596{ 597 if (regs_vaddr == NULL) { 598 ZF_LOGE("MMIO vaddr for CAR regs cannot be NULL!"); 599 return -EINVAL; 600 } 601 602 cs->priv = regs_vaddr; 603 604 cs->gate_enable = &tk1_car_gate_enable; 605 cs->get_clock = &tk1_car_get_clock; 606 return 0; 607} 608 609int 610clock_sys_init(ps_io_ops_t* o, clock_sys_t* clock_sys) 611{ 612 void *car_vaddr = NULL; 613 614 if (o == NULL || clock_sys == NULL) { 615 ZF_LOGE("Invalid io_ops or driver instance handle!"); 616 return -EINVAL; 617 } 618 619 MAP_IF_NULL(o, TK1_CLKCAR, car_vaddr); 620 if (car_vaddr == NULL) { 621 ZF_LOGE("Failed to map TK1 CAR registers into vmem."); 622 return -1; 623 } 624 625 return tegra_car_init(car_vaddr, clock_sys); 626} 627