1/*
2 * Copyright 2017, Data61
3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
4 * ABN 41 687 119 230.
5 *
6 * This software may be distributed and modified according to the terms of
7 * the BSD 2-Clause license. Note that NO WARRANTY is provided.
8 * See "LICENSE_BSD2.txt" for details.
9 *
10 * @TAG(DATA61_BSD)
11 */
12#include <platsupport/src.h>
13
14#define SRC_PADDR           0x20D8000
15#define SRC_SIZE            0x1000
16
17struct src_regs {
18    uint32_t scr;   /* 0x000 32 R/W 00000521h */
19    uint32_t sbmr1; /* 0x004 32  R  00000000h */
20    uint32_t srsr;  /* 0x008 32 R/W 00000001h */
21    uint32_t res1[2];
22    uint32_t sisr;  /* 0x014 32  R  00000000h */
23    uint32_t simr;  /* 0x018 32 R/W 0000001Fh */
24    uint32_t sbmr2; /* 0x01C 32  R  00000000h */
25    uint32_t gpr1;  /* 0x020 32 R/W 00000000h */
26    uint32_t gpr2;  /* 0x024 32 R/W 00000000h */
27    uint32_t gpr3;  /* 0x028 32 R/W 00000000h */
28    uint32_t gpr4;  /* 0x02C 32 R/W 00000000h */
29    uint32_t gpr5;  /* 0x030 32 R/W 00000000h */
30    uint32_t gpr6;  /* 0x034 32 R/W 00000000h */
31    uint32_t gpr7;  /* 0x038 32 R/W 00000000h */
32    uint32_t gpr8;  /* 0x03C 32 R/W 00000000h */
33    uint32_t gpr9;  /* 0x040 32 R/W 00000000h */
34    uint32_t gpr10; /* 0x044 32 R/W 00000000h */
35};
36typedef volatile struct src_regs src_regs_t;
37
38static src_regs_t* src_regs;
39
40static inline void
41src_set_regs(src_dev_t* d, src_regs_t* r)
42{
43    d->priv = (void*)r;
44}
45
46static inline src_regs_t*
47src_get_regs(src_dev_t* d)
48{
49    return (src_regs_t*)d->priv;
50}
51
52void
53reset_controller_assert_reset(src_dev_t* dev, enum src_rst_id id)
54{
55    src_regs_t* regs;
56    int reset_bit;
57    static const int reset_map[] = {
58        [SRCRST_CORE3]      = 16, [SRCRST_CORE2]   = 15,
59        [SRCRST_CORE1]      = 14, [SRCRST_CORE0]   = 13,
60        [SRCRST_SW_IPU2]    = 12, [SRCRST_EIM]     = 11,
61        [SRCRST_SW_OPEN_VG] =  4, [SRCRST_SW_IPU1] =  3,
62        [SRCRST_SW_VPU]     =  2, [SRCRST_SW_GPU]  =  1
63    };
64    if (id >= 0 && id < ARRAY_SIZE(reset_map)) {
65        reset_bit = reset_map[id];
66        regs = src_get_regs(dev);
67        /* Reset the subsystem */
68        regs->scr |= BIT(reset_bit);
69        while (regs->scr & BIT(reset_bit));
70    }
71}
72
73int
74reset_controller_init(enum src_id id, ps_io_ops_t* ops, src_dev_t* dev)
75{
76    assert(sizeof(struct src_regs) == 0x48);
77    if (id < 0 || id >= NSRC) {
78        return -1;
79    }
80
81    src_regs = ps_io_map(&ops->io_mapper, SRC_PADDR, SRC_SIZE, 0, PS_MEM_NORMAL);
82    if (src_regs == NULL) {
83        return -1;
84    }
85    src_set_regs(dev, src_regs);
86
87    return 0;
88}
89