1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 8 * See "LICENSE_BSD2.txt" for details. 9 * 10 * @TAG(DATA61_BSD) 11 */ 12 13#pragma once 14 15enum clk_id { 16 CLK_MASTER, /* The input clock PS_CLK */ 17 /* PLLs */ 18 CLK_ARM_PLL, 19 CLK_DDR_PLL, 20 CLK_IO_PLL, 21 /* CPU Clocks */ 22 CLK_CPU_6OR4X, 23 CLK_CPU_3OR2X, 24 CLK_CPU_2X, 25 CLK_CPU_1X, 26 /* DDR Clocks */ 27 CLK_DDR_2X, 28 CLK_DDR_3X, 29 /* ----- */ 30 CLK_DCI, 31 /* I/O Peripheral Clocks */ 32 CLK_GEM0, 33 CLK_GEM1, 34 CLK_SDIO0, 35 CLK_SDIO1, 36 CLK_SPI0, 37 CLK_SPI1, 38 CLK_CAN0, 39 CLK_CAN1, 40 CLK_UART0, 41 CLK_UART1, 42 CLK_LQSPI, 43 CLK_SMC, 44 /* FPGA Programmable Logic Clocks */ 45 CLK_FPGA_PL0, 46 CLK_FPGA_PL1, 47 CLK_FPGA_PL2, 48 CLK_FPGA_PL3, 49 /* System Debug Clocks */ 50 CLK_DBG, 51 CLK_PCAP, 52 /* ----- */ 53 NCLOCKS, 54 /* Aliases */ 55 PS_CLK = CLK_MASTER, 56}; 57 58enum clock_gate { 59 /* The value represents a clock's control bit in the APER_CLK_CTRL register */ 60 DMAC_CLKGATE = 0, 61 USB0_CLKGATE = 2, 62 USB1_CLKGATE = 3, 63 GEM0_CLKGATE = 6, 64 GEM1_CLKGATE = 7, 65 SDIO0_CLKGATE = 10, 66 SDIO1_CLKGATE = 11, 67 SPI0_CLKGATE = 14, 68 SPI1_CLKGATE = 15, 69 CAN0_CLKGATE = 16, 70 CAN1_CLKGATE = 17, 71 I2C0_CLKGATE = 18, 72 I2C1_CLKGATE = 19, 73 UART0_CLKGATE = 20, 74 UART1_CLKGATE = 21, 75 GPIO_CLKGATE = 22, 76 LQSPI_CLKGATE = 23, 77 SMC_CLKGATE = 24, 78 NCLKGATES 79}; 80 81/** 82 * Select 621 CPU clock ratio 83 * @param[in] cpu_clk One of the CPU clocks 84 * @return 0 on success 85 */ 86int clk_cpu_clk_select_621(clk_t* cpu_clk); 87 88/** 89 * Select 421 CPU clock ratio 90 * @param[in] cpu_clk One of the CPU clocks 91 * @return 0 on success 92 */ 93int clk_cpu_clk_select_421(clk_t* cpu_clk); 94 95