1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 8 * See "LICENSE_BSD2.txt" for details. 9 * 10 * @TAG(DATA61_BSD) 11 */ 12 13#pragma once 14 15/* this is the misc pinmux */ 16#define MUX_PADDR_BASE 0x70000000 17/* the auxiliary pinmux */ 18#define MUX_AUX_PADDR_BASE 0x70006000 19 20#define TK1_MUX_MISC_PADDR (MUX_PADDR_BASE) 21#define TK1_MUX_MISC_SIZE 0x1000 22 23#define TK1_MUX_AUX_PADDR (MUX_AUX_PADDR_BASE) 24#define TK1_MUX_AUX_SIZE 0x1000 25 26#define GMACFG_ADDR_OFFSET 0x0900 27 28typedef struct mux_sys mux_sys_t; 29typedef struct gpio_sys gpio_sys_t; 30typedef struct ps_io_ops ps_io_ops_t; 31 32enum mux_feature { 33 MUX_FEATURE_UARTA, 34 MUX_FEATURE_UARTB, 35 MUX_FEATURE_UARTC, 36 MUX_FEATURE_UARTD, 37 38 MUX_FEATURE_SPI1, 39 MUX_FEATURE_SPI2, 40 MUX_FEATURE_SPI3, 41 MUX_FEATURE_SPI4, 42 43 MUX_FEATURE_GPIO_PS3, 44 MUX_FEATURE_GPIO_PS4, 45 MUX_FEATURE_GPIO_PR0, 46 MUX_FEATURE_GPIO_PR6, 47 48 MUX_FEATURE_GPIO_PS5, 49 MUX_FEATURE_GPIO_PT0, 50 MUX_FEATURE_GPIO_PS6, 51 MUX_FEATURE_GPIO_PS2, 52 53 MUX_FEATURE_GPIO_PA3, 54 55 MUX_FEATURE_I2C0, 56 MUX_FEATURE_I2C1, 57 MUX_FEATURE_I2C2, 58 MUX_FEATURE_I2C3, 59 /* I2C4 and I2C5 don't seem to have recognizable mux pads. */ 60 // MUX_FEATURE_I2C4, 61 // MUX_FEATURE_I2C5, 62 63 MUX_FEATURE_GPIO_PC4, 64 MUX_FEATURE_GPIO_PC5, 65 MUX_FEATURE_GPIO_PBB1, 66 MUX_FEATURE_GPIO_PBB2, 67 68 MUX_FEATURE_PPM_MIRROR, 69 70 NMUX_FEATURES 71}; 72 73/* Please see the TK1 schematic for the signal-to-pad mappings. 74 * Please also see section 8.12 of the TegraK1 TRM for these register offsets. 75 */ 76#define MUX_PAD_INDEX(_reg_off) (_reg_off / 4) 77 78enum mux_pad { 79 MUX_PAD_ULPI_DATA0_PO1, 80 MUX_PAD_ULPI_DATA1_PO2, 81 MUX_PAD_ULPI_DATA2_PO3, 82 MUX_PAD_ULPI_DATA3_PO4, 83 MUX_PAD_ULPI_DATA4_PO5, 84 MUX_PAD_ULPI_DATA5_PO6, 85 MUX_PAD_ULPI_DATA6_PO7, 86 MUX_PAD_ULPI_DATA7_PO0, 87 MUX_PAD_ULPI_CLK_PY0, 88 MUX_PAD_ULPI_DIR_PY1, 89 MUX_PAD_ULPI_NXT_PY2, 90 MUX_PAD_ULPI_STP_PY3, 91 MUX_PAD_DAP3_FS_PP0, 92 MUX_PAD_DAP3_DIN_PP1, 93 MUX_PAD_DAP3_DOUT_PP2, 94 MUX_PAD_DAP3_SCLK_PP3, 95 MUX_PAD_PV0, 96 MUX_PAD_PV1, 97 MUX_PAD_SDMMC1_CLK_PZ0, 98 MUX_PAD_SDMMC1_CMD_PZ1, 99 MUX_PAD_SDMMC1_DAT3_PY4, 100 MUX_PAD_SDMMC1_DAT2_PY5, 101 MUX_PAD_SDMMC1_DAT1_PY6, 102 MUX_PAD_SDMMC1_DAT0_PY7, 103 MUX_PAD_CLK2_OUT_PW5 = (0x68 / 4), 104 MUX_PAD_CLK2_REQ_PCC5, 105 MUX_PAD_HDMI_INT_PN7 = (0x110 / 4), 106 MUX_PAD_DDC_SCL_PV4, 107 MUX_PAD_DDC_SDA_PV5, 108 MUX_PAD_UART2_RXD_PC3 = (0x164 / 4), 109 MUX_PAD_UART2_TXD_PC2, 110 MUX_PAD_UART2_RTS_N_PJ6, 111 MUX_PAD_UART2_CTS_N_PJ5, 112 MUX_PAD_UART3_TXD_PW6, 113 MUX_PAD_UART3_RXD_PW7, 114 MUX_PAD_UART3_CTS_N_PA1, 115 MUX_PAD_UART3_RTS_N_PC0, 116 MUX_PAD_PU0, 117 MUX_PAD_PU1, 118 MUX_PAD_PU2, 119 MUX_PAD_PU3, 120 MUX_PAD_PU4, 121 MUX_PAD_PU5, 122 MUX_PAD_PU6, 123 MUX_PAD_GEN1_I2C_SDA_PC5, 124 MUX_PAD_GEN1_I2C_SCL_PC4, 125 MUX_PAD_DAP4_FS_PP4, 126 MUX_PAD_DAP4_DIN_PP5, 127 MUX_PAD_DAP4_DOUT_PP6, 128 MUX_PAD_DAP4_SCLK_PP7, 129 MUX_PAD_CLK3_OUT_PEE0, 130 MUX_PAD_CLK3_REQ_PEE1, 131 MUX_PAD_PC7, 132 MUX_PAD_PI5, 133 MUX_PAD_PI7, 134 MUX_PAD_PK0, 135 MUX_PAD_PK1, 136 MUX_PAD_PJ0, 137 MUX_PAD_PJ2, 138 MUX_PAD_PK3, 139 MUX_PAD_PK4, 140 MUX_PAD_PK2, 141 MUX_PAD_PI3, 142 MUX_PAD_PI6, 143 MUX_PAD_PG0, 144 MUX_PAD_PG1, 145 MUX_PAD_PG2, 146 MUX_PAD_PG3, 147 MUX_PAD_PG4, 148 MUX_PAD_PG5, 149 MUX_PAD_PG6, 150 MUX_PAD_PG7, 151 MUX_PAD_PH0, 152 MUX_PAD_PH1, 153 MUX_PAD_PH2, 154 MUX_PAD_PH3, 155 MUX_PAD_PH4, 156 MUX_PAD_PH5, 157 MUX_PAD_PH6, 158 MUX_PAD_PH7, 159 MUX_PAD_PJ7, 160 MUX_PAD_PB0, 161 MUX_PAD_PB1, 162 MUX_PAD_PK7, 163 MUX_PAD_PI0, 164 MUX_PAD_PI1, 165 MUX_PAD_PI2, 166 MUX_PAD_PI4, 167 MUX_PAD_GEN2_I2C_SCL_PT5, 168 MUX_PAD_GEN2_I2C_SDA_PT6, 169 MUX_PAD_SDMMC4_CLK_PCC4, 170 MUX_PAD_SDMMC4_CMD_PT7, 171 MUX_PAD_SDMMC4_DAT0_PAA0, 172 MUX_PAD_SDMMC4_DAT1_PAA1, 173 MUX_PAD_SDMMC4_DAT2_PAA2, 174 MUX_PAD_SDMMC4_DAT3_PAA3, 175 MUX_PAD_SDMMC4_DAT4_PAA4, 176 MUX_PAD_SDMMC4_DAT5_PAA5, 177 MUX_PAD_SDMMC4_DAT6_PAA6, 178 MUX_PAD_SDMMC4_DAT7_PAA7, 179 MUX_PAD_CAM_MCLK_PCC0 = (0x284 / 4), 180 MUX_PAD_PCC1, 181 MUX_PAD_PBB0, 182 MUX_PAD_CAM_I2C_SCL_PBB1, 183 MUX_PAD_CAM_I2C_SDA_PBB2, 184 MUX_PAD_PBB3, 185 MUX_PAD_PBB4, 186 MUX_PAD_PBB5, 187 MUX_PAD_PBB6, 188 MUX_PAD_PBB7, 189 MUX_PAD_PCC2, 190 MUX_PAD_JTAG_RTCK, 191 MUX_PAD_PWR_I2C_SCL_PZ6, 192 MUX_PAD_PWR_I2C_SDA_PZ7, 193 MUX_PAD_KB_ROW0_PR0, 194 MUX_PAD_KB_ROW1_PR1, 195 MUX_PAD_KB_ROW2_PR2, 196 MUX_PAD_KB_ROW3_PR3, 197 MUX_PAD_KB_ROW4_PR4, 198 MUX_PAD_KB_ROW5_PR5, 199 MUX_PAD_KB_ROW6_PR6, 200 MUX_PAD_KB_ROW7_PR7, 201 MUX_PAD_KB_ROW8_PS0, 202 MUX_PAD_KB_ROW9_PS1, 203 MUX_PAD_KB_ROW10_PS2, 204 MUX_PAD_KB_ROW11_PS3, 205 MUX_PAD_KB_ROW12_PS4, 206 MUX_PAD_KB_ROW13_PS5, 207 MUX_PAD_KB_ROW14_PS6, 208 MUX_PAD_KB_ROW15_PS7, 209 MUX_PAD_KB_COL0_PQ0, 210 MUX_PAD_KB_COL1_PQ1, 211 MUX_PAD_KB_COL2_PQ2, 212 MUX_PAD_KB_COL3_PQ3, 213 MUX_PAD_KB_COL4_PQ4, 214 MUX_PAD_KB_COL5_PQ5, 215 MUX_PAD_KB_COL6_PQ6, 216 MUX_PAD_KB_COL7_PQ7, 217 MUX_PAD_CLK_32K_OUT_PA0, 218 MUX_PAD_CORE_PWR_REQ = (0x324 / 4), 219 MUX_PAD_CPU_PWR_REQ, 220 MUX_PAD_PWR_INT_N, 221 MUX_PAD_CLK_32K_IN, 222 MUX_PAD_OWR, 223 MUX_PAD_DAP1_FS_PN0, 224 MUX_PAD_DAP1_DIN_PN1, 225 MUX_PAD_DAP1_DOUT_PN2, 226 MUX_PAD_DAP1_SCLK_PN3, 227 MUX_PAD_DAP_MCLK1_REQ_PEE2, 228 MUX_PAD_DAP_MCLK1_PW4, 229 MUX_PAD_SPDIF_IN_PK6, 230 MUX_PAD_SPDIF_OUT_PK5, 231 MUX_PAD_DAP2_FS_PA2, 232 MUX_PAD_DAP2_DIN_PA4, 233 MUX_PAD_DAP2_DOUT_PA5, 234 MUX_PAD_DAP2_SCLK_PA3, 235 MUX_PAD_DVFS_PWM_PX0, 236 MUX_PAD_GPIO_X1_AUD_PX1, 237 MUX_PAD_GPIO_X3_AUD_PX3, 238 MUX_PAD_DVFS_CLK_PX2, 239 MUX_PAD_GPIO_X4_AUD_PX4, 240 MUX_PAD_GPIO_X5_AUD_PX5, 241 MUX_PAD_GPIO_X6_AUD_PX6, 242 MUX_PAD_GPIO_X7_AUD_PX7, 243 MUX_PAD_SDMMC3_CLK_PA6 = (0x390 / 4), 244 MUX_PAD_SDMMC3_CMD_PA7, 245 MUX_PAD_SDMMC3_DAT0_PB7, 246 MUX_PAD_SDMMC3_DAT1_PB6, 247 MUX_PAD_SDMMC3_DAT2_PB5, 248 MUX_PAD_SDMMC3_DAT3_PB4, 249 MUX_PAD_PEX_L0_RST_N_PDD1 = (0x3bc / 4), 250 MUX_PAD_PEX_L0_CLKREQ_N_PDD2, 251 MUX_PAD_PEX_WAKE_N_PDD3, 252 MUX_PAD_PEX_L1_RST_N_PDD5 = (0x3cc / 4), 253 MUX_PAD_PEX_L1_CLKREQ_N_PDD6, 254 MUX_PAD_HDMI_CEC_PEE3 = (0x3e0 / 4), 255 MUX_PAD_SDMMC1_WP_N_PV3, 256 MUX_PAD_SDMMC3_CD_N_PV2, 257 MUX_PAD_GPIO_W2_AUD_PW2, 258 MUX_PAD_GPIO_W3_AUD_PW3, 259 MUX_PAD_USB_VBUS_EN0_PN4, 260 MUX_PAD_USB_VBUS_EN1_PN5, 261 MUX_PAD_SDMMC3_CLK_LB_IN_PEE5, 262 MUX_PAD_SDMMC3_CLK_LB_OUT_PEE4, 263 MUX_PAD_GMI_CLK_LB, 264 MUX_PAD_RESET_OUT_N, 265 MUX_PAD_KB_ROW16_PT0, 266 MUX_PAD_KB_ROW17_PT1, 267 MUX_PAD_USB_VBUS_EN2_PFF1, 268 MUX_PAD_PFF2, 269 MUX_PAD_DP_HPD_PFF0 = (0x430 / 4), 270 271 NMUX_PADS 272}; 273 274int tegra_mux_init(volatile void *pinmux_misc, volatile void *pinmux_aux, 275 ps_io_ops_t *io_ops, 276 gpio_sys_t *gpio_sys, mux_sys_t *self); 277