1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 8 * See "LICENSE_BSD2.txt" for details. 9 * 10 * @TAG(DATA61_BSD) 11 */ 12 13#pragma once 14 15/* Register information sourced from "NVIDIA Tegra K1 Mobile Processor TECHNICAL REFERENCE MANUAL" */ 16 17#define CLK_ENB_CPU 0 18/* 1 */ 19/* 2 */ 20#define CLK_ENB_ISPB 3 21#define CLK_ENB_RTC 4 /* Enabled on reset */ 22#define CLK_ENB_TMR 5 /* Enabled on reset */ 23#define CLK_ENB_UARTA 6 24#define CLK_ENB_UARTB 7 /*UARTB/VFIR*/ 25#define CLK_ENB_GPIO 8 /* Enabled on reset */ 26#define CLK_ENB_SDMMC2 9 27#define CLK_ENB_SPDIF 10 28#define CLK_ENB_I2S1 11 29#define CLK_ENB_I2C1 12 30/* 13 */ 31#define CLK_ENB_SDMMC1 14 32#define CLK_ENB_SDMMC4 15 33/* 16 */ 34#define CLK_ENB_PWM 17 35#define CLK_ENB_I2S2 18 36/* 19 */ 37#define CLK_ENB_VI 20 38/* 21 */ 39#define CLK_ENB_USBD 22 40#define CLK_ENB_ISP 23 41/* 24 */ 42/* 25 */ 43#define CLK_ENB_DISP2 26 44#define CLK_ENB_DISP1 27 45#define CLK_ENB_HOST1X 28 46#define CLK_ENB_VCP 29 47#define CLK_ENB_I2S0 30 48#define CLK_ENB_CACHE2 31 /* Enabled on reset */ 49 50#define CLK_ENB_MEM 32 51#define CLK_ENB_AHBDMA 33 52#define CLK_ENB_APBDMA 34 53/* 35 */ 54#define CLK_ENB_KBC 36 55#define CLK_ENB_STAT_MON 37 56#define CLK_ENB_PMC 38 57#define CLK_ENB_FUSE 39 /* Enabled on reset */ 58#define CLK_ENB_KFUSE 40 59#define CLK_ENB_SPI1 41 60#define CLK_ENB_SNOR 42 /* Enabled on reset */ 61#define CLK_ENB_JTAG2TBC 43 /* Enabled on reset */ 62#define CLK_ENB_SPI2 44 63/* 45 */ 64#define CLK_ENB_SPI3 46 65#define CLK_ENB_I2C5 47 66#define CLK_ENB_DSI 48 67/* 49 */ 68#define CLK_ENB_HSI 50 69#define CLK_ENB_HDMI 51 70#define CLK_ENB_CSI 52 71/* 53 */ 72#define CLK_ENB_I2C2 54 73#define CLK_ENB_UARTC 55 74#define CLK_ENB_MIPI_CAL 56 75#define CLK_ENB_EMC 57 76#define CLK_ENB_USB2 58 77#define CLK_ENB_USB3 59 78/* 60 */ 79#define CLK_ENB_VDE 61 80#define CLK_ENB_BSEA 62 81#define CLK_ENB_BSEV 63 82 83/* 64 */ 84#define CLK_ENB_UARTD 65 85/* 66 */ 86#define CLK_ENB_I2C3 67 87#define CLK_ENB_SPI4 68 88#define CLK_ENB_SDMMC3 69 89#define CLK_ENB_PCIE 70 90#define CLK_ENB_OWR 71 91#define CLK_ENB_AFI 72 92#define CLK_ENB_CSITE 73 /* Enabled on reset */ 93/* 74 */ 94#define CLK_ENB_AVPUCQ 75 /* Enabled on reset */ 95//#define CLK_ENB_LA 76 96#define CLK_ENB_TRACECLKIN 77 /* Enabled on reset */ 97#define CLK_ENB_SOC_THERM 78 98#define CLK_ENB_DTV 79 99/* 80 */ 100#define CLK_ENB_I2C_SLOW 81 101#define CLK_ENB_DSIB 82 102#define CLK_ENB_TSEC 83 103#define CLK_ENB_IRAMA 84 /* Enabled on reset */ 104#define CLK_ENB_IRAMB 85 /* Enabled on reset */ 105#define CLK_ENB_IRAMC 86 /* Enabled on reset */ 106#define CLK_ENB_IRAMD 87 /* Enabled on reset */ 107#define CLK_ENB_CRAM2 88 /* Enabled on reset */ 108#define CLK_ENB_XUSB_HOST 89 109#define CLK_M_DOUBLER_ENB 90 /* Enabled on reset */ 110#define CLK_ENB_MSENC 91 111#define CLK_ENB_SUS_OUT 92 112#define CLK_ENB_DEV2_OUT 93 113#define CLK_ENB_DEV1_OUT 94 114#define CLK_ENB_XUSB_DEV 95 115 116#define CLK_ENB_CPUG 96 117#define CLK_ENB_CPULP 97 118/* 98 */ 119#define CLK_ENB_MSELECT 99 120#define CLK_ENB_TSENSOR 100 121#define CLK_ENB_I2S3 101 122#define CLK_ENB_I2S4 102 123#define CLK_ENB_I2C4 103 124#define CLK_ENB_SPI5 104 125#define CLK_ENB_SPI6 105 126#define CLK_ENB_AUDIO 106 127#define CLK_ENB_APBIF 107 128#define CLK_ENB_DAM0 108 129#define CLK_ENB_DAM1 109 130#define CLK_ENB_DAM2 110 131#define CLK_ENB_HDA2CODEC_2X 111 132#define CLK_ENB_ATOMICS 112 133// #define CLK_ENB_AUDIO0_2X 113 Not in manual? 134// #define CLK_ENB_AUDIO1_2X 114 135// #define CLK_ENB_AUDIO2_2X 115 136// #define CLK_ENB_AUDIO3_2X 116 137// #define CLK_ENB_AUDIO4_2X 117 138#define CLK_ENB_SPDIF_DOUBLER 118 /* Enabled on reset */ 139#define CLK_ENB_ACTMON 119 140#define CLK_ENB_EXTPERIPH1 120 141#define CLK_ENB_EXTPERIPH2 121 142#define CLK_ENB_EXTPERIPH3 122 143#define CLK_ENB_SATA_OOB 123 144#define CLK_ENB_SATA 124 145#define CLK_ENB_HDA 125 146/* 126 */ 147// #define CLK_ENB_SE 127 Not in manual? 148 149#define CLK_ENB_HDA2HDMICODEC 128 150#define CLK_ENB_RESERVED0 129 151#define CLK_ENB_PCIERX0 130 /* Enabled on reset, CLK_ENB_PCIE is master */ 152#define CLK_ENB_PCIERX1 131 /* Enabled on reset, CLK_ENB_PCIE is master */ 153#define CLK_ENB_PCIERX2 132 /* Enabled on reset, CLK_ENB_PCIE is master */ 154#define CLK_ENB_PCIERX3 133 /* Enabled on reset, CLK_ENB_PCIE is master */ 155#define CLK_ENB_PCIERX4 134 /* Enabled on reset, CLK_ENB_PCIE is master */ 156#define CLK_ENB_PCIERX5 135 /* Enabled on reset, CLK_ENB_PCIE is master */ 157#define CLK_ENB_CEC 136 158#define CLK_ENB_PCIE2_IOBIST 137 159#define CLK_ENB_EMC_IOBIST 138 160#define CLK_ENB_HDMI_IOBIST 139 161#define CLK_ENB_SATA_IOBIST 140 162#define CLK_ENB_MIPI_IOBIST 141 163/* 142 */ 164#define CLK_ENB_XUSB 143 165#define CLK_ENB_CILAB 144 166#define CLK_ENB_CILCD 145 167#define CLK_ENB_CILE 146 168#define CLK_ENB_DSIA_LP 147 169#define CLK_ENB_DSIB_LP 148 170#define CLK_ENB_ENTROPY 149 /* Enabled on reset */ 171// #define CLK_ENB_DDS 150 Not in manual? 172/* 151 */ 173// #define CLK_ENB_DP2 152 Not in manual? 174#define CLK_ENB_AMX0 153 175#define CLK_ENB_ADX0 154 176#define CLK_ENB_DVFS 155 177#define CLK_ENB_XUSB_SS 156 178#define CLK_ENB_EMC_LATENCY 157 179/* 158 */ 180/* 159 */ 181 182#define CLK_ENB_SPARE 160 183/* 161 */ 184/* 162 */ 185/* 163 */ 186#define CLK_ENB_CAM_MCLK 164 187#define CLK_ENB_CAM_MCLK2 165 188#define CLK_ENB_I2C6 166 189/* 167 */ 190/* 168 */ 191/* 169 */ 192/* 170 */ 193#define CLK_ENB_VIM2_CLK 171 194/* 172 */ 195/* 173 */ 196#define CLK_ENB_EMC_DLL 174 197/* 175 */ 198#define CLK_ENB_HDMI_AUDIO 176 199#define CLK_ENB_CLK72MHZ 177 200#define CLK_ENB_VIC 178 201/* 179 */ 202#define CLK_ENB_ADX1 180 203#define CLK_ENB_DPAUX 181 204#define CLK_ENB_SOR0 182 205/* 183 */ 206#define CLK_ENB_GPU 184 207#define CLK_ENB_AMX1 185 208/* 186 */ 209/* 187 */ 210/* 188 */ 211/* 189 */ 212/* 190 */ 213/* 191 */ 214 215/* These are passed as arguments to clk_gate_enable(). */ 216enum clock_gate { 217 CLK_GATE_CPU, 218 CLK_GATE_ISPB, 219 CLK_GATE_RTC, /* Enabled on reset */ 220 CLK_GATE_TMR, /* Enabled on reset */ 221 CLK_GATE_UARTA, 222 CLK_GATE_UARTB, /*UARTB/VFIR*/ 223 CLK_GATE_GPIO, /* Enabled on reset */ 224 CLK_GATE_SDMMC2, 225 CLK_GATE_SPDIF, 226 CLK_GATE_I2S1, 227 CLK_GATE_I2C1, 228 CLK_GATE_SDMMC1, 229 CLK_GATE_SDMMC4, 230 CLK_GATE_PWM, 231 CLK_GATE_I2S2, 232 CLK_GATE_VI, 233 CLK_GATE_USBD, 234 CLK_GATE_ISP, 235 CLK_GATE_DISP2, 236 CLK_GATE_DISP1, 237 CLK_GATE_HOST1X, 238 CLK_GATE_VCP, 239 CLK_GATE_I2S0, 240 CLK_GATE_CACHE2, /* Enabled on reset */ 241 CLK_GATE_MEM, 242 CLK_GATE_AHBDMA, 243 CLK_GATE_APBDMA, 244 CLK_GATE_KBC, 245 CLK_GATE_STAT_MON, 246 CLK_GATE_PMC, 247 CLK_GATE_FUSE, /* Enabled on reset */ 248 CLK_GATE_KFUSE, 249 CLK_GATE_SPI1, 250 CLK_GATE_SNOR, /* Enabled on reset */ 251 CLK_GATE_JTAG2TBC, /* Enabled on reset */ 252 CLK_GATE_SPI2, 253 CLK_GATE_SPI3, 254 CLK_GATE_I2C5, 255 CLK_GATE_DSI, 256 CLK_GATE_HSI, 257 CLK_GATE_HDMI, 258 CLK_GATE_CSI, 259 CLK_GATE_I2C2, 260 CLK_GATE_UARTC, 261 CLK_GATE_MIPI_CAL, 262 CLK_GATE_EMC, 263 CLK_GATE_USB2, 264 CLK_GATE_USB3, 265 CLK_GATE_VDE, 266 CLK_GATE_BSEA, 267 CLK_GATE_BSEV, 268 CLK_GATE_UARTD, 269 CLK_GATE_I2C3, 270 CLK_GATE_SPI4, 271 CLK_GATE_SDMMC3, 272 CLK_GATE_PCIE, 273 CLK_GATE_OWR, 274 CLK_GATE_AFI, 275 CLK_GATE_CSITE, /* Enabled on reset */ 276 CLK_GATE_AVPUCQ, /* Enabled on reset */ 277 CLK_GATE_TRACECLKIN, /* Enabled on reset */ 278 CLK_GATE_SOC_THERM, 279 CLK_GATE_DTV, 280 CLK_GATE_I2C_SLOW, 281 CLK_GATE_DSIB, 282 CLK_GATE_TSEC, 283 CLK_GATE_IRAMA, /* Enabled on reset */ 284 CLK_GATE_IRAMB, /* Enabled on reset */ 285 CLK_GATE_IRAMC, /* Enabled on reset */ 286 CLK_GATE_IRAMD, /* Enabled on reset */ 287 CLK_GATE_CRAM2, /* Enabled on reset */ 288 CLK_GATE_XUSB_HOST, 289 CLK_GATE_M_DOUBLER_ENB, /* Enabled on reset */ 290 CLK_GATE_MSENC, 291 CLK_GATE_SUS_OUT, 292 CLK_GATE_DEV2_OUT, 293 CLK_GATE_DEV1_OUT, 294 CLK_GATE_XUSB_DEV, 295 CLK_GATE_CPUG, 296 CLK_GATE_CPULP, 297 CLK_GATE_MSELECT, 298 CLK_GATE_TSENSOR, 299 CLK_GATE_I2S3, 300 CLK_GATE_I2S4, 301 CLK_GATE_I2C4, 302 CLK_GATE_SPI5, 303 CLK_GATE_SPI6, 304 CLK_GATE_AUDIO, 305 CLK_GATE_APBIF, 306 CLK_GATE_DAM0, 307 CLK_GATE_DAM1, 308 CLK_GATE_DAM2, 309 CLK_GATE_HDA2CODEC_2X, 310 CLK_GATE_ATOMICS, 311 CLK_GATE_SPDIF_DOUBLER, /* Enabled on reset */ 312 CLK_GATE_ACTMON, 313 CLK_GATE_EXTPERIPH1, 314 CLK_GATE_EXTPERIPH2, 315 CLK_GATE_EXTPERIPH3, 316 CLK_GATE_SATA_OOB, 317 CLK_GATE_SATA, 318 CLK_GATE_HDA, 319 CLK_GATE_HDA2HDMICODEC, 320 CLK_GATE_RESERVED0, 321 CLK_GATE_PCIERX0, /* Enabled on reset, CLK_GATE_PCIE is master */ 322 CLK_GATE_PCIERX1, /* Enabled on reset, CLK_GATE_PCIE is master */ 323 CLK_GATE_PCIERX2, /* Enabled on reset, CLK_GATE_PCIE is master */ 324 CLK_GATE_PCIERX3, /* Enabled on reset, CLK_GATE_PCIE is master */ 325 CLK_GATE_PCIERX4, /* Enabled on reset, CLK_GATE_PCIE is master */ 326 CLK_GATE_PCIERX5, /* Enabled on reset, CLK_GATE_PCIE is master */ 327 CLK_GATE_CEC, 328 CLK_GATE_PCIE2_IOBIST, 329 CLK_GATE_EMC_IOBIST, 330 CLK_GATE_HDMI_IOBIST, 331 CLK_GATE_SATA_IOBIST, 332 CLK_GATE_MIPI_IOBIST, 333 CLK_GATE_XUSB, 334 CLK_GATE_CILAB, 335 CLK_GATE_CILCD, 336 CLK_GATE_CILE, 337 CLK_GATE_DSIA_LP, 338 CLK_GATE_DSIB_LP, 339 CLK_GATE_ENTROPY, /* Enabled on reset */ 340 CLK_GATE_AMX0, 341 CLK_GATE_ADX0, 342 CLK_GATE_DVFS, 343 CLK_GATE_XUSB_SS, 344 CLK_GATE_EMC_LATENCY, 345 CLK_GATE_SPARE, 346 CLK_GATE_CAM_MCLK, 347 CLK_GATE_CAM_MCLK2, 348 CLK_GATE_I2C6, 349 CLK_GATE_VIM2_CLK, 350 CLK_GATE_EMC_DLL, 351 CLK_GATE_HDMI_AUDIO, 352 CLK_GATE_CLK72MHZ, 353 CLK_GATE_VIC, 354 CLK_GATE_ADX1, 355 CLK_GATE_DPAUX, 356 CLK_GATE_SOR0, 357 CLK_GATE_GPU, 358 CLK_GATE_AMX1, 359 360 NCLKGATES 361}; 362