1/* 2 * Copyright 2020, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the GNU General Public License version 2. Note that NO WARRANTY is provided. 8 * See "LICENSE_GPLv2.txt" for details. 9 * 10 * @TAG(DATA61_GPL) 11 */ 12 13#pragma once 14 15/* this is a dumping ground */ 16#include <stddef.h> 17#include <stdio.h> 18#include <stdint.h> 19 20#ifndef RESOURCE 21#define RESOURCE(mapper, id) ps_io_map(mapper, (uintptr_t) id##_PADDR, id##_SIZE, 0, PS_MEM_NORMAL) 22#define UNRESOURCE(mapper, id, addr) ps_io_unmap(mapper, addr, id##_SIZE) 23#endif 24 25#define __aligned(x) __attribute__((aligned(x))) 26#define unlikely(x) __builtin_expect(!!(x), 0) 27 28#define __always_inline inline __attribute__((always_inline)) 29#define noinline __attribute__((noinline)) 30 31#define __deprecated __attribute__((deprecated)) 32#define __packed __attribute__((packed)) 33#define __weak __attribute__((weak)) 34#define __alias(symbol) __attribute__((alias(#symbol))) 35#define __must_check __attribute__((warn_unused_result)) 36 37#define MAX_PKT_SIZE 1536 38 39#define BITS_PER_LONG 32 40 41#define ENOTSUPP 524 /* Operation is not supported */ 42 43void udelay(unsigned long us); 44 45unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base); 46 47#ifdef CONFIG_PHYS_64BIT 48typedef unsigned long long phys_addr_t; 49typedef unsigned long long phys_size_t; 50#else 51/* DMA addresses are 32-bits wide */ 52typedef unsigned long phys_addr_t; 53typedef unsigned long phys_size_t; 54#endif 55 56typedef uint64_t u64; 57typedef uint32_t u32; 58typedef uint16_t u16; 59typedef uint8_t u8; 60 61typedef int64_t s64; 62typedef int32_t s32; 63typedef int16_t s16; 64typedef int8_t s8; 65 66typedef unsigned long ulong; 67typedef unsigned short ushort; 68typedef unsigned int uint; 69typedef unsigned char uchar; 70 71typedef u64 __u64; 72typedef u32 __u32; 73typedef u16 __u16; 74typedef u8 __u8; 75 76// typedef u8 bool; 77 78#define __bitwise /*__attribute__((bitwise))*/ 79#define __force /* __attribute__((force)) */ 80 81typedef s64 __bitwise __le64; 82typedef s32 __bitwise __le32; 83typedef s16 __bitwise __le16; 84typedef s8 __bitwise __le8; 85 86typedef s64 __bitwise __be64; 87typedef s32 __bitwise __be32; 88typedef s16 __bitwise __be16; 89typedef s8 __bitwise __be8; 90 91typedef unsigned __bitwise gfp_t; 92 93#define gpio_init() 94#define WATCHDOG_RESET() 95 96typedef struct bd_info { 97 unsigned long bi_memstart; /* start of DRAM memory */ 98 phys_size_t bi_memsize; /* size of DRAM memory in bytes */ 99 unsigned long bi_flashstart; /* start of FLASH memory */ 100 unsigned long bi_flashsize; /* size of FLASH memory */ 101 unsigned long bi_flashoffset; /* reserved area for startup monitor */ 102 unsigned long bi_sramstart; /* start of SRAM memory */ 103 unsigned long bi_sramsize; /* size of SRAM memory */ 104#ifdef CONFIG_AVR32 105 unsigned char bi_phy_id[4]; /* PHY address for ATAG_ETHERNET */ 106 unsigned long bi_board_number;/* ATAG_BOARDINFO */ 107#endif 108#ifdef CONFIG_ARM 109 unsigned long bi_arm_freq; /* arm frequency */ 110 unsigned long bi_dsp_freq; /* dsp core frequency */ 111 unsigned long bi_ddr_freq; /* ddr frequency */ 112#endif 113#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \ 114 || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 115 unsigned long bi_immr_base; /* base of IMMR register */ 116#endif 117#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K) 118 unsigned long bi_mbar_base; /* base of internal registers */ 119#endif 120#if defined(CONFIG_MPC83xx) 121 unsigned long bi_immrbar; 122#endif 123 unsigned long bi_bootflags; /* boot / reboot flag (Unused) */ 124 unsigned long bi_ip_addr; /* IP Address */ 125 unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */ 126 unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ 127 unsigned long bi_intfreq; /* Internal Freq, in MHz */ 128 unsigned long bi_busfreq; /* Bus Freq, in MHz */ 129#if defined(CONFIG_CPM2) 130 unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */ 131 unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */ 132 unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ 133 unsigned long bi_vco; /* VCO Out from PLL, in MHz */ 134#endif 135#if defined(CONFIG_MPC512X) 136 unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */ 137#endif /* CONFIG_MPC512X */ 138#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K) 139 unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ 140 unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ 141#endif 142#if defined(CONFIG_EXTRA_CLOCK) 143 unsigned long bi_inpfreq; /* input Freq in MHz */ 144 unsigned long bi_vcofreq; /* vco Freq in MHz */ 145 unsigned long bi_flbfreq; /* Flexbus Freq in MHz */ 146#endif 147#if defined(CONFIG_405) || \ 148 defined(CONFIG_405GP) || \ 149 defined(CONFIG_405EP) || \ 150 defined(CONFIG_405EZ) || \ 151 defined(CONFIG_405EX) || \ 152 defined(CONFIG_440) 153 unsigned char bi_s_version[4]; /* Version of this structure */ 154 unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ 155 unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */ 156 unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ 157 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ 158 unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ 159#endif 160 161#ifdef CONFIG_HAS_ETH1 162 unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */ 163#endif 164#ifdef CONFIG_HAS_ETH2 165 unsigned char bi_enet2addr[6]; /* OLD: see README.enetaddr */ 166#endif 167#ifdef CONFIG_HAS_ETH3 168 unsigned char bi_enet3addr[6]; /* OLD: see README.enetaddr */ 169#endif 170#ifdef CONFIG_HAS_ETH4 171 unsigned char bi_enet4addr[6]; /* OLD: see README.enetaddr */ 172#endif 173#ifdef CONFIG_HAS_ETH5 174 unsigned char bi_enet5addr[6]; /* OLD: see README.enetaddr */ 175#endif 176 177#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ 178 defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \ 179 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ 180 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 181 defined(CONFIG_460EX) || defined(CONFIG_460GT) 182 unsigned int bi_opbfreq; /* OPB clock in Hz */ 183 int bi_iic_fast[2]; /* Use fast i2c mode */ 184#endif 185#if defined(CONFIG_4xx) 186#if defined(CONFIG_440GX) || \ 187 defined(CONFIG_460EX) || defined(CONFIG_460GT) 188 int bi_phynum[4]; /* Determines phy mapping */ 189 int bi_phymode[4]; /* Determines phy mode */ 190#elif defined(CONFIG_405EP) || defined(CONFIG_405EX) || defined(CONFIG_440) 191 int bi_phynum[2]; /* Determines phy mapping */ 192 int bi_phymode[2]; /* Determines phy mode */ 193#else 194 int bi_phynum[1]; /* Determines phy mapping */ 195 int bi_phymode[1]; /* Determines phy mode */ 196#endif 197#endif /* defined(CONFIG_4xx) */ 198 ulong bi_arch_number; /* unique id for this board */ 199 ulong bi_boot_params; /* where this board expects params */ 200#ifdef CONFIG_NR_DRAM_BANKS 201 struct { /* RAM configuration */ 202 phys_addr_t start; 203 phys_size_t size; 204 } bi_dram[CONFIG_NR_DRAM_BANKS]; 205#endif /* CONFIG_NR_DRAM_BANKS */ 206} bd_t; 207