1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 8 * See "LICENSE_BSD2.txt" for details. 9 * 10 * @TAG(DATA61_BSD) 11 */ 12 13/** 14 * \file edma.c 15 * 16 * \brief Platform related APIs for EDMA 17 */ 18 19/* 20* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 21*/ 22/* 23* Redistribution and use in source and binary forms, with or without 24* modification, are permitted provided that the following conditions 25* are met: 26* 27* Redistributions of source code must retain the above copyright 28* notice, this list of conditions and the following disclaimer. 29* 30* Redistributions in binary form must reproduce the above copyright 31* notice, this list of conditions and the following disclaimer in the 32* documentation and/or other materials provided with the 33* distribution. 34* 35* Neither the name of Texas Instruments Incorporated nor the names of 36* its contributors may be used to endorse or promote products derived 37* from this software without specific prior written permission. 38* 39* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 40* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 41* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 42* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 43* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 44* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 45* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 46* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 47* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 48* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 49* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 50* 51*/ 52 53#include <ethdrivers/plat/hw/hw_control_AM335x.h> 54#include <ethdrivers/plat/hw/soc_AM335x.h> 55#include <ethdrivers/plat/hw/hw_cm_per.h> 56#include <ethdrivers/plat/hw/hw_types.h> 57 58/** 59 * \brief This function maps the crossbar events. 60 * 61 * \param baseAdd It is the Control Module Address. 62 * 63 * \param crossBarEvent It is the crossBar event number. 64 * 65 * \param Channel It is the channel number to which cross bar 66 * event needs to be mapped. 67 */ 68 69unsigned int EDMA3CrossBarChannelMap(unsigned int baseAdd, unsigned int crossBarEvent, 70 unsigned int Channel) 71{ 72 73 unsigned int offset; 74 unsigned int select; 75 unsigned int n = 0; 76 77 /* offset of the TPCC_MUX to be configured */ 78 offset = Channel / 4; 79 80 /* 81 ** Each TPCC_MUX register has four event mux which can be used for 82 ** cross bar mapping.Thus "select" variable is used to select, 83 ** which of the event mux out of four,for a given TPCC_MUX register 84 ** to be used. 85 */ 86 select = Channel - offset * 4; 87 88 switch (select) { 89 case 0: 90 n = 0; 91 break; 92 93 case 1: 94 n = 8; 95 break; 96 97 case 2: 98 n = 16; 99 break; 100 101 case 3: 102 n = 24; 103 break; 104 105 default: 106 break; 107 } 108 109 /* 'n' specifies the offset of the event mux */ 110 HWREG(baseAdd + TPCC_MUX(offset)) &= ~(crossBarEvent << n); 111 112 HWREG(baseAdd + TPCC_MUX(offset)) |= crossBarEvent << n; 113 114 return 0; 115} 116 117/** 118* \brief This API returns a unique number which identifies itself 119* with the EDMA IP in AM335x SoC. 120* \param None 121* \return This returns a number '2' which is unique to EDMA IP in AM335x. 122*/ 123unsigned int EDMAVersionGet(void) 124{ 125 return 2; 126} 127 128/* 129** This function enables the system L3 clocks. 130** This also enables the clocks for EDMA instance. 131*/ 132 133void EDMAModuleClkConfig(void) 134{ 135 /* Configuring L3 Interface Clocks. */ 136 137 /* Writing to MODULEMODE field of CM_PER_L3_CLKCTRL register. */ 138 HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) |= 139 CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE; 140 141 /* Waiting for MODULEMODE field to reflect the written value. */ 142 while (CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE != 143 (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) & 144 CM_PER_L3_CLKCTRL_MODULEMODE)); 145 146 /* Writing to MODULEMODE field of CM_PER_L3_INSTR_CLKCTRL register. */ 147 HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) |= 148 CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE; 149 150 /* Waiting for MODULEMODE field to reflect the written value. */ 151 while (CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE != 152 (HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) & 153 CM_PER_L3_INSTR_CLKCTRL_MODULEMODE)); 154 155 /* Writing to CLKTRCTRL field of CM_PER_L3_CLKSTCTRL register. */ 156 HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) |= 157 CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP; 158 159 /* Waiting for CLKTRCTRL field to reflect the written value. */ 160 while (CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP != 161 (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) & 162 CM_PER_L3_CLKSTCTRL_CLKTRCTRL)); 163 164 /* Writing to CLKTRCTRL field of CM_PER_OCPWP_L3_CLKSTCTRL register. */ 165 HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) |= 166 CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP; 167 168 /*Waiting for CLKTRCTRL field to reflect the written value. */ 169 while (CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP != 170 (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) & 171 CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL)); 172 173 /* Writing to CLKTRCTRL field of CM_PER_L3S_CLKSTCTRL register. */ 174 HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) |= 175 CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP; 176 177 /*Waiting for CLKTRCTRL field to reflect the written value. */ 178 while (CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP != 179 (HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) & 180 CM_PER_L3S_CLKSTCTRL_CLKTRCTRL)); 181 182 /* Checking fields for necessary values. */ 183 184 /* Waiting for IDLEST field in CM_PER_L3_CLKCTRL register to be set to 0x0. */ 185 while ((CM_PER_L3_CLKCTRL_IDLEST_FUNC << CM_PER_L3_CLKCTRL_IDLEST_SHIFT) != 186 (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) & 187 CM_PER_L3_CLKCTRL_IDLEST)); 188 189 /* 190 ** Waiting for IDLEST field in CM_PER_L3_INSTR_CLKCTRL register to attain the 191 ** desired value. 192 */ 193 while ((CM_PER_L3_INSTR_CLKCTRL_IDLEST_FUNC << 194 CM_PER_L3_INSTR_CLKCTRL_IDLEST_SHIFT) != 195 (HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) & 196 CM_PER_L3_INSTR_CLKCTRL_IDLEST)); 197 198 /* 199 ** Waiting for CLKACTIVITY_L3_GCLK field in CM_PER_L3_CLKSTCTRL register to 200 ** attain the desired value. 201 */ 202 while (CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK != 203 (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) & 204 CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK)); 205 206 /* 207 ** Waiting for CLKACTIVITY_OCPWP_L3_GCLK field in CM_PER_OCPWP_L3_CLKSTCTRL 208 ** register to attain the desired value. 209 */ 210 while (CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK != 211 (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) & 212 CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK)); 213 214 /* 215 ** Waiting for CLKACTIVITY_L3S_GCLK field in CM_PER_L3S_CLKSTCTRL register 216 ** to attain the desired value. 217 */ 218 while (CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK != 219 (HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) & 220 CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK)); 221 222 /* Configuring clocks for EDMA3 TPCC and TPTCs. */ 223 224 /* Writing to MODULEMODE field of CM_PER_TPCC_CLKCTRL register. */ 225 HWREG(SOC_CM_PER_REGS + CM_PER_TPCC_CLKCTRL) |= 226 CM_PER_TPCC_CLKCTRL_MODULEMODE_ENABLE; 227 228 /* Waiting for MODULEMODE field to reflect the written value. */ 229 while (CM_PER_TPCC_CLKCTRL_MODULEMODE_ENABLE != 230 (HWREG(SOC_CM_PER_REGS + CM_PER_TPCC_CLKCTRL) & 231 CM_PER_TPCC_CLKCTRL_MODULEMODE)); 232 233 /* Writing to MODULEMODE field of CM_PER_TPTC0_CLKCTRL register. */ 234 HWREG(SOC_CM_PER_REGS + CM_PER_TPTC0_CLKCTRL) |= 235 CM_PER_TPTC0_CLKCTRL_MODULEMODE_ENABLE; 236 237 /* Waiting for MODULEMODE field to reflect the written value. */ 238 while (CM_PER_TPTC0_CLKCTRL_MODULEMODE_ENABLE != 239 (HWREG(SOC_CM_PER_REGS + CM_PER_TPTC0_CLKCTRL) & 240 CM_PER_TPTC0_CLKCTRL_MODULEMODE)); 241 242 /* Writing to MODULEMODE field of CM_PER_TPTC1_CLKCTRL register. */ 243 HWREG(SOC_CM_PER_REGS + CM_PER_TPTC1_CLKCTRL) |= 244 CM_PER_TPTC1_CLKCTRL_MODULEMODE_ENABLE; 245 246 /* Waiting for MODULEMODE field to reflect the written value. */ 247 while (CM_PER_TPTC1_CLKCTRL_MODULEMODE_ENABLE != 248 (HWREG(SOC_CM_PER_REGS + CM_PER_TPTC1_CLKCTRL) & 249 CM_PER_TPTC1_CLKCTRL_MODULEMODE)); 250 251 /* Writing to MODULEMODE field of CM_PER_TPTC2_CLKCTRL register. */ 252 HWREG(SOC_CM_PER_REGS + CM_PER_TPTC2_CLKCTRL) |= 253 CM_PER_TPTC2_CLKCTRL_MODULEMODE_ENABLE; 254 255 /* Waiting for MODULEMODE field to reflect the written value. */ 256 while (CM_PER_TPTC2_CLKCTRL_MODULEMODE_ENABLE != 257 (HWREG(SOC_CM_PER_REGS + CM_PER_TPTC2_CLKCTRL) & 258 CM_PER_TPTC2_CLKCTRL_MODULEMODE)); 259 260 /* 261 ** Waiting for IDLEST field in CM_PER_TPCC_CLKCTRL register to attain the 262 ** desired value. 263 */ 264 while ((CM_PER_TPCC_CLKCTRL_IDLEST_FUNC << 265 CM_PER_TPCC_CLKCTRL_IDLEST_SHIFT) != 266 (HWREG(SOC_CM_PER_REGS + CM_PER_TPCC_CLKCTRL) & 267 CM_PER_TPCC_CLKCTRL_IDLEST)); 268 269 /* 270 ** Waiting for IDLEST field in CM_PER_TPTC0_CLKCTRL register to attain the 271 ** desired value. 272 */ 273 while ((CM_PER_TPTC0_CLKCTRL_IDLEST_FUNC << 274 CM_PER_TPTC0_CLKCTRL_IDLEST_SHIFT) != 275 (HWREG(SOC_CM_PER_REGS + CM_PER_TPTC0_CLKCTRL) & 276 CM_PER_TPTC0_CLKCTRL_IDLEST)); 277 278 /* 279 ** Waiting for STBYST field in CM_PER_TPTC0_CLKCTRL register to attain the 280 ** desired value. 281 */ 282 while ((CM_PER_TPTC0_CLKCTRL_STBYST_FUNC << 283 CM_PER_TPTC0_CLKCTRL_STBYST_SHIFT) != 284 (HWREG(SOC_CM_PER_REGS + CM_PER_TPTC0_CLKCTRL) & 285 CM_PER_TPTC0_CLKCTRL_STBYST)); 286 287 /* 288 ** Waiting for IDLEST field in CM_PER_TPTC1_CLKCTRL register to attain the 289 ** desired value. 290 */ 291 while ((CM_PER_TPTC1_CLKCTRL_IDLEST_FUNC << 292 CM_PER_TPTC1_CLKCTRL_IDLEST_SHIFT) != 293 (HWREG(SOC_CM_PER_REGS + CM_PER_TPTC1_CLKCTRL) & 294 CM_PER_TPTC1_CLKCTRL_IDLEST)); 295 296 /* 297 ** Waiting for STBYST field in CM_PER_TPTC1_CLKCTRL register to attain the 298 ** desired value. 299 */ 300 while ((CM_PER_TPTC1_CLKCTRL_STBYST_FUNC << 301 CM_PER_TPTC1_CLKCTRL_STBYST_SHIFT) != 302 (HWREG(SOC_CM_PER_REGS + CM_PER_TPTC1_CLKCTRL) & 303 CM_PER_TPTC1_CLKCTRL_STBYST)); 304 305 /* 306 ** Waiting for IDLEST field in CM_PER_TPTC2_CLKCTRL register to attain the 307 ** desired value. 308 */ 309 while ((CM_PER_TPTC2_CLKCTRL_IDLEST_FUNC << 310 CM_PER_TPTC2_CLKCTRL_IDLEST_SHIFT) != 311 (HWREG(SOC_CM_PER_REGS + CM_PER_TPTC2_CLKCTRL) & 312 CM_PER_TPTC2_CLKCTRL_IDLEST)); 313 314 /* 315 ** Waiting for STBYST field in CM_PER_TPTC2_CLKCTRL register to attain the 316 ** desired value. 317 */ 318 while ((CM_PER_TPTC2_CLKCTRL_STBYST_FUNC << 319 CM_PER_TPTC2_CLKCTRL_STBYST_SHIFT) != 320 (HWREG(SOC_CM_PER_REGS + CM_PER_TPTC2_CLKCTRL) & 321 CM_PER_TPTC2_CLKCTRL_STBYST)); 322} 323