1/* @TAG(CUSTOM) *//** 2 * \file edma.c 3 * 4 * \brief This file contains device abstraction layer APIs for the EDMA device. 5 * There are APIs here to enable the EDMA instance, set the required 6 * configurations for communication, transmit or receive data. 7 */ 8 9/* 10* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 11*/ 12/* 13* Redistribution and use in source and binary forms, with or without 14* modification, are permitted provided that the following conditions 15* are met: 16* 17* Redistributions of source code must retain the above copyright 18* notice, this list of conditions and the following disclaimer. 19* 20* Redistributions in binary form must reproduce the above copyright 21* notice, this list of conditions and the following disclaimer in the 22* documentation and/or other materials provided with the 23* distribution. 24* 25* Neither the name of Texas Instruments Incorporated nor the names of 26* its contributors may be used to endorse or promote products derived 27* from this software without specific prior written permission. 28* 29* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40* 41*/ 42 43/* Driver APIs */ 44#include <utils/attribute.h> 45#include <ethdrivers/plat/edma.h> 46 47#include <ethdrivers/plat/hw/hw_types.h> 48 49/****************************************************************************/ 50/* GLOBAL VARIABLES */ 51/****************************************************************************/ 52unsigned int regionId; 53 54/****************************************************************************/ 55/* API FUNCTION DEFINITIONS */ 56/****************************************************************************/ 57 58/** 59 * \brief EDMA3 Initialization 60 * 61 * This function initializes the EDMA3 Driver 62 * Clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR) & 63 * initialize the Queue Number Registers 64 * 65 * \param baseAdd Memory address of the EDMA instance used.\n 66 * 67 * \param queNum Event Queue Number to which the channel 68 * will be mapped (valid only for the 69 * Master Channel (DMA/QDMA) request).\n 70 * 71 * \return None 72 * 73 * \note The regionId is the shadow region(0 or 1) used and the, 74 * Event Queue used is either (0 or 1). There are only four shadow 75 * regions and only two event Queues 76 */ 77void EDMA3Init(unsigned int baseAdd, 78 unsigned int queNum) 79{ 80 unsigned int count = 0; 81 unsigned int i = 0; 82 83#ifdef _TMS320C6X 84 /* For DSP, regionId is assigned here and used globally in the driver */ 85 regionId = (unsigned int)1u; 86#else 87 /* FOR ARM, regionId is assigned here and used globally in the driver */ 88 regionId = (unsigned int)0u; 89#endif 90 91 /* Clear the Event miss Registers */ 92 HWREG(baseAdd + EDMA3CC_EMCR) = EDMA3_SET_ALL_BITS; 93 HWREG(baseAdd + EDMA3CC_EMCRH) = EDMA3_SET_ALL_BITS; 94 95 HWREG(baseAdd + EDMA3CC_QEMCR) = EDMA3_SET_ALL_BITS; 96 97 /* Clear CCERR register */ 98 HWREG(baseAdd + EDMA3CC_CCERRCLR) = EDMA3_SET_ALL_BITS; 99 100 /* FOR TYPE EDMA*/ 101 /* Enable the DMA (0 - 64) channels in the DRAE and DRAEH register */ 102 103 HWREG(baseAdd + EDMA3CC_DRAE(regionId)) = EDMA3_SET_ALL_BITS; 104 HWREG(baseAdd + EDMA3CC_DRAEH(regionId)) = EDMA3_SET_ALL_BITS; 105 106 if ((EDMA_REVID_AM335X == EDMAVersionGet())) { 107 for (i = 0; i < 64; i++) { 108 /* All events are one to one mapped with the channels */ 109 HWREG(baseAdd + EDMA3CC_DCHMAP(i)) = i << 5; 110 } 111 112 } 113 /* Initialize the DMA Queue Number Registers */ 114 for (count = 0; count < SOC_EDMA3_NUM_DMACH; count++) { 115 HWREG(baseAdd + EDMA3CC_DMAQNUM(count >> 3u)) &= 116 EDMA3CC_DMAQNUM_CLR(count); 117 HWREG(baseAdd + EDMA3CC_DMAQNUM(count >> 3u)) |= 118 EDMA3CC_DMAQNUM_SET(count, queNum); 119 } 120 121 /* FOR TYPE QDMA */ 122 /* Enable the DMA (0 - 64) channels in the DRAE register */ 123 HWREG(baseAdd + EDMA3CC_QRAE(regionId)) = EDMA3_SET_ALL_BITS; 124 125 /* Initialize the QDMA Queue Number Registers */ 126 for (count = 0; count < SOC_EDMA3_NUM_QDMACH; count++) { 127 HWREG(baseAdd + EDMA3CC_QDMAQNUM) &= EDMA3CC_QDMAQNUM_CLR(count); 128 HWREG(baseAdd + EDMA3CC_QDMAQNUM) |= 129 EDMA3CC_QDMAQNUM_SET(count, queNum); 130 } 131} 132 133/** 134 * \brief This API return the revision Id of the peripheral. 135 * 136 * \param baseAdd Memory address of the EDMA instance used.\n 137 * 138 * \return None 139 */ 140unsigned int EDMA3PeripheralIdGet(unsigned int baseAdd) 141{ 142 return (HWREG(baseAdd + EDMA3CC_REVID)); 143} 144 145/** 146 * \brief Enable channel to Shadow region mapping 147 * 148 * This API allocates DMA/QDMA channels or TCCs, and the same resources are 149 * enabled in the shadow region specific register (DRAE/DRAEH/QRAE). 150 * Here only one shadow region is used since, there is only one Master. 151 * 152 * \param baseAdd Memory address of the EDMA instance used.\n 153 * 154 * \param chtype (DMA/QDMA) Channel 155 * For Example: For DMA it is, 156 * EDMA3_CHANNEL_TYPE_DMA.\n 157 * 158 * \param chNum Allocated channel number.\n 159 * 160 * chtype can have values 161 * EDMA3_CHANNEL_TYPE_DMA\n 162 * EDMA3_CHANNEL_TYPE_QDMA 163 * 164 * \return None 165 */ 166void EDMA3EnableChInShadowReg(unsigned int baseAdd, 167 unsigned int chType, 168 unsigned int chNum) 169{ 170 /* Allocate the DMA/QDMA channel */ 171 if (EDMA3_CHANNEL_TYPE_DMA == chType) { 172 /* FOR TYPE EDMA*/ 173 if (chNum < 32) { 174 /* Enable the DMA channel in the DRAE registers */ 175 HWREG(baseAdd + EDMA3CC_DRAE(regionId)) |= (0x01u << chNum); 176 } else { 177 /* Enable the DMA channel in the DRAEH registers */ 178 HWREG(baseAdd + EDMA3CC_DRAEH(regionId)) |= (0x01u << (chNum - 32)); 179 } 180 181 } else if (EDMA3_CHANNEL_TYPE_QDMA == chType) { 182 /* FOR TYPE QDMA */ 183 /* Enable the QDMA channel in the DRAE/DRAEH registers */ 184 HWREG(baseAdd + EDMA3CC_QRAE(regionId)) |= 0x01u << chNum; 185 } 186} 187 188/** 189 * \brief Disable channel to Shadow region mapping 190 * 191 * This API allocates DMA/QDMA channels or TCCs, and the same resources are 192 * enabled in the shadow region specific register (DRAE/DRAEH/QRAE). 193 * Here only one shadow region is used since, there is only one Master. 194 * 195 * \param baseAdd Memory address of the EDMA instance used.\n 196 * 197 * \param chtype (DMA/QDMA) Channel 198 * For Example: For DMA it is, 199 * EDMA3_CHANNEL_TYPE_DMA.\n 200 * 201 * \param chNum Allocated channel number.\n 202 * 203 * chtype can have values 204 * EDMA3_CHANNEL_TYPE_DMA\n 205 * EDMA3_CHANNEL_TYPE_QDMA 206 * 207 * \return None 208 */ 209void EDMA3DisableChInShadowReg(unsigned int baseAdd, 210 unsigned int chType, 211 unsigned int chNum) 212{ 213 /* Allocate the DMA/QDMA channel */ 214 if (EDMA3_CHANNEL_TYPE_DMA == chType) { 215 /* FOR TYPE EDMA*/ 216 if (chNum < 32) { 217 /* Enable the DMA channel in the DRAE registers */ 218 HWREG(baseAdd + EDMA3CC_DRAE(regionId)) &= ~(0x01u << chNum); 219 } else { 220 /* Enable the DMA channel in the DRAEH registers */ 221 HWREG(baseAdd + EDMA3CC_DRAEH(regionId)) &= ~(0x01u << (chNum - 32)); 222 } 223 } else if (EDMA3_CHANNEL_TYPE_QDMA == chType) { 224 /* FOR TYPE QDMA */ 225 /* Enable the QDMA channel in the DRAE/DRAEH registers */ 226 HWREG(baseAdd + EDMA3CC_QRAE(regionId)) &= ((~0x01u) << chNum); 227 } 228} 229 230/** 231 * \brief This function maps DMA channel to any of the PaRAM sets 232 * in the PaRAM memory map. 233 * 234 * \param baseAdd Memory address of the EDMA instance used. 235 * 236 * \param channel The DMA channel number required to be mapped. 237 * 238 * \param paramSet It specifies the paramSet to which DMA channel 239 * required to be mapped. 240 * 241 * \return None 242 */ 243void EDMA3ChannelToParamMap(unsigned int baseAdd, 244 unsigned int channel, 245 unsigned int paramSet) 246{ 247 HWREG(baseAdd + EDMA3CC_DCHMAP(channel)) = paramSet << 5; 248} 249 250/** 251 * \brief Map channel to Event Queue 252 * 253 * This API maps DMA/QDMA channels to the Event Queue 254 * 255 * \param baseAdd Memory address of the EDMA instance used.\n 256 * 257 * \param chtype (DMA/QDMA) Channel 258 * For Example: For QDMA it is 259 * EDMA3_CHANNEL_TYPE_QDMA.\n 260 * 261 * \param chNum Allocated channel number.\n 262 * 263 * \param evtQNum Event Queue Number to which the channel 264 * will be mapped (valid only for the 265 * Master Channel (DMA/QDMA) request).\n 266 * 267 * chtype can have values 268 * EDMA3_CHANNEL_TYPE_DMA\n 269 * EDMA3_CHANNEL_TYPE_QDMA 270 * 271 * \return None 272 */ 273void EDMA3MapChToEvtQ(unsigned int baseAdd, 274 unsigned int chType, 275 unsigned int chNum, 276 unsigned int evtQNum) 277{ 278 if (EDMA3_CHANNEL_TYPE_DMA == chType) { 279 /* Associate DMA Channel to Event Queue */ 280 HWREG(baseAdd + EDMA3CC_DMAQNUM((chNum) >> 3u)) &= 281 EDMA3CC_DMAQNUM_CLR(chNum); 282 283 HWREG(baseAdd + EDMA3CC_DMAQNUM((chNum) >> 3u)) |= 284 EDMA3CC_DMAQNUM_SET((chNum), evtQNum); 285 } else if (EDMA3_CHANNEL_TYPE_QDMA == chType) { 286 /* Associate QDMA Channel to Event Queue */ 287 HWREG(baseAdd + EDMA3CC_QDMAQNUM) |= 288 EDMA3CC_QDMAQNUM_SET(chNum, evtQNum); 289 } 290} 291 292/** 293 * \brief Remove Mapping of channel to Event Queue 294 * 295 * This API Unmaps DMA/QDMA channels to the Event Queue allocated 296 * 297 * \param baseAdd Memory address of the EDMA instance used.\n 298 * 299 * \param chtype (DMA/QDMA) Channel 300 * For Example: For DMA it is 301 * EDMA3_CHANNEL_TYPE_DMA.\n 302 * 303 * \param chNum Allocated channel number.\n 304 * 305 * chtype can have values 306 * EDMA3_CHANNEL_TYPE_DMA\n 307 * EDMA3_CHANNEL_TYPE_QDMA 308 * 309 * \return None 310 */ 311void EDMA3UnmapChToEvtQ(unsigned int baseAdd, 312 unsigned int chType, 313 unsigned int chNum) 314{ 315 if (EDMA3_CHANNEL_TYPE_DMA == chType) { 316 /* Unmap DMA Channel to Event Queue */ 317 HWREG(baseAdd + EDMA3CC_DMAQNUM((chNum) >> 3u)) |= 318 EDMA3CC_DMAQNUM_CLR(chNum); 319 } else if (EDMA3_CHANNEL_TYPE_QDMA == chType) { 320 /* Unmap QDMA Channel to Event Queue */ 321 HWREG(baseAdd + EDMA3CC_QDMAQNUM) |= 322 EDMA3CC_QDMAQNUM_CLR(chNum); 323 } 324} 325 326/** 327 * \brief Enables the user to map a QDMA channel to PaRAM set 328 * This API Needs to be called before programming the paRAM sets for 329 * the QDMA Channels.Application needs to maitain the paRAMId 330 * provided by this API.This paRAMId is used to set paRAM and get 331 * paRAM. Refer corresponding API's for more details. 332 * 333 * \param baseAdd Memory address of the EDMA instance used.\n 334 * 335 * \param chNum Allocated QDMA channel number.\n 336 * 337 * \param paRaMID PaRAM Id to which the QDMA channel will be 338 * mapped to. 339 * 340 * \return None 341 * 342 * Note : The PaRAMId requested must be greater than 32(SOC_EDMA3_NUM_DMACH). 343 * and lesser than SOC_EDMA3_NUM_DMACH + chNum Because, the first 344 * 32 PaRAM's are directly mapped to first 32 DMA channels and (32 - 38) 345 * for QDMA Channels. (32 - 38) is assigned by driver in this API. 346 * 347 */ 348void EDMA3MapQdmaChToPaRAM(unsigned int baseAdd, 349 unsigned int chNum, 350 unsigned int *paRAMId) 351{ 352 /* First 32 channels are for DMA only */ 353 /* if (((*paRAMId) > SOC_EDMA3_NUM_DMACH) && 354 ((*paRAMId) < SOC_EDMA3_NUM_DMACH+SOC_EDMA3_NUM_QDMACH)) */ 355 if ((SOC_EDMA3_NUM_DMACH + chNum) == (*paRAMId)) { 356 /* Map Parameter RAM Set Number for specified channelId */ 357 HWREG(baseAdd + EDMA3CC_QCHMAP(chNum)) &= EDMA3CC_QCHMAP_PAENTRY_CLR; 358 HWREG(baseAdd + EDMA3CC_QCHMAP(chNum)) |= EDMA3CC_QCHMAP_PAENTRY_SET(*paRAMId); 359 } else { 360 (*paRAMId) = (SOC_EDMA3_NUM_DMACH + chNum); 361 /* Map Parameter RAM Set Number for specified channelId */ 362 HWREG(baseAdd + EDMA3CC_QCHMAP(chNum)) &= EDMA3CC_QCHMAP_PAENTRY_CLR; 363 HWREG(baseAdd + EDMA3CC_QCHMAP(chNum)) |= EDMA3CC_QCHMAP_PAENTRY_SET(*paRAMId); 364 } 365} 366 367/** 368 * \brief Assign a Trigger Word to the specified QDMA channel 369 * 370 * This API sets the Trigger word for the specific QDMA channel in the QCHMAP 371 * Register. Default QDMA trigger word is CCNT. 372 * 373 * \param baseAdd Memory address of the EDMA instance used.\n 374 * 375 * \param chNum QDMA Channel which needs to be assigned 376 * the Trigger Word 377 * 378 * \param trigWord The Trigger Word for the QDMA channel. 379 * Trigger Word is the word in the PaRAM 380 * Register Set which, when written to by CPU, 381 * will start the QDMA transfer automatically. 382 * 383 * \return None 384 */ 385void EDMA3SetQdmaTrigWord(unsigned int baseAdd, 386 unsigned int chNum, 387 unsigned int trigWord) 388{ 389 /* Set the Trigger Word */ 390 HWREG(baseAdd + EDMA3CC_QCHMAP(chNum)) |= EDMA3CC_QCHMAP_TRWORD_SET(trigWord); 391} 392 393/** 394 * \brief Enables the user to Clear any missed event 395 * 396 * \param baseAdd Memory address of the EDMA instance used.\n 397 * 398 * \param chNum Allocated channel number.\n 399 * 400 * \return None 401 */ 402void EDMA3ClrMissEvt(unsigned int baseAdd, 403 unsigned int chNum) 404{ 405 if (chNum < 32) { 406 /*clear SECR to clean any previous NULL request */ 407 HWREG(baseAdd + EDMA3CC_S_SECR(regionId)) = (0x01u << chNum); 408 /*clear EMCR to clean any previous NULL request */ 409 HWREG(baseAdd + EDMA3CC_EMCR) |= (0x01u << chNum); 410 } else { 411 HWREG(baseAdd + EDMA3CC_S_SECRH(regionId)) = (0x01u << (chNum - 32)); 412 /*clear EMCRH to clean any previous NULL request */ 413 HWREG(baseAdd + EDMA3CC_EMCRH) |= (0x01u << (chNum - 32)); 414 } 415} 416 417/** 418 * \brief Enables the user to Clear any QDMA missed event 419 * 420 * 421 * \param baseAdd Memory address of the EDMA instance used.\n 422 * 423 * \param chNum Allocated channel number.\n 424 * 425 * \return None 426 */ 427void EDMA3QdmaClrMissEvt(unsigned int baseAdd, 428 unsigned int chNum) 429{ 430 /*clear SECR to clean any previous NULL request */ 431 HWREG(baseAdd + EDMA3CC_S_QSECR(regionId)) = (0x01u << chNum); 432 433 /*clear EMCR to clean any previous NULL request */ 434 HWREG(baseAdd + EDMA3CC_QEMCR) |= (0x01u << chNum); 435} 436 437/** 438 * \brief Enables the user to Clear any Channel controller Errors 439 * 440 * \param baseAdd Memory address of the EDMA instance used.\n 441 * 442 * \param Flags Masks to be passed.\n 443 * 444 * Flags can have values: 445 * 446 * EDMA3CC_CLR_TCCERR Clears the TCCERR bit in the EDMA3CC 447 * ERR Reg\n 448 * EDMA3CC_CLR_QTHRQ0 Queue threshold error clear for queue 0.\n 449 * EDMA3CC_CLR_QTHRQ1 Queue threshold error clear for queue 1. 450 * 451 * \return None 452 */ 453void EDMA3ClrCCErr(unsigned int baseAdd, 454 unsigned int Flags) 455{ 456 /* (CCERRCLR) - clear channel controller error register */ 457 HWREG(baseAdd + EDMA3CC_CCERRCLR) = Flags; 458} 459 460/** 461 * \brief Enables the user to Set an event. This API helps user to manually 462 * set events to initiate DMA transfer requests. 463 * 464 * \param baseAdd Memory address of the EDMA instance used.\n 465 * 466 * \param chNum Allocated channel number.\n 467 * 468 * \return None 469 * 470 * Note : This API is generally used during Manual transfers.\n 471 */ 472void EDMA3SetEvt(unsigned int baseAdd, 473 unsigned int chNum) 474{ 475 if (chNum < 32) { 476 /* (ESR) - set corresponding bit to set a event */ 477 HWREG(baseAdd + EDMA3CC_S_ESR(regionId)) |= (0x01u << chNum); 478 } else { 479 /* (ESRH) - set corresponding bit to set a event */ 480 HWREG(baseAdd + EDMA3CC_S_ESRH(regionId)) |= (0x01u << (chNum - 32)); 481 } 482} 483 484/** 485 * \brief Enables the user to Clear an event. 486 * 487 * \param baseAdd Memory address of the EDMA instance used.\n 488 * 489 * \param chNum Allocated channel number.\n 490 * 491 * \return None 492 * 493 * Note : This API is generally used during Manual transfers.\n 494 */ 495void EDMA3ClrEvt(unsigned int baseAdd, 496 unsigned int chNum) 497{ 498 if (chNum < 32) { 499 /* (ECR) - set corresponding bit to clear a event */ 500 HWREG(baseAdd + EDMA3CC_S_ECR(regionId)) |= (0x01u << chNum); 501 } else { 502 /* (ECRH) - set corresponding bit to clear a event */ 503 HWREG(baseAdd + EDMA3CC_S_ECRH(regionId)) |= (0x01u << (chNum - 32)); 504 } 505} 506 507/** 508 * \brief Enables the user to enable an DMA event. 509 * 510 * \param baseAdd Memory address of the EDMA instance used.\n 511 * 512 * \param chNum Allocated channel number.\n 513 * 514 * \return None 515 * 516 * Note : Writes of 1 to the bits in EESR sets the corresponding event 517 * bits in EER. This is generally used for Event Based transfers.\n 518 */ 519void EDMA3EnableDmaEvt(unsigned int baseAdd, 520 unsigned int chNum) 521{ 522 if (chNum < 32) { 523 /* (EESR) - set corresponding bit to enable DMA event */ 524 HWREG(baseAdd + EDMA3CC_S_EESR(regionId)) |= (0x01u << chNum); 525 } else { 526 /* (EESRH) - set corresponding bit to enable DMA event */ 527 HWREG(baseAdd + EDMA3CC_S_EESRH(regionId)) |= (0x01u << (chNum - 32)); 528 } 529} 530 531/** 532 * \brief Enables the user to Disable an DMA event. 533 * 534 * \param baseAdd Memory address of the EDMA instance used.\n 535 * 536 * \param chNum Allocated channel number.\n 537 * 538 * \return None 539 * 540 * Note : Writes of 1 to the bits in EECR clear the corresponding event bits 541 * in EER; writes of 0 have no effect.. This is generally used for 542 * Event Based transfers.\n 543 */ 544void EDMA3DisableDmaEvt(unsigned int baseAdd, 545 unsigned int chNum) 546{ 547 if (chNum < 32) { 548 /* (EECR) - set corresponding bit to disable event */ 549 HWREG(baseAdd + EDMA3CC_S_EECR(regionId)) |= (0x01u << chNum); 550 } else { 551 /* (EECRH) - set corresponding bit to disable event */ 552 HWREG(baseAdd + EDMA3CC_S_EECRH(regionId)) |= (0x01u << chNum); 553 } 554} 555 556/** 557 * \brief Enables the user to enable an QDMA event. 558 * 559 * \param baseAdd Memory address of the EDMA instance used.\n 560 * 561 * \param chNum Allocated channel number.\n 562 * 563 * \return None 564 * 565 * Note : Writes of 1 to the bits in QEESR sets the corresponding event 566 bits in QEER.\n 567 */ 568void EDMA3EnableQdmaEvt(unsigned int baseAdd, 569 unsigned int chNum) 570{ 571 /* (QEESR) - set corresponding bit to enable QDMA event */ 572 HWREG(baseAdd + EDMA3CC_S_QEESR(regionId)) = (0x01u << chNum); 573} 574 575/** 576 * \brief Enables the user to disable an QDMA event. 577 * 578 * \param baseAdd Memory address of the EDMA instance used.\n 579 * 580 * \param chNum Allocated channel number.\n 581 * 582 * \return None 583 * 584 * Note : Writes of 1 to the bits in QEECR clears the corresponding event 585 bits in QEER.\n 586 */ 587void EDMA3DisableQdmaEvt(unsigned int baseAdd, 588 unsigned int chNum) 589{ 590 /* (QEESR) - set corresponding bit to enable QDMA event */ 591 HWREG(baseAdd + EDMA3CC_S_QEECR(regionId)) = (0x01u << chNum); 592} 593 594/** 595 * \brief This returns EDMA3 CC error status. 596 * 597 * \param baseAdd Memory address of the EDMA instance used.\n 598 * 599 * \return value Status of the Interrupt Pending Register 600 * 601 */ 602unsigned int EDMA3GetCCErrStatus(unsigned int baseAdd) 603{ 604 unsigned int IntrStatusVal = 0; 605 IntrStatusVal = (unsigned int)HWREG(baseAdd + EDMA3CC_CCERR); 606 607 return IntrStatusVal; 608} 609 610/** 611 * \brief This function returns interrupts status of those events 612 * which is less than 32. 613 * 614 * \param baseAdd Memory address of the EDMA instance used.\n 615 * 616 * \return value Status of the Interrupt Pending Register 617 * 618 */ 619unsigned int EDMA3GetIntrStatus(unsigned int baseAdd) 620{ 621 unsigned int IntrStatusVal = 0; 622 623 IntrStatusVal = (unsigned int)HWREG(baseAdd + EDMA3CC_S_IPR(regionId)); 624 625 return IntrStatusVal; 626} 627 628/** 629 * \brief This function returns interrupts status of those events 630 * which is greater than 32. 631 * 632 * \param baseAdd Memory address of the EDMA instance used.\n 633 * 634 * \return value Status of the Interrupt Pending Register 635 * 636 */ 637unsigned int EDMA3IntrStatusHighGet(unsigned int baseAdd) 638{ 639 unsigned int IntrStatusVal = 0; 640 641 IntrStatusVal = (unsigned int)HWREG(baseAdd + EDMA3CC_S_IPRH(regionId)); 642 643 return IntrStatusVal; 644} 645 646/** 647 * \brief This returns error interrupt status for those events whose 648 * event number is less than 32. 649 * 650 * \param baseAdd Memory address of the EDMA instance used.\n 651 * 652 * \return value Status of the Interrupt Pending Register 653 * 654 */ 655unsigned int EDMA3GetErrIntrStatus(unsigned int baseAdd) 656{ 657 unsigned int IntrStatusVal = 0; 658 659 IntrStatusVal = (unsigned int)HWREG(baseAdd + EDMA3CC_EMR); 660 661 return IntrStatusVal; 662} 663 664/** 665 * \brief This returns error interrupt status for those events whose 666 * event number is greater than 32. 667 * 668 * \param baseAdd Memory address of the EDMA instance used.\n 669 * 670 * \return value Status of the Interrupt Pending Register 671 * 672 */ 673unsigned int EDMA3ErrIntrHighStatusGet(unsigned int baseAdd) 674{ 675 unsigned int IntrStatusVal = 0; 676 677 IntrStatusVal = (unsigned int)HWREG(baseAdd + EDMA3CC_EMRH); 678 679 return IntrStatusVal; 680} 681 682/** 683 * \brief This returns QDMA error interrupt status. 684 * 685 * \param baseAdd Memory address of the EDMA instance used.\n 686 * 687 * \return value Status of the QDMA Interrupt Pending Register 688 * 689 */ 690unsigned int EDMA3QdmaGetErrIntrStatus(unsigned int baseAdd) 691{ 692 unsigned int IntrStatusVal = 0; 693 IntrStatusVal = (unsigned int)HWREG(baseAdd + EDMA3CC_QEMR); 694 695 return IntrStatusVal; 696} 697 698/** 699 * \brief Enables the user to enable the transfer completion interrupt 700 * generation by the EDMA3CC for all DMA/QDMA channels. 701 * 702 * \param baseAdd Memory address of the EDMA instance used.\n 703 * 704 * \param chNum Allocated channel number.\n 705 * 706 * \return None 707 * 708 * Note : To set any interrupt bit in IER, a 1 must be written to the 709 * corresponding interrupt bit in the interrupt enable set register. 710 */ 711void EDMA3EnableEvtIntr(unsigned int baseAdd, 712 unsigned int chNum) 713{ 714 if (chNum < 32) { 715 /* Interrupt Enable Set Register (IESR) */ 716 HWREG(baseAdd + EDMA3CC_S_IESR(regionId)) |= (0x01u << chNum); 717 } else { 718 /* Interrupt Enable Set Register (IESRH) */ 719 HWREG(baseAdd + EDMA3CC_S_IESRH(regionId)) |= (0x01u << (chNum - 32)); 720 } 721} 722 723/** 724 * \brief Enables the user to clear CC interrupts 725 * 726 * \param baseAdd Memory address of the EDMA instance used.\n 727 * 728 * \param chNum Allocated channel number.\n 729 * 730 * \return None 731 * 732 * Note : Writes of 1 to the bits in IECR clear the corresponding interrupt 733 * bits in the interrupt enable registers (IER); writes of 0 have 734 * no effect.\n 735 */ 736void EDMA3DisableEvtIntr(unsigned int baseAdd, 737 unsigned int chNum) 738{ 739 if (chNum < 32) { 740 /* Interrupt Enable Clear Register (IECR) */ 741 HWREG(baseAdd + EDMA3CC_S_IECR(regionId)) |= (0x01u << chNum); 742 } else { 743 /* Interrupt Enable Clear Register (IECRH) */ 744 HWREG(baseAdd + EDMA3CC_S_IECRH(regionId)) |= (0x01u << (chNum - 32)); 745 } 746} 747 748/** 749 * \brief Enables the user to Clear an Interrupt. 750 * 751 * \param baseAdd Memory address of the EDMA instance used. 752 * 753 * \param value Value to be set to clear the Interrupt Status. 754 * 755 * \return None 756 * 757 */ 758void EDMA3ClrIntr(unsigned int baseAdd, unsigned int value) 759{ 760 if (value < 32) { 761 HWREG(baseAdd + EDMA3CC_S_ICR(regionId)) = (1u << value); 762 } else { 763 HWREG(baseAdd + EDMA3CC_S_ICRH(regionId)) = (1u << (value - 32)); 764 } 765} 766 767/** 768 * \brief Retrieve existing PaRAM set associated with specified logical 769 * channel (DMA/Link). 770 * 771 * \param baseAdd Memory address of the EDMA instance used.\n 772 * 773 * \param chNum Logical Channel whose PaRAM set is 774 * requested.\n 775 * 776 * \param currPaRAM User gets the existing PaRAM here.\n 777 * 778 * \return None 779 */ 780void EDMA3GetPaRAM(unsigned int baseAdd, 781 unsigned int PaRAMId, 782 EDMA3CCPaRAMEntry* currPaRAM) 783{ 784 unsigned int i = 0; 785 unsigned int *sr; 786 unsigned int *ds = (unsigned int *)currPaRAM; 787 788 sr = (unsigned int *)(baseAdd + EDMA3CC_OPT(PaRAMId)); 789 790 for (i = 0; i < EDMA3CC_PARAM_ENTRY_FIELDS; i++) { 791 *ds++ = *sr++; 792 } 793} 794 795/** 796 * \brief Retrieve existing PaRAM set associated with specified logical 797 * channel (QDMA). 798 * 799 * \param baseAdd Memory address of the EDMA instance used.\n 800 * 801 * \param chNum Logical Channel whose PaRAM set is 802 * requested.\n 803 * 804 * \param currPaRAM User gets the existing PaRAM here.\n 805 * 806 * \return None 807 */ 808void EDMA3QdmaGetPaRAM(unsigned int baseAdd, 809 UNUSED unsigned int chNum, 810 unsigned int paRAMId, 811 EDMA3CCPaRAMEntry* currPaRAM) 812{ 813 unsigned int i = 0; 814 unsigned int *sr; 815 unsigned int *ds = (unsigned int *)currPaRAM; 816 817 sr = (unsigned int *)(baseAdd + EDMA3CC_OPT(paRAMId)); 818 819 for (i = 0; i < EDMA3CC_PARAM_ENTRY_FIELDS; i++) { 820 *ds = *sr; 821 ds++; 822 sr++; 823 } 824} 825 826/** 827 * \brief Copy the user specified PaRAM Set onto the PaRAM Set associated 828 * with the logical channel (DMA/Link). 829 * 830 * This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set 831 * associated with the logical channel. OPT field of the PaRAM Set is written 832 * first and the CCNT field is written last. 833 * 834 * 835 * \param baseAdd Memory address of the EDMA instance used.\n 836 * 837 * \param chNum Logical Channel whose PaRAM set is 838 * requested.\n 839 * 840 * \param newPaRAM Parameter RAM set to be copied onto existing 841 * PaRAM.\n 842 * 843 * \return None 844 */ 845void EDMA3SetPaRAM(unsigned int baseAdd, 846 unsigned int chNum, 847 EDMA3CCPaRAMEntry* newPaRAM) 848{ 849 unsigned int PaRAMId = chNum; /* PaRAM mapped to channel Number */ 850 unsigned int i = 0; 851 unsigned int *sr = (unsigned int *)newPaRAM; 852 volatile unsigned int *ds; 853 854 ds = (unsigned int *)(baseAdd + EDMA3CC_OPT(PaRAMId)); 855 856 for (i = 0; i < EDMA3CC_PARAM_ENTRY_FIELDS; i++) { 857 *ds = *sr; 858 ds++; 859 sr++; 860 } 861} 862 863/** 864 * \brief Copy the user specified PaRAM Set onto the PaRAM Set associated 865 * with the logical channel (QDMA only). 866 * 867 * This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set 868 * associated with the logical channel. OPT field of the PaRAM Set is written 869 * first and the CCNT field is written last. 870 * 871 * 872 * \param baseAdd Memory address of the EDMA instance used.\n 873 * 874 * \param chNum Logical Channel whose PaRAM set is 875 * requested.\n 876 * 877 * \param paRaMID PaRAM Id to which the QDMA channel is 878 * mapped to. 879 * 880 * \param newPaRAM Parameter RAM set to be copied onto existing 881 * PaRAM.\n 882 * 883 * \return None 884 */ 885void EDMA3QdmaSetPaRAM(unsigned int baseAdd, 886 UNUSED unsigned int chNum, 887 unsigned int paRAMId, 888 EDMA3CCPaRAMEntry* newPaRAM) 889{ 890 unsigned int i = 0; 891 unsigned int *sr = (unsigned int *)newPaRAM; 892 unsigned int *ds; 893 894 ds = (unsigned int *)(baseAdd + EDMA3CC_OPT(paRAMId)); 895 896 for (i = 0; i < EDMA3CC_PARAM_ENTRY_FIELDS; i++) { 897 *ds = *sr; 898 ds++; 899 sr++; 900 } 901} 902 903/** 904 * \brief Set a particular PaRAM set entry of the specified PaRAM set 905 * 906 * \param baseAdd Memory address of the EDMA instance used.\n 907 * 908 * \param paRaMID PaRAM Id to which the QDMA channel is 909 * mapped to. 910 * 911 * \param paRAMEntry Specify the PaRAM set entry which needs 912 * to be set. 913 * 914 * \param newPaRAMEntryVal The new field setting. Make sure this field is 915 * packed for setting certain fields in paRAM. 916 * 917 * paRAMEntry can have values: 918 * 919 * EDMA3CC_PARAM_ENTRY_OPT 920 * EDMA3CC_PARAM_ENTRY_SRC 921 * EDMA3CC_PARAM_ENTRY_ACNT_BCNT 922 * EDMA3CC_PARAM_ENTRY_DST 923 * EDMA3CC_PARAM_ENTRY_SRC_DST_BIDX 924 * EDMA3CC_PARAM_ENTRY_LINK_BCNTRLD 925 * EDMA3CC_PARAM_ENTRY_SRC_DST_CIDX 926 * EDMA3CC_PARAM_ENTRY_CCNT 927 * 928 * \return None 929 * 930 * \note This API should be used while setting the PaRAM set entry 931 * for QDMA channels. If EDMA3QdmaSetPaRAMEntry() used, 932 * it will trigger the QDMA channel before complete 933 * PaRAM set entry is written. 934 */ 935void EDMA3QdmaSetPaRAMEntry(unsigned int baseAdd, 936 unsigned int paRAMId, 937 unsigned int paRAMEntry, 938 unsigned int newPaRAMEntryVal) 939{ 940 if ((paRAMEntry > EDMA3CC_PARAM_ENTRY_OPT) || 941 (paRAMEntry < EDMA3CC_PARAM_ENTRY_CCNT)) { 942 HWREG(baseAdd + EDMA3CC_OPT(paRAMId) + 943 (unsigned int)(paRAMEntry * 0x04)) = newPaRAMEntryVal; 944 } 945} 946 947/** 948 * \brief Get a particular PaRAM entry of the specified PaRAM set 949 * 950 * \param baseAdd Memory address of the EDMA instance used.\n 951 * 952 * \param paRaMID PaRAM Id to which the QDMA channel is 953 * mapped to. 954 * 955 * \param paRAMEntry Specify the PaRAM set entry which needs 956 * to be read. 957 * 958 * paRAMEntry can have values: 959 * 960 * EDMA3CC_PARAM_ENTRY_OPT 961 * EDMA3CC_PARAM_ENTRY_SRC 962 * EDMA3CC_PARAM_ENTRY_ACNT_BCNT 963 * EDMA3CC_PARAM_ENTRY_DST 964 * EDMA3CC_PARAM_ENTRY_SRC_DST_BIDX 965 * EDMA3CC_PARAM_ENTRY_LINK_BCNTRLD 966 * EDMA3CC_PARAM_ENTRY_SRC_DST_CIDX 967 * EDMA3CC_PARAM_ENTRY_CCNT 968 * 969 * \return paRAMEntryVal The value of the paRAM field pointed by the 970 * paRAMEntry. 971 * 972 * \note This API should be used while reading the PaRAM set entry 973 * for QDMA channels. And the paRAMEntryVal is a packed value for 974 * certain fields of paRAMEntry.The user has to make sure the value 975 * is unpacked appropriately. 976 * For example, the third field is A_B_CNT. Hence he will have to 977 * unpack it to two 16 bit fields to get ACNT and BCNT. 978 */ 979unsigned int EDMA3QdmaGetPaRAMEntry(unsigned int baseAdd, 980 unsigned int paRAMId, 981 unsigned int paRAMEntry) 982{ 983 unsigned int paRAMEntryVal = 0; 984 if ((paRAMEntry > EDMA3CC_PARAM_ENTRY_OPT) || 985 (paRAMEntry < EDMA3CC_PARAM_ENTRY_CCNT)) { 986 paRAMEntryVal = HWREG(baseAdd + EDMA3CC_OPT(paRAMId) + 987 (unsigned int)(paRAMEntry * 0x04)); 988 } 989 return(paRAMEntryVal); 990} 991 992/** 993 * \brief Request a DMA/QDMA/Link channel. 994 * 995 * Each channel (DMA/QDMA/Link) must be requested before initiating a DMA 996 * transfer on that channel. 997 * 998 * This API is used to allocate a logical channel (DMA/QDMA/Link) along with 999 * the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are 1000 * also allocated along with the requested channel. 1001 * 1002 * User can request a specific logical channel by passing the channel number 1003 * in 'chNum'. 1004 * 1005 * For DMA/QDMA channels, after allocating all the EDMA3 resources, this API 1006 * sets the TCC field of the OPT PaRAM Word with the allocated TCC. It also sets 1007 * the event queue for the channel allocated. The event queue needs to be 1008 * specified by the user. 1009 * 1010 * For DMA channel, it also sets the DCHMAP register. 1011 * 1012 * For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and 1013 * enables the QDMA channel by writing to the QEESR register. 1014 * 1015 * \param baseAdd Memory address of the EDMA instance used.\n 1016 * 1017 * \param chtype (DMA/QDMA) Channel 1018 * For Example: For DMA it is 1019 * EDMA3_CHANNEL_TYPE_DMA.\n 1020 * 1021 * \param chNum This is the channel number requested for a 1022 * particular event.\n 1023 * 1024 * \param tccNum The channel number on which the 1025 * completion/error interrupt is generated. 1026 * Not used if user requested for a Link 1027 * channel.\n 1028 * 1029 * \param evtQNum Event Queue Number to which the channel 1030 * will be mapped (valid only for the 1031 * Master Channel (DMA/QDMA) request).\n 1032 * 1033 * \return TRUE if parameters are valid, else FALSE 1034 */ 1035unsigned int EDMA3RequestChannel(unsigned int baseAdd, 1036 unsigned int chType, 1037 unsigned int chNum, 1038 unsigned int tccNum, 1039 unsigned int evtQNum) 1040{ 1041 unsigned int retVal = FALSE; 1042 if (chNum < SOC_EDMA3_NUM_DMACH) { 1043 /* Enable the DMA channel in the enabled in the shadow region 1044 * specific register 1045 */ 1046 EDMA3EnableChInShadowReg(baseAdd, chType, chNum); 1047 1048 EDMA3MapChToEvtQ( baseAdd, chType, chNum, evtQNum); 1049 if (EDMA3_CHANNEL_TYPE_DMA == chType) { 1050 /* Interrupt channel nums are < 32 */ 1051 if (tccNum < SOC_EDMA3_NUM_DMACH) { 1052 /* Enable the Event Interrupt */ 1053 EDMA3EnableEvtIntr(baseAdd, chNum); 1054 retVal = TRUE; 1055 } 1056 HWREG(baseAdd + EDMA3CC_OPT(chNum)) &= EDMA3CC_OPT_TCC_CLR; 1057 HWREG(baseAdd + EDMA3CC_OPT(chNum)) |= EDMA3CC_OPT_TCC_SET(chNum); 1058 } else if (EDMA3_CHANNEL_TYPE_QDMA == chType) { 1059 /* Interrupt channel nums are < 8 */ 1060 if (tccNum < SOC_EDMA3_NUM_QDMACH) { 1061 /* Enable the Event Interrupt */ 1062 EDMA3EnableEvtIntr(baseAdd, chNum); 1063 retVal = TRUE; 1064 } 1065 HWREG(baseAdd + EDMA3CC_OPT(chNum)) &= EDMA3CC_OPT_TCC_CLR; 1066 HWREG(baseAdd + EDMA3CC_OPT(chNum)) |= EDMA3CC_OPT_TCC_SET(chNum); 1067 } 1068 } 1069 return retVal; 1070} 1071 1072/** 1073 * \brief Free the specified channel (DMA/QDMA/Link) and its associated 1074 * resources (PaRAM Set, TCC etc) and removes various mappings. 1075 * 1076 * For Link channels, this API only frees the associated PaRAM Set. 1077 * 1078 * For DMA/QDMA channels, it does the following operations: 1079 * 1) Disable any ongoing transfer on the channel,\n 1080 * 2) Remove the channel to Event Queue mapping,\n 1081 * 3) For DMA channels, clear the DCHMAP register, if available\n 1082 * 4) For QDMA channels, clear the QCHMAP register,\n 1083 * 5) Frees the DMA/QDMA channel in the end.\n 1084 * 1085 * \param baseAdd Memory address of the EDMA instance used.\n 1086 * 1087 * \param chtype (DMA/QDMA) Channel 1088 * For Example: For QDMA it is, 1089 * EDMA3_CHANNEL_TYPE_QDMA.\n 1090 * 1091 * \param chNum This is the channel number requested for a 1092 * particular event.\n 1093 * 1094 * \param trigMode Mode of triggering start of transfer.\n 1095 * 1096 * \param tccNum The channel number on which the 1097 * completion/error interrupt is generated. 1098 * Not used if user requested for a Link 1099 * channel.\n 1100 * 1101 * \param evtQNum Event Queue Number to which the channel 1102 * will be unmapped (valid only for the 1103 * Master Channel (DMA/QDMA) request).\n 1104 * 1105 * trigMode can have values: 1106 * EDMA3_TRIG_MODE_MANUAL\n 1107 * EDMA3_TRIG_MODE_QDMA\n 1108 * EDMA3_TRIG_MODE_EVENT 1109 * 1110 * \return TRUE if parameters are valid else return FALSE 1111 */ 1112unsigned int EDMA3FreeChannel(unsigned int baseAdd, unsigned int chType, 1113 unsigned int chNum, unsigned int trigMode, 1114 unsigned int tccNum, UNUSED unsigned int evtQNum) 1115{ 1116 unsigned int retVal = FALSE; 1117 if (chNum < SOC_EDMA3_NUM_DMACH) { 1118 EDMA3DisableTransfer(baseAdd, chNum, trigMode); 1119 /* Disable the DMA channel in the shadow region specific register 1120 */ 1121 EDMA3DisableChInShadowReg(baseAdd, chType, chNum); 1122 1123 EDMA3UnmapChToEvtQ( baseAdd, chType, chNum); 1124 if (EDMA3_CHANNEL_TYPE_DMA == chType) { 1125 /* Interrupt channel nums are < 32 */ 1126 if (tccNum < SOC_EDMA3_NUM_DMACH) { 1127 /* Disable the DMA Event Interrupt */ 1128 EDMA3DisableEvtIntr(baseAdd, chNum); 1129 retVal = TRUE; 1130 } 1131 } else if (EDMA3_CHANNEL_TYPE_QDMA == chType) { 1132 /* Interrupt channel nums are < 8 */ 1133 if (tccNum < SOC_EDMA3_NUM_QDMACH) { 1134 /* Disable the QDMA Event Interrupt */ 1135 EDMA3DisableEvtIntr(baseAdd, chNum); 1136 retVal = TRUE; 1137 } 1138 } 1139 } 1140 return retVal; 1141} 1142 1143/** 1144 * \brief Start EDMA transfer on the specified channel. 1145 * 1146 * There are multiple ways to trigger an EDMA3 transfer. The triggering mode 1147 * option allows choosing from the available triggering modes: Event, 1148 * Manual or QDMA. 1149 * 1150 * In event triggered, a peripheral or an externally generated event triggers 1151 * the transfer. This API clears the Event and Event Miss Register and then 1152 * enables the DMA channel by writing to the EESR. 1153 * 1154 * In manual triggered mode, CPU manually triggers a transfer by writing a 1 1155 * in the Event Set Register ESR. This API writes to the ESR to start the 1156 * transfer. 1157 * 1158 * In QDMA triggered mode, a QDMA transfer is triggered when a CPU (or other 1159 * EDMA3 programmer) writes to the trigger word of the QDMA channel PaRAM set 1160 * (auto-triggered) or when the EDMA3CC performs a link update on a PaRAM set 1161 * that has been mapped to a QDMA channel (link triggered). This API enables 1162 * the QDMA channel by writing to the QEESR register. 1163 * 1164 * \param baseAdd Memory address of the EDMA instance used.\n 1165 * 1166 * \param chNum Channel being used to enable transfer.\n 1167 * 1168 * \param trigMode Mode of triggering start of transfer (Manual, 1169 * QDMA or Event).\n 1170 * 1171 * trigMode can have values: 1172 * EDMA3_TRIG_MODE_MANUAL\n 1173 * EDMA3_TRIG_MODE_QDMA\n 1174 * EDMA3_TRIG_MODE_EVENT\n 1175 * 1176 * \return retVal TRUE or FALSE depending on the param passed.\n 1177 * 1178 */ 1179unsigned int EDMA3EnableTransfer(unsigned int baseAdd, 1180 unsigned int chNum, 1181 unsigned int trigMode) 1182{ 1183 unsigned int retVal = FALSE; 1184 switch (trigMode) { 1185 case EDMA3_TRIG_MODE_MANUAL : 1186 if (chNum < SOC_EDMA3_NUM_DMACH) { 1187 EDMA3SetEvt(baseAdd, chNum); 1188 retVal = TRUE; 1189 } 1190 break; 1191 1192 case EDMA3_TRIG_MODE_QDMA : 1193 if (chNum < SOC_EDMA3_NUM_QDMACH) { 1194 EDMA3EnableQdmaEvt(baseAdd, chNum); 1195 retVal = TRUE; 1196 } 1197 break; 1198 1199 case EDMA3_TRIG_MODE_EVENT : 1200 if (chNum < SOC_EDMA3_NUM_DMACH) { 1201 /*clear SECR & EMCR to clean any previous NULL request */ 1202 EDMA3ClrMissEvt(baseAdd, chNum); 1203 1204 /* Set EESR to enable event */ 1205 EDMA3EnableDmaEvt(baseAdd, chNum); 1206 retVal = TRUE; 1207 } 1208 break; 1209 1210 default : 1211 retVal = FALSE; 1212 break; 1213 } 1214 return retVal; 1215} 1216 1217/** 1218 * \brief Disable DMA transfer on the specified channel 1219 * 1220 * There are multiple ways by which an EDMA3 transfer could be triggered. 1221 * The triggering mode option allows choosing from the available triggering 1222 * modes. 1223 * 1224 * To disable a channel which was previously triggered in manual mode, 1225 * this API clears the Secondary Event Register and Event Miss Register, 1226 * if set, for the specific DMA channel. 1227 * 1228 * To disable a channel which was previously triggered in QDMA mode, this 1229 * API clears the QDMA Event Enable Register, for the specific QDMA channel. 1230 * 1231 * To disable a channel which was previously triggered in event mode, this API 1232 * clears the Event Enable Register, Event Register, Secondary Event Register 1233 * and Event Miss Register, if set, for the specific DMA channel. 1234 * 1235 * 1236 * \param baseAdd Memory address of the EDMA instance used.\n 1237 * 1238 * \param chNum Channel being used to enable transfer.\n 1239 * 1240 * \param trigMode Mode of triggering start of transfer (Manual, 1241 * QDMA or Event).\n 1242 * 1243 * trigMode can have values: 1244 * EDMA3_TRIG_MODE_MANUAL 1245 * EDMA3_TRIG_MODE_QDMA 1246 * EDMA3_TRIG_MODE_EVENT 1247 * 1248 * \return retVal TRUE or FALSE depending on the param passed.\n 1249 * 1250 */ 1251unsigned int EDMA3DisableTransfer(unsigned int baseAdd, 1252 unsigned int chNum, 1253 unsigned int trigMode) 1254{ 1255 unsigned int retVal = FALSE; 1256 switch (trigMode) { 1257 case EDMA3_TRIG_MODE_MANUAL : 1258 if (chNum < SOC_EDMA3_NUM_DMACH) { 1259 EDMA3ClrEvt(baseAdd, chNum); 1260 retVal = TRUE; 1261 } 1262 break; 1263 1264 case EDMA3_TRIG_MODE_QDMA : 1265 if (chNum < SOC_EDMA3_NUM_QDMACH) { 1266 EDMA3DisableQdmaEvt(baseAdd, chNum); 1267 retVal = TRUE; 1268 } 1269 break; 1270 1271 case EDMA3_TRIG_MODE_EVENT : 1272 if (chNum < SOC_EDMA3_NUM_DMACH) { 1273 /*clear SECR & EMCR to clean any previous NULL request */ 1274 EDMA3ClrMissEvt(baseAdd, chNum); 1275 1276 /* Set EESR to enable event */ 1277 EDMA3DisableDmaEvt(baseAdd, chNum); 1278 retVal = TRUE; 1279 } 1280 break; 1281 1282 default : 1283 retVal = FALSE; 1284 break; 1285 } 1286 return retVal; 1287} 1288 1289/** 1290 * \brief Clears Event Register and Error Register for a specific 1291 * DMA channel and brings back EDMA3 to its initial state. 1292 * 1293 * This API clears the Event register, Event Miss register, Event Enable 1294 * register for a specific DMA channel. It also clears the CC Error register. 1295 * 1296 * \param baseAdd Memory address of the EDMA instance used.\n 1297 * 1298 * \param chNum This is the channel number requested for a 1299 * particular event.\n 1300 * 1301 * \param evtQNum Event Queue Number to which the channel 1302 * will be unmapped (valid only for the 1303 * Master Channel (DMA/QDMA) request).\n 1304 * 1305 * \return none.\n 1306 */ 1307void EDMA3ClearErrorBits(unsigned int baseAdd, 1308 unsigned int chNum, 1309 unsigned int evtQNum) 1310{ 1311 if (chNum < SOC_EDMA3_NUM_DMACH) { 1312 if (chNum < 32) { 1313 HWREG(baseAdd + EDMA3CC_S_EECR(regionId)) = (0x01u << chNum); 1314 /* Write to EMCR to clear the corresponding EMR bit */ 1315 HWREG(baseAdd + EDMA3CC_EMCR) = (0x01u << chNum); 1316 /* Clears the SER */ 1317 HWREG(baseAdd + EDMA3CC_S_SECR(regionId)) = (0x01u << chNum); 1318 } else { 1319 HWREG(baseAdd + EDMA3CC_S_EECRH(regionId)) = (0x01u << (chNum - 32)); 1320 /* Write to EMCR to clear the corresponding EMR bit */ 1321 HWREG(baseAdd + EDMA3CC_EMCRH) = (0x01u << (chNum - 32)); 1322 /* Clears the SER */ 1323 HWREG(baseAdd + EDMA3CC_S_SECRH(regionId)) = (0x01u << (chNum - 32)); 1324 } 1325 1326 } 1327 1328 /* Clear the global CC Error Register */ 1329 if (0 == evtQNum) { 1330 HWREG(baseAdd + EDMA3CC_CCERRCLR) &= (EDMA3CC_CCERRCLR_QTHRXCD0 | 1331 EDMA3CC_CCERRCLR_TCCERR); 1332 } else if (1 == evtQNum) { 1333 HWREG(baseAdd + EDMA3CC_CCERRCLR) &= (EDMA3CC_CCERRCLR_QTHRXCD1 | 1334 EDMA3CC_CCERRCLR_TCCERR); 1335 } else if (2 == evtQNum) { 1336 HWREG(baseAdd + EDMA3CC_CCERRCLR) &= (EDMA3CC_CCERRCLR_QTHRXCD2 | 1337 EDMA3CC_CCERRCLR_TCCERR); 1338 } else if (3 == evtQNum) { 1339 HWREG(baseAdd + EDMA3CC_CCERRCLR) &= (EDMA3CC_CCERRCLR_QTHRXCD2 | 1340 EDMA3CC_CCERRCLR_TCCERR); 1341 } 1342} 1343 1344/** 1345 * \brief EDMA3 Deinitialization 1346 * 1347 * This function deinitializes the EDMA3 Driver 1348 * Clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR) & 1349 * deinitialize the Queue Number Registers 1350 * 1351 * \param baseAdd Memory address of the EDMA instance used.\n 1352 * 1353 * \param queNum Event Queue used 1354 * 1355 * \return None 1356 * 1357 * \note The regionId is the shadow region(0 or 1) used and the, 1358 * Event Queue used is either (0 or 1). There are only two shadow regions 1359 * and only two event Queues 1360 */ 1361void EDMA3Deinit(unsigned int baseAdd, 1362 UNUSED unsigned int queNum) 1363{ 1364 unsigned int count = 0; 1365 1366 /* Disable the DMA (0 - 62) channels in the DRAE register */ 1367 HWREG(baseAdd + EDMA3CC_DRAE(regionId)) = EDMA3_CLR_ALL_BITS; 1368 HWREG(baseAdd + EDMA3CC_DRAEH(regionId)) = EDMA3_CLR_ALL_BITS; 1369 1370 EDMA3ClrCCErr(baseAdd, EDMA3CC_CLR_TCCERR); 1371 1372 /* Clear the Event miss Registers */ 1373 HWREG(baseAdd + EDMA3CC_EMCR) = EDMA3_SET_ALL_BITS; 1374 HWREG(baseAdd + EDMA3CC_EMCRH) = EDMA3_SET_ALL_BITS; 1375 1376 /* Clear CCERR register */ 1377 HWREG(baseAdd + EDMA3CC_CCERRCLR) = EDMA3_SET_ALL_BITS; 1378 1379 /* Deinitialize the Queue Number Registers */ 1380 for (count = 0; count < SOC_EDMA3_NUM_DMACH; count++) { 1381 HWREG(baseAdd + EDMA3CC_DMAQNUM(count >> 3u)) &= EDMA3CC_DMAQNUM_CLR(count); 1382 } 1383 1384 for (count = 0; count < SOC_EDMA3_NUM_QDMACH; count++) { 1385 HWREG(baseAdd + EDMA3CC_QDMAQNUM) &= EDMA3CC_QDMAQNUM_CLR(count); 1386 } 1387} 1388 1389/** 1390 * \brief This API can be used to save the register context for EDMA 1391 * 1392 * \param baseAdd Memory address of the EDMA instance used.\n 1393 * 1394 * \param edmaCntxPtr Pointer to the structure where the context 1395 * needs to be saved. 1396 * 1397 * \return None 1398 */ 1399void EDMA3ContextSave(unsigned int baseAddr, EDMACONTEXT *edmaCntxPtr) 1400{ 1401 unsigned int i; 1402 unsigned int maxPar; 1403 1404 /* Get the Channel mapping reg Val */ 1405 1406 for (i = 0; i < 64; i++) { 1407 /* All events are one to one mapped with the channels */ 1408 edmaCntxPtr->dchMap[i] = HWREG(baseAddr + EDMA3CC_DCHMAP(i)); 1409 } 1410 1411 /* Get DMA Queue Number Register Val */ 1412 for (i = 0; i < 8; i++) { 1413 edmaCntxPtr->dmaQNum[i] = HWREG(baseAddr + EDMA3CC_DMAQNUM((i))); 1414 } 1415 1416 /* Get the DMA Region Access Enable Register val */ 1417 1418 edmaCntxPtr->regAccEnableLow = HWREG(baseAddr + EDMA3CC_DRAE(0)); 1419 edmaCntxPtr->regAccEnableHigh = HWREG(baseAddr + EDMA3CC_DRAEH(0)); 1420 1421 /* Get Event Set Register value */ 1422 1423 edmaCntxPtr->eventSetRegLow = HWREG(baseAddr + EDMA3CC_S_ESR(0)); 1424 edmaCntxPtr->eventSetRegHigh = HWREG(baseAddr + EDMA3CC_S_ESRH(0)); 1425 1426 /* Get Event Enable Set Register value */ 1427 1428 edmaCntxPtr->enableEvtSetRegLow = HWREG(baseAddr + EDMA3CC_S_EER(0)); 1429 edmaCntxPtr->enableEvtSetRegHigh = HWREG(baseAddr + EDMA3CC_S_EERH(0)); 1430 1431 /* Get Interrupt Enable Set Register value */ 1432 1433 edmaCntxPtr->intEnableSetRegLow = HWREG(baseAddr + EDMA3CC_S_IER(0)); 1434 edmaCntxPtr->intEnableSetRegHigh = HWREG(baseAddr + EDMA3CC_S_IERH(0)); 1435 1436 maxPar = 128; 1437 1438 if ((EDMA_REVID_AM335X == EDMAVersionGet())) { 1439 maxPar = 256; 1440 } 1441 1442 for (i = 0; i < maxPar; i++) { 1443 /* Get the PaRAM values */ 1444 EDMA3GetPaRAM(baseAddr, i, 1445 (struct EDMA3CCPaRAMEntry *)(&(edmaCntxPtr->dmaParEntry[i]))); 1446 } 1447} 1448 1449/** 1450 * \brief This API can be used to restore the register context for EDMA 1451 * 1452 * \param baseAdd Memory address of the EDMA instance used.\n 1453 * 1454 * \param edmaCntxPtr Pointer to the structure where the context 1455 * needs to be restored from. 1456 * 1457 * \return None 1458 */ 1459void EDMA3ContextRestore(unsigned int baseAddr, EDMACONTEXT *edmaCntxPtr) 1460{ 1461 unsigned int i; 1462 unsigned int maxPar; 1463 1464 /* set the Channel mapping reg Val */ 1465 for (i = 0; i < 64; i++) { 1466 /* All events are one to one mapped with the channels */ 1467 HWREG(baseAddr + EDMA3CC_DCHMAP(i)) = edmaCntxPtr->dchMap[i] ; 1468 } 1469 1470 /* set DMA Queue Number Register Val */ 1471 for (i = 0; i < 8; i++) { 1472 HWREG(baseAddr + EDMA3CC_DMAQNUM((i))) = edmaCntxPtr->dmaQNum[i]; 1473 } 1474 1475 /* set the DMA Region Access Enable Register val */ 1476 1477 HWREG(baseAddr + EDMA3CC_DRAE(0)) = edmaCntxPtr->regAccEnableLow; 1478 HWREG(baseAddr + EDMA3CC_DRAEH(0)) = edmaCntxPtr->regAccEnableHigh; 1479 1480 /* set Event Set Register value */ 1481 HWREG(baseAddr + EDMA3CC_S_ESR(0)) = edmaCntxPtr->eventSetRegLow; 1482 HWREG(baseAddr + EDMA3CC_S_ESRH(0)) = edmaCntxPtr->eventSetRegHigh; 1483 1484 /* set Event Enable Set Register value */ 1485 HWREG(baseAddr + EDMA3CC_S_EESR(0)) = edmaCntxPtr->enableEvtSetRegLow; 1486 HWREG(baseAddr + EDMA3CC_S_EESRH(0)) = edmaCntxPtr->enableEvtSetRegHigh; 1487 1488 /* set Interrupt Enable Set Register value */ 1489 HWREG(baseAddr + EDMA3CC_S_IESR(0)) = edmaCntxPtr->intEnableSetRegLow; 1490 HWREG(baseAddr + EDMA3CC_S_IESRH(0)) = edmaCntxPtr->intEnableSetRegHigh; 1491 1492 maxPar = 128; 1493 1494 if ((EDMA_REVID_AM335X == EDMAVersionGet())) { 1495 maxPar = 256; 1496 } 1497 1498 for (i = 0; i < maxPar; i++) { 1499 /* Get the PaRAM values */ 1500 EDMA3SetPaRAM(baseAddr, i, 1501 (struct EDMA3CCPaRAMEntry *)(&(edmaCntxPtr->dmaParEntry[i]))); 1502 } 1503} 1504 1505/********************************* End of file ******************************/ 1506