1/* @TAG(CUSTOM) *//** 2 * \file edma.h 3 * 4 * \brief This file contains the function prototypes for the device 5 * abstraction layer for EDMA. It also contains some 6 * related macro definitions and some files to be included. 7 */ 8 9/* 10* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 11*/ 12/* 13* Redistribution and use in source and binary forms, with or without 14* modification, are permitted provided that the following conditions 15* are met: 16* 17* Redistributions of source code must retain the above copyright 18* notice, this list of conditions and the following disclaimer. 19* 20* Redistributions in binary form must reproduce the above copyright 21* notice, this list of conditions and the following disclaimer in the 22* documentation and/or other materials provided with the 23* distribution. 24* 25* Neither the name of Texas Instruments Incorporated nor the names of 26* its contributors may be used to endorse or promote products derived 27* from this software without specific prior written permission. 28* 29* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40* 41*/ 42 43#pragma once 44 45#define am335x 1 46 47#include <stdio.h> 48#include <stdlib.h> 49#include "hw/hw_edma3cc.h" 50#include "hw/hw_edma3tc.h" 51 52#ifdef __cplusplus 53extern "C" { 54#endif 55//*********************************************************************** 56// Values that can be used by the application for configuration via APIs 57//***********************************************************************/ 58 59 /** Maximum number of EDMA Shadow regions available */ 60#define EDMA3_MAX_REGIONS (2u) 61 62 /** Number of PaRAM Sets available */ 63#define EDMA3_NUM_PARAMSET (128u) 64 65 /** Number of Event Queues available */ 66#define EDMA3_0_NUM_EVTQUE (2u) 67 68 /** Number of Transfer Controllers available */ 69#define EDMA3_0_NUM_TC (2u) 70 71 /** Interrupt no. for Transfer Completion */ 72#define EDMA3_0_CC_XFER_COMPLETION_INT (11u) 73 74 /** Interrupt no. for CC Error */ 75#define EDMA3_0_CC0_ERRINT (12u) 76 77 /** Interrupt no. for TCs Error */ 78#define EDMA3_0_TC0_ERRINT (13u) 79#define EDMA3_0_TC1_ERRINT (32u) 80 81#define EDMA3CC_DMA_CHANNELS (32u) 82#define EDMA3CC_QDMA_CHANNELS (8u) 83 84 /** DMAQNUM bits Clear */ 85#define EDMA3CC_DMAQNUM_CLR(chNum) ( ~ (0x7u << (((chNum) % 8u) \ 86 * 4u))) 87 /** DMAQNUM bits Set */ 88#define EDMA3CC_DMAQNUM_SET(chNum,queNum) ((0x7u & (queNum)) << \ 89 (((chNum) % 8u) * 4u)) 90 /** QDMAQNUM bits Clear */ 91#define EDMA3CC_QDMAQNUM_CLR(chNum) ( ~ (0x7u << ((chNum) * 4u))) 92 /** QDMAQNUM bits Set */ 93#define EDMA3CC_QDMAQNUM_SET(chNum,queNum) ((0x7u & (queNum)) << \ 94 ((chNum) * 4u)) 95 96#define EDMA3CC_QCHMAP_PAENTRY_CLR (~EDMA3CC_QCHMAP_PAENTRY) 97 /** QCHMAP-PaRAMEntry bitfield Set */ 98#define EDMA3CC_QCHMAP_PAENTRY_SET(paRAMId) (((EDMA3CC_QCHMAP_PAENTRY >> \ 99 EDMA3CC_QCHMAP_PAENTRY_SHIFT) & \ 100 (paRAMId)) << \ 101 EDMA3CC_QCHMAP_PAENTRY_SHIFT) 102 /** QCHMAP-TrigWord bitfield Clear */ 103#define EDMA3CC_QCHMAP_TRWORD_CLR (~EDMA3CC_QCHMAP_TRWORD) 104 /** QCHMAP-TrigWord bitfield Set */ 105#define EDMA3CC_QCHMAP_TRWORD_SET(paRAMId) (((EDMA3CC_QCHMAP_TRWORD >> \ 106 EDMA3CC_QCHMAP_TRWORD_SHIFT) & \ 107 (paRAMId)) << \ 108 EDMA3CC_QCHMAP_TRWORD_SHIFT) 109 110 /** OPT-TCC bitfield Clear */ 111#define EDMA3CC_OPT_TCC_CLR (~EDMA3CC_OPT_TCC) 112 113 /** OPT-TCC bitfield Set */ 114#define EDMA3CC_OPT_TCC_SET(tcc) (((EDMA3CC_OPT_TCC >> \ 115 EDMA3CC_OPT_TCC_SHIFT) & \ 116 (tcc)) << EDMA3CC_OPT_TCC_SHIFT) 117 118#define EDMA3_SET_ALL_BITS (0xFFFFFFFFu) 119#define EDMA3_CLR_ALL_BITS (0x00000000u) 120 121#define EDMA3CC_COMPL_HANDLER_RETRY_COUNT (10u) 122#define EDMA3CC_ERR_HANDLER_RETRY_COUNT (10u) 123 124#define EDMA3_TRIG_MODE_MANUAL (0u) 125#define EDMA3_TRIG_MODE_QDMA (1u) 126#define EDMA3_TRIG_MODE_EVENT (2u) 127 128#define EDMA3_CHANNEL_TYPE_DMA (0u) 129#define EDMA3_CHANNEL_TYPE_QDMA (1u) 130 131#define EDMA3_XFER_COMPLETE (0u) 132#define EDMA3_CC_DMA_EVT_MISS (1u) 133#define EDMA3_CC_QDMA_EVT_MISS (2u) 134 135#define EDMA3_SYNC_A (0u) 136#define EDMA3_SYNC_AB (1u) 137 138#define EDMA3CC_CLR_TCCERR EDMA3CC_CCERRCLR_TCCERR 139#define EDMA3CC_CLR_QTHRQ0 EDMA3CC_CCERRCLR_QTHRXCD0 140#define EDMA3CC_CLR_QTHRQ1 EDMA3CC_CCERRCLR_QTHRXCD1 141 142 /* paRAMEntry Fields*/ 143 /** 144 * The OPT field (Offset Address 0x0 Bytes) 145 */ 146#define EDMA3CC_PARAM_ENTRY_OPT (0x0u) 147 148 /** 149 * The SRC field (Offset Address 0x4 Bytes) 150 */ 151#define EDMA3CC_PARAM_ENTRY_SRC (0x1u) 152 153 /** 154 * The (ACNT+BCNT) field (Offset Address 0x8 Bytes) 155 */ 156#define EDMA3CC_PARAM_ENTRY_ACNT_BCNT (0x2u) 157 158 /** 159 * The DST field (Offset Address 0xC Bytes) 160 */ 161#define EDMA3CC_PARAM_ENTRY_DST (0x3u) 162 163 /** 164 * The (SRCBIDX+DSTBIDX) field (Offset Address 0x10 Bytes) 165 */ 166#define EDMA3CC_PARAM_ENTRY_SRC_DST_BIDX (0x4u) 167 168 /** 169 * The (LINK+BCNTRLD) field (Offset Address 0x14 Bytes) 170 */ 171#define EDMA3CC_PARAM_ENTRY_LINK_BCNTRLD (0x5u) 172 173 /** 174 * The (SRCCIDX+DSTCIDX) field (Offset Address 0x18 Bytes) 175 */ 176#define EDMA3CC_PARAM_ENTRY_SRC_DST_CIDX (0x6u) 177 178 /** 179 * The (CCNT+RSVD) field (Offset Address 0x1C Bytes) 180 */ 181#define EDMA3CC_PARAM_ENTRY_CCNT (0x7u) 182 183 /** The offset for each PaRAM Entry field */ 184#define EDMA3CC_PARAM_FIELD_OFFSET (0x4u) 185 186 /** Number of PaRAM Entry fields 187 * OPT, SRC, A_B_CNT, DST, SRC_DST_BIDX, LINK_BCNTRLD, SRC_DST_CIDX 188 * and CCNT 189 */ 190#define EDMA3CC_PARAM_ENTRY_FIELDS (0x8u) 191 192#define EDMA_REVID_AM335X (0x02u) 193 194#if defined(am335x) || defined(am335x_13x13) || defined(am335x_15x15) || \ 195 defined(c6a811x) || defined(am386x) || defined(c6741x) 196#define SOC_EDMA3_NUM_DMACH 64 197#define SOC_EDMA3_NUM_QDMACH 8 198#define SOC_EDMA3_NUM_PARAMSETS 256 199#define SOC_EDMA3_NUM_EVQUE 4 200#define SOC_EDMA3_CHMAPEXIST 0 201#define SOC_EDMA3_NUM_REGIONS 8 202#define SOC_EDMA3_MEMPROTECT 0 203#endif 204 205#if defined(am1808) || defined(omapl138) || defined(c6748) 206#define SOC_EDMA3_NUM_DMACH 32 207#define SOC_EDMA3_NUM_QDMACH 8 208#define SOC_EDMA3_NUM_PARAMSETS 128 209#define SOC_EDMA3_NUM_EVQUE 2 210#define SOC_EDMA3_CHMAPEXIST 0 211#define SOC_EDMA3_NUM_REGIONS 4 212#define SOC_EDMA3_MEMPROTECT 0 213#endif 214 215 /** Number of TCCS available */ 216#define EDMA3_NUM_TCC SOC_EDMA3_NUM_DMACH 217 218 /** 219 * \brief EDMA3 Parameter RAM Set in User Configurable format 220 * 221 * This is a mapping of the EDMA3 PaRAM set provided to the user 222 * for ease of modification of the individual fields 223 */ 224 typedef struct EDMA3CCPaRAMEntry { 225 /** OPT field of PaRAM Set */ 226 unsigned int opt; 227 228 /** 229 * \brief Starting byte address of Source 230 * For FIFO mode, srcAddr must be a 256-bit aligned address. 231 */ 232 unsigned int srcAddr; 233 234 /** 235 * \brief Number of bytes in each Array (ACNT) 236 */ 237 unsigned short aCnt; 238 239 /** 240 * \brief Number of Arrays in each Frame (BCNT) 241 */ 242 unsigned short bCnt; 243 244 /** 245 * \brief Starting byte address of destination 246 * For FIFO mode, destAddr must be a 256-bit aligned address. 247 * i.e. 5 LSBs should be 0. 248 */ 249 unsigned int destAddr; 250 251 /** 252 * \brief Index between consec. arrays of a Source Frame (SRCBIDX) 253 */ 254 short srcBIdx; 255 256 /** 257 * \brief Index between consec. arrays of a Destination Frame (DSTBIDX) 258 */ 259 short destBIdx; 260 261 /** 262 * \brief Address for linking (AutoReloading of a PaRAM Set) 263 * This must point to a valid aligned 32-byte PaRAM set 264 * A value of 0xFFFF means no linking 265 */ 266 unsigned short linkAddr; 267 268 /** 269 * \brief Reload value of the numArrInFrame (BCNT) 270 * Relevant only for A-sync transfers 271 */ 272 unsigned short bCntReload; 273 274 /** 275 * \brief Index between consecutive frames of a Source Block (SRCCIDX) 276 */ 277 short srcCIdx; 278 279 /** 280 * \brief Index between consecutive frames of a Dest Block (DSTCIDX) 281 */ 282 short destCIdx; 283 284 /** 285 * \brief Number of Frames in a block (CCNT) 286 */ 287 unsigned short cCnt; 288 289 /** 290 * \brief This field is Reserved. Write zero to this field. 291 */ 292 unsigned short rsvd; 293 294 } EDMA3CCPaRAMEntry; 295 296 /* 297 ** Structure to store the EDMA context 298 */ 299 typedef struct edmaContext { 300 /* Channel mapping reg Val */ 301 unsigned int dchMap[64]; 302 /* DMA Queue Number Register Val */ 303 unsigned int dmaQNum[8]; 304 305 /* DMA Region Access Enable Register val */ 306 unsigned int regAccEnableLow; 307 unsigned int regAccEnableHigh; 308 309 /* Event Set Register value */ 310 unsigned int eventSetRegLow; 311 unsigned int eventSetRegHigh; 312 313 /* Enable Event Set Register value */ 314 unsigned int enableEvtSetRegLow; 315 unsigned int enableEvtSetRegHigh; 316 317 /* Interrupt Enable Set Register value */ 318 unsigned int intEnableSetRegLow; 319 unsigned int intEnableSetRegHigh; 320 321 struct EDMA3CCPaRAMEntry dmaParEntry[512]; 322 323 } EDMACONTEXT; 324 325 /**************************************************************************** 326 ** API FUNCTION PROTOTYPES 327 ****************************************************************************/ 328 329 void EDMA3Init(unsigned int baseAdd, 330 unsigned int queNum); 331 332 void EDMA3EnableChInShadowReg(unsigned int baseAdd, 333 unsigned int chType, 334 unsigned int chNum); 335 336 void EDMA3DisableChInShadowReg(unsigned int baseAdd, 337 unsigned int chType, 338 unsigned int chNum); 339 340 void EDMA3MapChToEvtQ(unsigned int baseAdd, 341 unsigned int chType, 342 unsigned int chNum, 343 unsigned int evtQNum); 344 345 void EDMA3UnmapChToEvtQ(unsigned int baseAdd, 346 unsigned int chType, 347 unsigned int chNum); 348 349 void EDMA3MapQdmaChToPaRAM(unsigned int baseAdd, 350 unsigned int chNum, 351 unsigned int *paRAMId); 352 353 void EDMA3SetQdmaTrigWord(unsigned int baseAdd, 354 unsigned int chNum, 355 unsigned int trigWord); 356 357 void EDMA3ClrMissEvt(unsigned int baseAdd, 358 unsigned int chNum); 359 360 void EDMA3QdmaClrMissEvt(unsigned int baseAdd, 361 unsigned int chNum); 362 363 void EDMA3ClrCCErr(unsigned int baseAdd, 364 unsigned int Flags); 365 366 void EDMA3SetEvt(unsigned int baseAdd, 367 unsigned int chNum); 368 369 void EDMA3ClrEvt(unsigned int baseAdd, 370 unsigned int chNum); 371 372 void EDMA3EnableDmaEvt(unsigned int baseAdd, 373 unsigned int chNum); 374 375 void EDMA3DisableDmaEvt(unsigned int baseAdd, 376 unsigned int chNum); 377 378 void EDMA3EnableQdmaEvt(unsigned int baseAdd, 379 unsigned int chNum); 380 381 void EDMA3DisableQdmaEvt(unsigned int baseAdd, 382 unsigned int chNum); 383 384 unsigned int EDMA3GetIntrStatus(unsigned int baseAdd); 385 386 void EDMA3EnableEvtIntr(unsigned int baseAdd, 387 unsigned int chNum); 388 389 void EDMA3DisableEvtIntr(unsigned int baseAdd, 390 unsigned int chNum); 391 392 void EDMA3ClrIntr(unsigned int baseAdd, unsigned int value); 393 394 void EDMA3GetPaRAM(unsigned int baseAdd, 395 unsigned int chNum, 396 EDMA3CCPaRAMEntry* currPaRAM); 397 398 void EDMA3QdmaGetPaRAM(unsigned int baseAdd, 399 unsigned int chNum, 400 unsigned int paRAMId, 401 EDMA3CCPaRAMEntry* currPaRAM); 402 403 void EDMA3SetPaRAM(unsigned int baseAdd, 404 unsigned int chNum, 405 EDMA3CCPaRAMEntry* newPaRAM); 406 407 void EDMA3QdmaSetPaRAM(unsigned int baseAdd, 408 unsigned int chNum, 409 unsigned int paRAMId, 410 EDMA3CCPaRAMEntry* newPaRAM); 411 412 void EDMA3QdmaSetPaRAMEntry(unsigned int baseAdd, 413 unsigned int paRAMId, 414 unsigned int paRAMEntry, 415 unsigned int newPaRAMEntryVal); 416 417 unsigned int EDMA3QdmaGetPaRAMEntry(unsigned int baseAdd, 418 unsigned int paRAMId, 419 unsigned int paRAMEntry); 420 421 unsigned int EDMA3RequestChannel(unsigned int baseAdd, unsigned int chType, 422 unsigned int chNum, unsigned int tccNum, 423 unsigned int evtQNum); 424 425 unsigned int EDMA3FreeChannel(unsigned int baseAdd, unsigned int chType, 426 unsigned int chNum, unsigned int trigMode, 427 unsigned int tccNum, unsigned int evtQNum); 428 429 unsigned int EDMA3EnableTransfer(unsigned int baseAdd, 430 unsigned int chNum, 431 unsigned int trigMode); 432 433 unsigned int EDMA3DisableTransfer(unsigned int baseAdd, 434 unsigned int chNum, 435 unsigned int trigMode); 436 437 void EDMA3ClearErrorBits(unsigned int baseAdd, 438 unsigned int chNum, 439 unsigned int evtQNum); 440 441 unsigned int EDMA3GetCCErrStatus(unsigned int baseAdd); 442 443 unsigned int EDMA3GetErrIntrStatus(unsigned int baseAdd); 444 445 unsigned int EDMA3QdmaGetErrIntrStatus(unsigned int baseAdd); 446 447 void EDMA3Deinit(unsigned int baseAdd, 448 unsigned int queNum); 449 450 unsigned int EDMAVersionGet(void); 451 452 unsigned int EDMA3PeripheralIdGet(unsigned int baseAdd); 453 unsigned int EDMA3IntrStatusHighGet(unsigned int baseAdd); 454 unsigned int EDMA3ErrIntrHighStatusGet(unsigned int baseAdd); 455 456 void EDMA3ChannelToParamMap(unsigned int baseAdd, 457 unsigned int channel, 458 unsigned int paramSet); 459 460 extern void EDMA3ContextSave(unsigned int baseAddr, 461 EDMACONTEXT *edmaCntxPtr); 462 extern void EDMA3ContextRestore(unsigned int baseAddr, 463 EDMACONTEXT *edmaCntxPtr); 464 465#ifdef __cplusplus 466} 467#endif 468 469/* !! EOF !! */ 470