1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 8 * See "LICENSE_BSD2.txt" for details. 9 * 10 * @TAG(DATA61_BSD) 11 */ 12 13#include <stdint.h> 14#include "mux.h" 15#include <utils/util.h> 16#include <platsupport/gpio.h> 17#include <platsupport/plat/gpio.h> 18#include <platsupport/plat/mux.h> 19#include "../../services.h" 20 21#define IMX6_IOMUXC_PADDR 0x020E0000 22#define IMX6_IOMUXC_SIZE 0x4000 23 24#define IOMUXC_MUXCTL_OFFSET 0x4C 25#define IOMUXC_PADCTL_OFFSET 0x360 26 27#define IOMUXC_MUXCTL_FORCE_INPUT BIT(4) 28#define IOMUXC_MUXCTL_MODE(x) ((x) & 0x7) 29#define IOMUXC_MUXCTL_MODE_MASK IOMUXC_MUXCTL_MODE(0x7) 30 31/* NOTE: Daisy field is only 1 but for some registers */ 32#define IOMUXC_IS_DAISY(x) ((x) & 0x3) 33#define IOMUXC_IS_DAISY_MASK IOMUXC_IS_DAISY(0x3) 34 35struct imx6_iomuxc_regs { 36 /*** GPR ***/ 37 uint32_t gpr0; /* +0x000 */ 38 uint32_t gpr1; /* +0x004 */ 39 uint32_t gpr2; /* +0x008 */ 40 uint32_t gpr3; /* +0x00C */ 41 uint32_t gpr4; /* +0x010 */ 42 uint32_t gpr5; /* +0x014 */ 43 uint32_t gpr6; /* +0x018 */ 44 uint32_t gpr7; /* +0x01C */ 45 uint32_t gpr8; /* +0x020 */ 46 uint32_t gpr9; /* +0x024 */ 47 uint32_t gpr10; /* +0x028 */ 48 uint32_t gpr11; /* +0x02C */ 49 uint32_t gpr12; /* +0x030 */ 50 uint32_t gpr13; /* +0x034 */ 51 uint32_t res0[2]; 52 /*** MUX control ***/ 53 uint32_t res1[3]; 54 uint32_t sw_mux_ctl_pad_sd2_data1; /* +0x04C */ 55 uint32_t sw_mux_ctl_pad_sd2_data2; /* +0x050 */ 56 uint32_t sw_mux_ctl_pad_sd2_data0; /* +0x054 */ 57 uint32_t sw_mux_ctl_pad_rgmii_txc; /* +0x058 */ 58 uint32_t sw_mux_ctl_pad_rgmii_td0; /* +0x05C */ 59 uint32_t sw_mux_ctl_pad_rgmii_td1; /* +0x060 */ 60 uint32_t sw_mux_ctl_pad_rgmii_td2; /* +0x064 */ 61 uint32_t sw_mux_ctl_pad_rgmii_td3; /* +0x068 */ 62 uint32_t sw_mux_ctl_pad_rgmii_rx_ctl; /* +0x06C */ 63 uint32_t sw_mux_ctl_pad_rgmii_rd0; /* +0x070 */ 64 uint32_t sw_mux_ctl_pad_rgmii_tx_ctl; /* +0x074 */ 65 uint32_t sw_mux_ctl_pad_rgmii_rd1; /* +0x078 */ 66 uint32_t sw_mux_ctl_pad_rgmii_rd2; /* +0x07C */ 67 uint32_t sw_mux_ctl_pad_rgmii_rd3; /* +0x080 */ 68 uint32_t sw_mux_ctl_pad_rgmii_rxc; /* +0x084 */ 69 uint32_t sw_mux_ctl_pad_eim_addr25; /* +0x088 */ 70 uint32_t sw_mux_ctl_pad_eim_eb2; /* +0x08C */ 71 uint32_t sw_mux_ctl_pad_eim_data16; /* +0x090 */ 72 uint32_t sw_mux_ctl_pad_eim_data17; /* +0x094 */ 73 uint32_t sw_mux_ctl_pad_eim_data18; /* +0x098 */ 74 uint32_t sw_mux_ctl_pad_eim_data19; /* +0x09C */ 75 uint32_t sw_mux_ctl_pad_eim_data20; /* +0x0A0 */ 76 uint32_t sw_mux_ctl_pad_eim_data21; /* +0x0A4 */ 77 uint32_t sw_mux_ctl_pad_eim_data22; /* +0x0A8 */ 78 uint32_t sw_mux_ctl_pad_eim_data23; /* +0x0AC */ 79 uint32_t sw_mux_ctl_pad_eim_eb3; /* +0x0B0 */ 80 uint32_t sw_mux_ctl_pad_eim_data24; /* +0x0B4 */ 81 uint32_t sw_mux_ctl_pad_eim_data25; /* +0x0B8 */ 82 uint32_t sw_mux_ctl_pad_eim_data26; /* +0x0BC */ 83 uint32_t sw_mux_ctl_pad_eim_data27; /* +0x0C0 */ 84 uint32_t sw_mux_ctl_pad_eim_data28; /* +0x0C4 */ 85 uint32_t sw_mux_ctl_pad_eim_data29; /* +0x0C8 */ 86 uint32_t sw_mux_ctl_pad_eim_data30; /* +0x0CC */ 87 uint32_t sw_mux_ctl_pad_eim_data31; /* +0x0D0 */ 88 uint32_t sw_mux_ctl_pad_eim_addr24; /* +0x0D4 */ 89 uint32_t sw_mux_ctl_pad_eim_addr23; /* +0x0D8 */ 90 uint32_t sw_mux_ctl_pad_eim_addr22; /* +0x0DC */ 91 uint32_t sw_mux_ctl_pad_eim_addr21; /* +0x0E0 */ 92 uint32_t sw_mux_ctl_pad_eim_addr20; /* +0x0E4 */ 93 uint32_t sw_mux_ctl_pad_eim_addr19; /* +0x0E8 */ 94 uint32_t sw_mux_ctl_pad_eim_addr18; /* +0x0EC */ 95 uint32_t sw_mux_ctl_pad_eim_addr17; /* +0x0F0 */ 96 uint32_t sw_mux_ctl_pad_eim_addr16; /* +0x0F4 */ 97 uint32_t sw_mux_ctl_pad_eim_cs0; /* +0x0F8 */ 98 uint32_t sw_mux_ctl_pad_eim_cs1; /* +0x0FC */ 99 uint32_t sw_mux_ctl_pad_eim_oe; /* +0x100 */ 100 uint32_t sw_mux_ctl_pad_eim_rw; /* +0x104 */ 101 uint32_t sw_mux_ctl_pad_eim_lba; /* +0x108 */ 102 uint32_t sw_mux_ctl_pad_eim_eb0; /* +0x10C */ 103 uint32_t sw_mux_ctl_pad_eim_eb1; /* +0x110 */ 104 uint32_t sw_mux_ctl_pad_eim_ad00; /* +0x114 */ 105 uint32_t sw_mux_ctl_pad_eim_ad01; /* +0x118 */ 106 uint32_t sw_mux_ctl_pad_eim_ad02; /* +0x11C */ 107 uint32_t sw_mux_ctl_pad_eim_ad03; /* +0x120 */ 108 uint32_t sw_mux_ctl_pad_eim_ad04; /* +0x124 */ 109 uint32_t sw_mux_ctl_pad_eim_ad05; /* +0x128 */ 110 uint32_t sw_mux_ctl_pad_eim_ad06; /* +0x12C */ 111 uint32_t sw_mux_ctl_pad_eim_ad07; /* +0x130 */ 112 uint32_t sw_mux_ctl_pad_eim_ad08; /* +0x134 */ 113 uint32_t sw_mux_ctl_pad_eim_ad09; /* +0x138 */ 114 uint32_t sw_mux_ctl_pad_eim_ad10; /* +0x13C */ 115 uint32_t sw_mux_ctl_pad_eim_ad11; /* +0x140 */ 116 uint32_t sw_mux_ctl_pad_eim_ad12; /* +0x144 */ 117 uint32_t sw_mux_ctl_pad_eim_ad13; /* +0x148 */ 118 uint32_t sw_mux_ctl_pad_eim_ad14; /* +0x14C */ 119 uint32_t sw_mux_ctl_pad_eim_ad15; /* +0x150 */ 120 uint32_t sw_mux_ctl_pad_eim_wait; /* +0x154 */ 121 uint32_t sw_mux_ctl_pad_eim_bclk; /* +0x158 */ 122 uint32_t sw_mux_ctl_pad_di0_disp_clk; /* +0x15C */ 123 uint32_t sw_mux_ctl_pad_di0_pin15; /* +0x160 */ 124 uint32_t sw_mux_ctl_pad_di0_pin02; /* +0x164 */ 125 uint32_t sw_mux_ctl_pad_di0_pin03; /* +0x168 */ 126 uint32_t sw_mux_ctl_pad_di0_pin04; /* +0x16C */ 127 uint32_t sw_mux_ctl_pad_disp0_data00; /* +0x170 */ 128 uint32_t sw_mux_ctl_pad_disp0_data01; /* +0x174 */ 129 uint32_t sw_mux_ctl_pad_disp0_data02; /* +0x178 */ 130 uint32_t sw_mux_ctl_pad_disp0_data03; /* +0x17C */ 131 uint32_t sw_mux_ctl_pad_disp0_data04; /* +0x180 */ 132 uint32_t sw_mux_ctl_pad_disp0_data05; /* +0x184 */ 133 uint32_t sw_mux_ctl_pad_disp0_data06; /* +0x188 */ 134 uint32_t sw_mux_ctl_pad_disp0_data07; /* +0x18C */ 135 uint32_t sw_mux_ctl_pad_disp0_data08; /* +0x190 */ 136 uint32_t sw_mux_ctl_pad_disp0_data09; /* +0x194 */ 137 uint32_t sw_mux_ctl_pad_disp0_data10; /* +0x198 */ 138 uint32_t sw_mux_ctl_pad_disp0_data11; /* +0x19C */ 139 uint32_t sw_mux_ctl_pad_disp0_data12; /* +0x1A0 */ 140 uint32_t sw_mux_ctl_pad_disp0_data13; /* +0x1A4 */ 141 uint32_t sw_mux_ctl_pad_disp0_data14; /* +0x1A8 */ 142 uint32_t sw_mux_ctl_pad_disp0_data15; /* +0x1AC */ 143 uint32_t sw_mux_ctl_pad_disp0_data16; /* +0x1B0 */ 144 uint32_t sw_mux_ctl_pad_disp0_data17; /* +0x1B4 */ 145 uint32_t sw_mux_ctl_pad_disp0_data18; /* +0x1B8 */ 146 uint32_t sw_mux_ctl_pad_disp0_data19; /* +0x1BC */ 147 uint32_t sw_mux_ctl_pad_disp0_data20; /* +0x1C0 */ 148 uint32_t sw_mux_ctl_pad_disp0_data21; /* +0x1C4 */ 149 uint32_t sw_mux_ctl_pad_disp0_data22; /* +0x1C8 */ 150 uint32_t sw_mux_ctl_pad_disp0_data23; /* +0x1CC */ 151 uint32_t sw_mux_ctl_pad_enet_mdio; /* +0x1D0 */ 152 uint32_t sw_mux_ctl_pad_enet_ref_clk; /* +0x1D4 */ 153 uint32_t sw_mux_ctl_pad_enet_rx_er; /* +0x1D8 */ 154 uint32_t sw_mux_ctl_pad_enet_crs_dv; /* +0x1DC */ 155 uint32_t sw_mux_ctl_pad_enet_rx_data1; /* +0x1E0 */ 156 uint32_t sw_mux_ctl_pad_enet_rx_data0; /* +0x1E4 */ 157 uint32_t sw_mux_ctl_pad_enet_tx_en; /* +0x1E8 */ 158 uint32_t sw_mux_ctl_pad_enet_tx_data1; /* +0x1EC */ 159 uint32_t sw_mux_ctl_pad_enet_tx_data0; /* +0x1F0 */ 160 uint32_t sw_mux_ctl_pad_enet_mdc; /* +0x1F4 */ 161 uint32_t sw_mux_ctl_pad_key_col0; /* +0x1F8 */ 162 uint32_t sw_mux_ctl_pad_key_row0; /* +0x1FC */ 163 uint32_t sw_mux_ctl_pad_key_col1; /* +0x200 */ 164 uint32_t sw_mux_ctl_pad_key_row1; /* +0x204 */ 165 uint32_t sw_mux_ctl_pad_key_col2; /* +0x208 */ 166 uint32_t sw_mux_ctl_pad_key_row2; /* +0x20C */ 167 uint32_t sw_mux_ctl_pad_key_col3; /* +0x210 */ 168 uint32_t sw_mux_ctl_pad_key_row3; /* +0x214 */ 169 uint32_t sw_mux_ctl_pad_key_col4; /* +0x218 */ 170 uint32_t sw_mux_ctl_pad_key_row4; /* +0x21C */ 171 uint32_t sw_mux_ctl_pad_gpio00; /* +0x220 */ 172 uint32_t sw_mux_ctl_pad_gpio01; /* +0x224 */ 173 uint32_t sw_mux_ctl_pad_gpio09; /* +0x228 */ 174 uint32_t sw_mux_ctl_pad_gpio03; /* +0x22C */ 175 uint32_t sw_mux_ctl_pad_gpio06; /* +0x230 */ 176 uint32_t sw_mux_ctl_pad_gpio02; /* +0x234 */ 177 uint32_t sw_mux_ctl_pad_gpio04; /* +0x238 */ 178 uint32_t sw_mux_ctl_pad_gpio05; /* +0x23C */ 179 uint32_t sw_mux_ctl_pad_gpio07; /* +0x240 */ 180 uint32_t sw_mux_ctl_pad_gpio08; /* +0x244 */ 181 uint32_t sw_mux_ctl_pad_gpio16; /* +0x248 */ 182 uint32_t sw_mux_ctl_pad_gpio17; /* +0x24C */ 183 uint32_t sw_mux_ctl_pad_gpio18; /* +0x250 */ 184 uint32_t sw_mux_ctl_pad_gpio19; /* +0x254 */ 185 uint32_t sw_mux_ctl_pad_csi0_pixclk; /* +0x258 */ 186 uint32_t sw_mux_ctl_pad_csi0_hsync; /* +0x25C */ 187 uint32_t sw_mux_ctl_pad_csi0_data_en; /* +0x260 */ 188 uint32_t sw_mux_ctl_pad_csi0_vsync; /* +0x264 */ 189 uint32_t sw_mux_ctl_pad_csi0_data04; /* +0x268 */ 190 uint32_t sw_mux_ctl_pad_csi0_data05; /* +0x26C */ 191 uint32_t sw_mux_ctl_pad_csi0_data06; /* +0x270 */ 192 uint32_t sw_mux_ctl_pad_csi0_data07; /* +0x274 */ 193 uint32_t sw_mux_ctl_pad_csi0_data08; /* +0x278 */ 194 uint32_t sw_mux_ctl_pad_csi0_data09; /* +0x27C */ 195 uint32_t sw_mux_ctl_pad_csi0_data10; /* +0x280 */ 196 uint32_t sw_mux_ctl_pad_csi0_data11; /* +0x284 */ 197 uint32_t sw_mux_ctl_pad_csi0_data12; /* +0x288 */ 198 uint32_t sw_mux_ctl_pad_csi0_data13; /* +0x28C */ 199 uint32_t sw_mux_ctl_pad_csi0_data14; /* +0x290 */ 200 uint32_t sw_mux_ctl_pad_csi0_data15; /* +0x294 */ 201 uint32_t sw_mux_ctl_pad_csi0_data16; /* +0x298 */ 202 uint32_t sw_mux_ctl_pad_csi0_data17; /* +0x29C */ 203 uint32_t sw_mux_ctl_pad_csi0_data18; /* +0x2A0 */ 204 uint32_t sw_mux_ctl_pad_csi0_data19; /* +0x2A4 */ 205 uint32_t sw_mux_ctl_pad_sd3_data7; /* +0x2A8 */ 206 uint32_t sw_mux_ctl_pad_sd3_data6; /* +0x2AC */ 207 uint32_t sw_mux_ctl_pad_sd3_data5; /* +0x2B0 */ 208 uint32_t sw_mux_ctl_pad_sd3_data4; /* +0x2B4 */ 209 uint32_t sw_mux_ctl_pad_sd3_cmd; /* +0x2B8 */ 210 uint32_t sw_mux_ctl_pad_sd3_clk; /* +0x2BC */ 211 uint32_t sw_mux_ctl_pad_sd3_data0; /* +0x2C0 */ 212 uint32_t sw_mux_ctl_pad_sd3_data1; /* +0x2C4 */ 213 uint32_t sw_mux_ctl_pad_sd3_data2; /* +0x2C8 */ 214 uint32_t sw_mux_ctl_pad_sd3_data3; /* +0x2CC */ 215 uint32_t sw_mux_ctl_pad_sd3_reset; /* +0x2D0 */ 216 uint32_t sw_mux_ctl_pad_nand_cle; /* +0x2D4 */ 217 uint32_t sw_mux_ctl_pad_nand_ale; /* +0x2D8 */ 218 uint32_t sw_mux_ctl_pad_nand_wp_b; /* +0x2DC */ 219 uint32_t sw_mux_ctl_pad_nand_ready; /* +0x2E0 */ 220 uint32_t sw_mux_ctl_pad_nand_cs0_b; /* +0x2E4 */ 221 uint32_t sw_mux_ctl_pad_nand_cs1_b; /* +0x2E8 */ 222 uint32_t sw_mux_ctl_pad_nand_cs2_b; /* +0x2EC */ 223 uint32_t sw_mux_ctl_pad_nand_cs3_b; /* +0x2F0 */ 224 uint32_t sw_mux_ctl_pad_sd4_cmd; /* +0x2F4 */ 225 uint32_t sw_mux_ctl_pad_sd4_clk; /* +0x2F8 */ 226 uint32_t sw_mux_ctl_pad_nand_data00; /* +0x2FC */ 227 uint32_t sw_mux_ctl_pad_nand_data01; /* +0x300 */ 228 uint32_t sw_mux_ctl_pad_nand_data02; /* +0x304 */ 229 uint32_t sw_mux_ctl_pad_nand_data03; /* +0x308 */ 230 uint32_t sw_mux_ctl_pad_nand_data04; /* +0x30C */ 231 uint32_t sw_mux_ctl_pad_nand_data05; /* +0x310 */ 232 uint32_t sw_mux_ctl_pad_nand_data06; /* +0x314 */ 233 uint32_t sw_mux_ctl_pad_nand_data07; /* +0x318 */ 234 uint32_t sw_mux_ctl_pad_sd4_data0; /* +0x31C */ 235 uint32_t sw_mux_ctl_pad_sd4_data1; /* +0x320 */ 236 uint32_t sw_mux_ctl_pad_sd4_data2; /* +0x324 */ 237 uint32_t sw_mux_ctl_pad_sd4_data3; /* +0x328 */ 238 uint32_t sw_mux_ctl_pad_sd4_data4; /* +0x32C */ 239 uint32_t sw_mux_ctl_pad_sd4_data5; /* +0x330 */ 240 uint32_t sw_mux_ctl_pad_sd4_data6; /* +0x334 */ 241 uint32_t sw_mux_ctl_pad_sd4_data7; /* +0x338 */ 242 uint32_t sw_mux_ctl_pad_sd1_data1; /* +0x33C */ 243 uint32_t sw_mux_ctl_pad_sd1_data0; /* +0x340 */ 244 uint32_t sw_mux_ctl_pad_sd1_data3; /* +0x344 */ 245 uint32_t sw_mux_ctl_pad_sd1_cmd; /* +0x348 */ 246 uint32_t sw_mux_ctl_pad_sd1_data2; /* +0x34C */ 247 uint32_t sw_mux_ctl_pad_sd1_clk; /* +0x350 */ 248 uint32_t sw_mux_ctl_pad_sd2_clk; /* +0x354 */ 249 uint32_t sw_mux_ctl_pad_sd2_cmd; /* +0x358 */ 250 uint32_t sw_mux_ctl_pad_sd2_data3; /* +0x35C */ 251 /*** Pad Control ***/ 252 uint32_t sw_pad_ctl_pad_sd2_data1; /* +0x360 */ 253 uint32_t sw_pad_ctl_pad_sd2_data2; /* +0x364 */ 254 uint32_t sw_pad_ctl_pad_sd2_data0; /* +0x368 */ 255 uint32_t sw_pad_ctl_pad_rgmii_txc; /* +0x36C */ 256 uint32_t sw_pad_ctl_pad_rgmii_td0; /* +0x370 */ 257 uint32_t sw_pad_ctl_pad_rgmii_td1; /* +0x374 */ 258 uint32_t sw_pad_ctl_pad_rgmii_td2; /* +0x378 */ 259 uint32_t sw_pad_ctl_pad_rgmii_td3; /* +0x37C */ 260 uint32_t sw_pad_ctl_pad_rgmii_rx_ctl; /* +0x380 */ 261 uint32_t sw_pad_ctl_pad_rgmii_rd0; /* +0x384 */ 262 uint32_t sw_pad_ctl_pad_rgmii_tx_ctl; /* +0x388 */ 263 uint32_t sw_pad_ctl_pad_rgmii_rd1; /* +0x38C */ 264 uint32_t sw_pad_ctl_pad_rgmii_rd2; /* +0x390 */ 265 uint32_t sw_pad_ctl_pad_rgmii_rd3; /* +0x394 */ 266 uint32_t sw_pad_ctl_pad_rgmii_rxc; /* +0x398 */ 267 uint32_t sw_pad_ctl_pad_eim_addr25; /* +0x39C */ 268 uint32_t sw_pad_ctl_pad_eim_eb2; /* +0x3A0 */ 269 uint32_t sw_pad_ctl_pad_eim_data16; /* +0x3A4 */ 270 uint32_t sw_pad_ctl_pad_eim_data17; /* +0x3A8 */ 271 uint32_t sw_pad_ctl_pad_eim_data18; /* +0x3AC */ 272 uint32_t sw_pad_ctl_pad_eim_data19; /* +0x3B0 */ 273 uint32_t sw_pad_ctl_pad_eim_data20; /* +0x3B4 */ 274 uint32_t sw_pad_ctl_pad_eim_data21; /* +0x3B8 */ 275 uint32_t sw_pad_ctl_pad_eim_data22; /* +0x3BC */ 276 uint32_t sw_pad_ctl_pad_eim_data23; /* +0x3C0 */ 277 uint32_t sw_pad_ctl_pad_eim_eb3; /* +0x3C4 */ 278 uint32_t sw_pad_ctl_pad_eim_data24; /* +0x3C8 */ 279 uint32_t sw_pad_ctl_pad_eim_data25; /* +0x3CC */ 280 uint32_t sw_pad_ctl_pad_eim_data26; /* +0x3D0 */ 281 uint32_t sw_pad_ctl_pad_eim_data27; /* +0x3D4 */ 282 uint32_t sw_pad_ctl_pad_eim_data28; /* +0x3D8 */ 283 uint32_t sw_pad_ctl_pad_eim_data29; /* +0x3DC */ 284 uint32_t sw_pad_ctl_pad_eim_data30; /* +0x3E0 */ 285 uint32_t sw_pad_ctl_pad_eim_data31; /* +0x3E4 */ 286 uint32_t sw_pad_ctl_pad_eim_addr24; /* +0x3E8 */ 287 uint32_t sw_pad_ctl_pad_eim_addr23; /* +0x3EC */ 288 uint32_t sw_pad_ctl_pad_eim_addr22; /* +0x3F0 */ 289 uint32_t sw_pad_ctl_pad_eim_addr21; /* +0x3F4 */ 290 uint32_t sw_pad_ctl_pad_eim_addr20; /* +0x3F8 */ 291 uint32_t sw_pad_ctl_pad_eim_addr19; /* +0x3FC */ 292 uint32_t sw_pad_ctl_pad_eim_addr18; /* +0x400 */ 293 uint32_t sw_pad_ctl_pad_eim_addr17; /* +0x404 */ 294 uint32_t sw_pad_ctl_pad_eim_addr16; /* +0x408 */ 295 uint32_t sw_pad_ctl_pad_eim_cs0; /* +0x40C */ 296 uint32_t sw_pad_ctl_pad_eim_cs1; /* +0x410 */ 297 uint32_t sw_pad_ctl_pad_eim_oe; /* +0x414 */ 298 uint32_t sw_pad_ctl_pad_eim_rw; /* +0x418 */ 299 uint32_t sw_pad_ctl_pad_eim_lba; /* +0x41C */ 300 uint32_t sw_pad_ctl_pad_eim_eb0; /* +0x420 */ 301 uint32_t sw_pad_ctl_pad_eim_eb1; /* +0x424 */ 302 uint32_t sw_pad_ctl_pad_eim_ad00; /* +0x428 */ 303 uint32_t sw_pad_ctl_pad_eim_ad01; /* +0x42C */ 304 uint32_t sw_pad_ctl_pad_eim_ad02; /* +0x430 */ 305 uint32_t sw_pad_ctl_pad_eim_ad03; /* +0x434 */ 306 uint32_t sw_pad_ctl_pad_eim_ad04; /* +0x438 */ 307 uint32_t sw_pad_ctl_pad_eim_ad05; /* +0x43C */ 308 uint32_t sw_pad_ctl_pad_eim_ad06; /* +0x440 */ 309 uint32_t sw_pad_ctl_pad_eim_ad07; /* +0x444 */ 310 uint32_t sw_pad_ctl_pad_eim_ad08; /* +0x448 */ 311 uint32_t sw_pad_ctl_pad_eim_ad09; /* +0x44C */ 312 uint32_t sw_pad_ctl_pad_eim_ad10; /* +0x450 */ 313 uint32_t sw_pad_ctl_pad_eim_ad11; /* +0x454 */ 314 uint32_t sw_pad_ctl_pad_eim_ad12; /* +0x458 */ 315 uint32_t sw_pad_ctl_pad_eim_ad13; /* +0x45C */ 316 uint32_t sw_pad_ctl_pad_eim_ad14; /* +0x460 */ 317 uint32_t sw_pad_ctl_pad_eim_ad15; /* +0x464 */ 318 uint32_t sw_pad_ctl_pad_eim_wait; /* +0x468 */ 319 uint32_t sw_pad_ctl_pad_eim_bclk; /* +0x46C */ 320 uint32_t sw_pad_ctl_pad_di0_disp_clk; /* +0x470 */ 321 uint32_t sw_pad_ctl_pad_di0_pin15; /* +0x474 */ 322 uint32_t sw_pad_ctl_pad_di0_pin02; /* +0x478 */ 323 uint32_t sw_pad_ctl_pad_di0_pin03; /* +0x47C */ 324 uint32_t sw_pad_ctl_pad_di0_pin04; /* +0x480 */ 325 uint32_t sw_pad_ctl_pad_disp0_data00; /* +0x484 */ 326 uint32_t sw_pad_ctl_pad_disp0_data01; /* +0x488 */ 327 uint32_t sw_pad_ctl_pad_disp0_data02; /* +0x48C */ 328 uint32_t sw_pad_ctl_pad_disp0_data03; /* +0x490 */ 329 uint32_t sw_pad_ctl_pad_disp0_data04; /* +0x494 */ 330 uint32_t sw_pad_ctl_pad_disp0_data05; /* +0x498 */ 331 uint32_t sw_pad_ctl_pad_disp0_data06; /* +0x49C */ 332 uint32_t sw_pad_ctl_pad_disp0_data07; /* +0x4A0 */ 333 uint32_t sw_pad_ctl_pad_disp0_data08; /* +0x4A4 */ 334 uint32_t sw_pad_ctl_pad_disp0_data09; /* +0x4A8 */ 335 uint32_t sw_pad_ctl_pad_disp0_data10; /* +0x4AC */ 336 uint32_t sw_pad_ctl_pad_disp0_data11; /* +0x4B0 */ 337 uint32_t sw_pad_ctl_pad_disp0_data12; /* +0x4B4 */ 338 uint32_t sw_pad_ctl_pad_disp0_data13; /* +0x4B8 */ 339 uint32_t sw_pad_ctl_pad_disp0_data14; /* +0x4BC */ 340 uint32_t sw_pad_ctl_pad_disp0_data15; /* +0x4C0 */ 341 uint32_t sw_pad_ctl_pad_disp0_data16; /* +0x4C4 */ 342 uint32_t sw_pad_ctl_pad_disp0_data17; /* +0x4C8 */ 343 uint32_t sw_pad_ctl_pad_disp0_data18; /* +0x4CC */ 344 uint32_t sw_pad_ctl_pad_disp0_data19; /* +0x4D0 */ 345 uint32_t sw_pad_ctl_pad_disp0_data20; /* +0x4D4 */ 346 uint32_t sw_pad_ctl_pad_disp0_data21; /* +0x4D8 */ 347 uint32_t sw_pad_ctl_pad_disp0_data22; /* +0x4DC */ 348 uint32_t sw_pad_ctl_pad_disp0_data23; /* +0x4E0 */ 349 uint32_t sw_pad_ctl_pad_enet_mdio; /* +0x4E4 */ 350 uint32_t sw_pad_ctl_pad_enet_ref_clk; /* +0x4E8 */ 351 uint32_t sw_pad_ctl_pad_enet_rx_er; /* +0x4EC */ 352 uint32_t sw_pad_ctl_pad_enet_crs_dv; /* +0x4F0 */ 353 uint32_t sw_pad_ctl_pad_enet_rx_data1; /* +0x4F4 */ 354 uint32_t sw_pad_ctl_pad_enet_rx_data0; /* +0x4F8 */ 355 uint32_t sw_pad_ctl_pad_enet_tx_en; /* +0x4FC */ 356 uint32_t sw_pad_ctl_pad_enet_tx_data1; /* +0x500 */ 357 uint32_t sw_pad_ctl_pad_enet_tx_data0; /* +0x504 */ 358 uint32_t sw_pad_ctl_pad_enet_mdc; /* +0x508 */ 359 uint32_t sw_pad_ctl_pad_dram_sdqs5_p; /* +0x50C */ 360 uint32_t sw_pad_ctl_pad_dram_dqm5; /* +0x510 */ 361 uint32_t sw_pad_ctl_pad_dram_dqm4; /* +0x514 */ 362 uint32_t sw_pad_ctl_pad_dram_sdqs4_p; /* +0x518 */ 363 uint32_t sw_pad_ctl_pad_dram_sdqs3_p; /* +0x51C */ 364 uint32_t sw_pad_ctl_pad_dram_dqm3; /* +0x520 */ 365 uint32_t sw_pad_ctl_pad_dram_sdqs2_p; /* +0x524 */ 366 uint32_t sw_pad_ctl_pad_dram_dqm2; /* +0x528 */ 367 uint32_t sw_pad_ctl_pad_dram_addr00; /* +0x52C */ 368 uint32_t sw_pad_ctl_pad_dram_addr01; /* +0x530 */ 369 uint32_t sw_pad_ctl_pad_dram_addr02; /* +0x534 */ 370 uint32_t sw_pad_ctl_pad_dram_addr03; /* +0x538 */ 371 uint32_t sw_pad_ctl_pad_dram_addr04; /* +0x53C */ 372 uint32_t sw_pad_ctl_pad_dram_addr05; /* +0x540 */ 373 uint32_t sw_pad_ctl_pad_dram_addr06; /* +0x544 */ 374 uint32_t sw_pad_ctl_pad_dram_addr07; /* +0x548 */ 375 uint32_t sw_pad_ctl_pad_dram_addr08; /* +0x54C */ 376 uint32_t sw_pad_ctl_pad_dram_addr09; /* +0x550 */ 377 uint32_t sw_pad_ctl_pad_dram_addr10; /* +0x554 */ 378 uint32_t sw_pad_ctl_pad_dram_addr11; /* +0x558 */ 379 uint32_t sw_pad_ctl_pad_dram_addr12; /* +0x55C */ 380 uint32_t sw_pad_ctl_pad_dram_addr13; /* +0x560 */ 381 uint32_t sw_pad_ctl_pad_dram_addr14; /* +0x564 */ 382 uint32_t sw_pad_ctl_pad_dram_addr15; /* +0x568 */ 383 uint32_t sw_pad_ctl_pad_dram_cas; /* +0x56C */ 384 uint32_t sw_pad_ctl_pad_dram_cs0; /* +0x570 */ 385 uint32_t sw_pad_ctl_pad_dram_cs1; /* +0x574 */ 386 uint32_t sw_pad_ctl_pad_dram_ras; /* +0x578 */ 387 uint32_t sw_pad_ctl_pad_dram_reset; /* +0x57C */ 388 uint32_t sw_pad_ctl_pad_dram_sdba0; /* +0x580 */ 389 uint32_t sw_pad_ctl_pad_dram_sdba1; /* +0x584 */ 390 uint32_t sw_pad_ctl_pad_dram_sdclk0_p; /* +0x588 */ 391 uint32_t sw_pad_ctl_pad_dram_sdba2; /* +0x58C */ 392 uint32_t sw_pad_ctl_pad_dram_sdcke0; /* +0x590 */ 393 uint32_t sw_pad_ctl_pad_dram_sdclk1_p; /* +0x594 */ 394 uint32_t sw_pad_ctl_pad_dram_sdcke1; /* +0x598 */ 395 uint32_t sw_pad_ctl_pad_dram_odt0; /* +0x59C */ 396 uint32_t sw_pad_ctl_pad_dram_odt1; /* +0x5A0 */ 397 uint32_t sw_pad_ctl_pad_dram_sdwe; /* +0x5A4 */ 398 uint32_t sw_pad_ctl_pad_dram_sdqs0_p; /* +0x5A8 */ 399 uint32_t sw_pad_ctl_pad_dram_dqm0; /* +0x5AC */ 400 uint32_t sw_pad_ctl_pad_dram_sdqs1_p; /* +0x5B0 */ 401 uint32_t sw_pad_ctl_pad_dram_dqm1; /* +0x5B4 */ 402 uint32_t sw_pad_ctl_pad_dram_sdqs6_p; /* +0x5B8 */ 403 uint32_t sw_pad_ctl_pad_dram_dqm6; /* +0x5BC */ 404 uint32_t sw_pad_ctl_pad_dram_sdqs7_p; /* +0x5C0 */ 405 uint32_t sw_pad_ctl_pad_dram_dqm7; /* +0x5C4 */ 406 uint32_t sw_pad_ctl_pad_key_col0; /* +0x5C8 */ 407 uint32_t sw_pad_ctl_pad_key_row0; /* +0x5CC */ 408 uint32_t sw_pad_ctl_pad_key_col1; /* +0x5D0 */ 409 uint32_t sw_pad_ctl_pad_key_row1; /* +0x5D4 */ 410 uint32_t sw_pad_ctl_pad_key_col2; /* +0x5D8 */ 411 uint32_t sw_pad_ctl_pad_key_row2; /* +0x5DC */ 412 uint32_t sw_pad_ctl_pad_key_col3; /* +0x5E0 */ 413 uint32_t sw_pad_ctl_pad_key_row3; /* +0x5E4 */ 414 uint32_t sw_pad_ctl_pad_key_col4; /* +0x5E8 */ 415 uint32_t sw_pad_ctl_pad_key_row4; /* +0x5EC */ 416 uint32_t sw_pad_ctl_pad_mux00; /* +0x5F0 */ 417 uint32_t sw_pad_ctl_pad_mux01; /* +0x5F4 */ 418 uint32_t sw_pad_ctl_pad_mux09; /* +0x5F8 */ 419 uint32_t sw_pad_ctl_pad_mux03; /* +0x5FC */ 420 uint32_t sw_pad_ctl_pad_mux06; /* +0x600 */ 421 uint32_t sw_pad_ctl_pad_mux02; /* +0x604 */ 422 uint32_t sw_pad_ctl_pad_mux04; /* +0x608 */ 423 uint32_t sw_pad_ctl_pad_mux05; /* +0x60C */ 424 uint32_t sw_pad_ctl_pad_mux07; /* +0x610 */ 425 uint32_t sw_pad_ctl_pad_mux08; /* +0x614 */ 426 uint32_t sw_pad_ctl_pad_mux16; /* +0x618 */ 427 uint32_t sw_pad_ctl_pad_mux17; /* +0x61C */ 428 uint32_t sw_pad_ctl_pad_mux18; /* +0x620 */ 429 uint32_t sw_pad_ctl_pad_mux19; /* +0x624 */ 430 uint32_t sw_pad_ctl_pad_csi0_pixclk; /* +0x628 */ 431 uint32_t sw_pad_ctl_pad_csi0_hsync; /* +0x62C */ 432 uint32_t sw_pad_ctl_pad_csi0_data_en; /* +0x630 */ 433 uint32_t sw_pad_ctl_pad_csi0_vsync; /* +0x634 */ 434 uint32_t sw_pad_ctl_pad_csi0_data04; /* +0x638 */ 435 uint32_t sw_pad_ctl_pad_csi0_data05; /* +0x63C */ 436 uint32_t sw_pad_ctl_pad_csi0_data06; /* +0x640 */ 437 uint32_t sw_pad_ctl_pad_csi0_data07; /* +0x644 */ 438 uint32_t sw_pad_ctl_pad_csi0_data08; /* +0x648 */ 439 uint32_t sw_pad_ctl_pad_csi0_data09; /* +0x64C */ 440 uint32_t sw_pad_ctl_pad_csi0_data10; /* +0x650 */ 441 uint32_t sw_pad_ctl_pad_csi0_data11; /* +0x654 */ 442 uint32_t sw_pad_ctl_pad_csi0_data12; /* +0x658 */ 443 uint32_t sw_pad_ctl_pad_csi0_data13; /* +0x65C */ 444 uint32_t sw_pad_ctl_pad_csi0_data14; /* +0x660 */ 445 uint32_t sw_pad_ctl_pad_csi0_data15; /* +0x664 */ 446 uint32_t sw_pad_ctl_pad_csi0_data16; /* +0x668 */ 447 uint32_t sw_pad_ctl_pad_csi0_data17; /* +0x66C */ 448 uint32_t sw_pad_ctl_pad_csi0_data18; /* +0x670 */ 449 uint32_t sw_pad_ctl_pad_csi0_data19; /* +0x674 */ 450 uint32_t sw_pad_ctl_pad_jtag_tms; /* +0x678 */ 451 uint32_t sw_pad_ctl_pad_jtag_mod; /* +0x67C */ 452 uint32_t sw_pad_ctl_pad_jtag_trstb; /* +0x680 */ 453 uint32_t sw_pad_ctl_pad_jtag_tdi; /* +0x684 */ 454 uint32_t sw_pad_ctl_pad_jtag_tck; /* +0x688 */ 455 uint32_t sw_pad_ctl_pad_jtag_tdo; /* +0x68C */ 456 uint32_t sw_pad_ctl_pad_sd3_data7; /* +0x690 */ 457 uint32_t sw_pad_ctl_pad_sd3_data6; /* +0x694 */ 458 uint32_t sw_pad_ctl_pad_sd3_data5; /* +0x698 */ 459 uint32_t sw_pad_ctl_pad_sd3_data4; /* +0x69C */ 460 uint32_t sw_pad_ctl_pad_sd3_cmd; /* +0x6A0 */ 461 uint32_t sw_pad_ctl_pad_sd3_clk; /* +0x6A4 */ 462 uint32_t sw_pad_ctl_pad_sd3_data0; /* +0x6A8 */ 463 uint32_t sw_pad_ctl_pad_sd3_data1; /* +0x6AC */ 464 uint32_t sw_pad_ctl_pad_sd3_data2; /* +0x6B0 */ 465 uint32_t sw_pad_ctl_pad_sd3_data3; /* +0x6B4 */ 466 uint32_t sw_pad_ctl_pad_sd3_reset; /* +0x6B8 */ 467 uint32_t sw_pad_ctl_pad_nand_cle; /* +0x6BC */ 468 uint32_t sw_pad_ctl_pad_nand_ale; /* +0x6C0 */ 469 uint32_t sw_pad_ctl_pad_nand_wp_b; /* +0x6C4 */ 470 uint32_t sw_pad_ctl_pad_nand_ready; /* +0x6C8 */ 471 uint32_t sw_pad_ctl_pad_nand_cs0_b; /* +0x6CC */ 472 uint32_t sw_pad_ctl_pad_nand_cs1_b; /* +0x6D0 */ 473 uint32_t sw_pad_ctl_pad_nand_cs2_b; /* +0x6D4 */ 474 uint32_t sw_pad_ctl_pad_nand_cs3_b; /* +0x6D8 */ 475 uint32_t sw_pad_ctl_pad_sd4_cmd; /* +0x6DC */ 476 uint32_t sw_pad_ctl_pad_sd4_clk; /* +0x6E0 */ 477 uint32_t sw_pad_ctl_pad_nand_data00; /* +0x6E4 */ 478 uint32_t sw_pad_ctl_pad_nand_data01; /* +0x6E8 */ 479 uint32_t sw_pad_ctl_pad_nand_data02; /* +0x6EC */ 480 uint32_t sw_pad_ctl_pad_nand_data03; /* +0x6F0 */ 481 uint32_t sw_pad_ctl_pad_nand_data04; /* +0x6F4 */ 482 uint32_t sw_pad_ctl_pad_nand_data05; /* +0x6F8 */ 483 uint32_t sw_pad_ctl_pad_nand_data06; /* +0x6FC */ 484 uint32_t sw_pad_ctl_pad_nand_data07; /* +0x700 */ 485 uint32_t sw_pad_ctl_pad_sd4_data0; /* +0x704 */ 486 uint32_t sw_pad_ctl_pad_sd4_data1; /* +0x708 */ 487 uint32_t sw_pad_ctl_pad_sd4_data2; /* +0x70C */ 488 uint32_t sw_pad_ctl_pad_sd4_data3; /* +0x710 */ 489 uint32_t sw_pad_ctl_pad_sd4_data4; /* +0x714 */ 490 uint32_t sw_pad_ctl_pad_sd4_data5; /* +0x718 */ 491 uint32_t sw_pad_ctl_pad_sd4_data6; /* +0x71C */ 492 uint32_t sw_pad_ctl_pad_sd4_data7; /* +0x720 */ 493 uint32_t sw_pad_ctl_pad_sd1_data1; /* +0x724 */ 494 uint32_t sw_pad_ctl_pad_sd1_data0; /* +0x728 */ 495 uint32_t sw_pad_ctl_pad_sd1_data3; /* +0x72C */ 496 uint32_t sw_pad_ctl_pad_sd1_cmd; /* +0x730 */ 497 uint32_t sw_pad_ctl_pad_sd1_data2; /* +0x734 */ 498 uint32_t sw_pad_ctl_pad_sd1_clk; /* +0x738 */ 499 uint32_t sw_pad_ctl_pad_sd2_clk; /* +0x73C */ 500 uint32_t sw_pad_ctl_pad_sd2_cmd; /* +0x740 */ 501 uint32_t sw_pad_ctl_pad_sd2_data3; /* +0x744 */ 502 /*** Group ***/ 503 uint32_t sw_pad_ctl_grp_b7ds; /* +0x748 */ 504 uint32_t sw_pad_ctl_grp_addds; /* +0x74C */ 505 uint32_t sw_pad_ctl_grp_ddrmode_ctl; /* +0x750 */ 506 uint32_t sw_pad_ctl_grp_term_ctl0; /* +0x754 */ 507 uint32_t sw_pad_ctl_grp_ddrpke; /* +0x758 */ 508 uint32_t sw_pad_ctl_grp_term_ctl1; /* +0x75C */ 509 uint32_t sw_pad_ctl_grp_term_ctl2; /* +0x760 */ 510 uint32_t sw_pad_ctl_grp_term_ctl3; /* +0x764 */ 511 uint32_t sw_pad_ctl_grp_ddrpk; /* +0x768 */ 512 uint32_t sw_pad_ctl_grp_term_ctl4; /* +0x76C */ 513 uint32_t sw_pad_ctl_grp_ddrhys; /* +0x770 */ 514 uint32_t sw_pad_ctl_grp_ddrmode; /* +0x774 */ 515 uint32_t sw_pad_ctl_grp_term_ctl5; /* +0x778 */ 516 uint32_t sw_pad_ctl_grp_term_ctl6; /* +0x77C */ 517 uint32_t sw_pad_ctl_grp_term_ctl7; /* +0x780 */ 518 uint32_t sw_pad_ctl_grp_b0ds; /* +0x784 */ 519 uint32_t sw_pad_ctl_grp_b1ds; /* +0x788 */ 520 uint32_t sw_pad_ctl_grp_ctlds; /* +0x78C */ 521 uint32_t sw_pad_ctl_grp_ddr_type_rgmii; /* +0x790 */ 522 uint32_t sw_pad_ctl_grp_b2ds; /* +0x794 */ 523 uint32_t sw_pad_ctl_grp_ddr_type; /* +0x798 */ 524 uint32_t sw_pad_ctl_grp_b3ds; /* +0x79C */ 525 uint32_t sw_pad_ctl_grp_b4ds; /* +0x7A0 */ 526 uint32_t sw_pad_ctl_grp_b5ds; /* +0x7A4 */ 527 uint32_t sw_pad_ctl_grp_b6ds; /* +0x7A8 */ 528 uint32_t sw_pad_ctl_grp_rgmii_term; /* +0x7AC */ 529 /*** Select Input ***/ 530 uint32_t asrc_asrck_clock_6_select_input; /* +0x7B0 */ 531 uint32_t aud4_input_da_amx_select_input; /* +0x7B4 */ 532 uint32_t aud4_input_db_amx_select_input; /* +0x7B8 */ 533 uint32_t aud4_input_rxclk_amx_select_input; /* +0x7BC */ 534 uint32_t aud4_input_rxfs_amx_select_input; /* +0x7C0 */ 535 uint32_t aud4_input_txclk_amx_select_input; /* +0x7C4 */ 536 uint32_t aud4_input_txfs_amx_select_input; /* +0x7C8 */ 537 uint32_t aud5_input_da_amx_select_input; /* +0x7CC */ 538 uint32_t aud5_input_db_amx_select_input; /* +0x7D0 */ 539 uint32_t aud5_input_rxclk_amx_select_input; /* +0x7D4 */ 540 uint32_t aud5_input_rxfs_amx_select_input; /* +0x7D8 */ 541 uint32_t aud5_input_txclk_amx_select_input; /* +0x7DC */ 542 uint32_t aud5_input_txfs_amx_select_input; /* +0x7E0 */ 543 uint32_t flexcan1_rx_select_input; /* +0x7E4 */ 544 uint32_t flexcan2_rx_select_input; /* +0x7E8 */ 545 uint32_t res2; 546 uint32_t ccm_pmic_ready_select_input; /* +0x7F0 */ 547 uint32_t ecspi1_cspi_clk_in_select_input; /* +0x7F4 */ 548 uint32_t ecspi1_miso_select_input; /* +0x7F8 */ 549 uint32_t ecspi1_mosi_select_input; /* +0x7FC */ 550 uint32_t ecspi1_ss0_select_input; /* +0x800 */ 551 uint32_t ecspi1_ss1_select_input; /* +0x804 */ 552 uint32_t ecspi1_ss2_select_input; /* +0x808 */ 553 uint32_t ecspi1_ss3_select_input; /* +0x80C */ 554 uint32_t ecspi2_cspi_clk_in_select_input; /* +0x814 */ 555 uint32_t ecspi2_miso_select_input; /* +0x810 */ 556 uint32_t ecspi2_mosi_select_input; /* +0x818 */ 557 uint32_t ecspi2_ss0_select_input; /* +0x81C */ 558 uint32_t ecspi2_ss1_select_input; /* +0x820 */ 559 uint32_t ecspi4_ss0_select_input; /* +0x824 */ 560 uint32_t ecspi5_cspi_clk_in_select_input; /* +0x828 */ 561 uint32_t ecspi5_miso_select_input; /* +0x82C */ 562 uint32_t ecspi5_mosi_select_input; /* +0x830 */ 563 uint32_t ecspi5_ss0_select_input; /* +0x834 */ 564 uint32_t ecspi5_ss1_select_input; /* +0x838 */ 565 uint32_t enet_ref_clk_select_input; /* +0x83C */ 566 uint32_t enet_mac0_mdio_select_input; /* +0x840 */ 567 uint32_t enet_mac0_rx_clk_select_input; /* +0x844 */ 568 uint32_t enet_mac0_rx_data0_select_input; /* +0x848 */ 569 uint32_t enet_mac0_rx_data1_select_input; /* +0x84C */ 570 uint32_t enet_mac0_rx_data2_select_input; /* +0x850 */ 571 uint32_t enet_mac0_rx_data3_select_input; /* +0x854 */ 572 uint32_t enet_mac0_rx_en_select_input; /* +0x858 */ 573 uint32_t esai_rx_fs_select_input; /* +0x85C */ 574 uint32_t esai_tx_fs_select_input; /* +0x860 */ 575 uint32_t esai_rx_hf_clk_select_input; /* +0x864 */ 576 uint32_t esai_tx_hf_clk_select_input; /* +0x868 */ 577 uint32_t esai_rx_clk_select_input; /* +0x86C */ 578 uint32_t esai_tx_clk_select_input; /* +0x870 */ 579 uint32_t esai_sdo0_select_input; /* +0x874 */ 580 uint32_t esai_sdo1_select_input; /* +0x878 */ 581 uint32_t esai_sdo2_sdi3_select_input; /* +0x87C */ 582 uint32_t esai_sdo3_sdi2_select_input; /* +0x880 */ 583 uint32_t esai_sdo4_sdi1_select_input; /* +0x884 */ 584 uint32_t esai_sdo5_sdi0_select_input; /* +0x888 */ 585 uint32_t hdmi_icecin_select_input; /* +0x88C */ 586 uint32_t hdmi_ii2c_clkin_select_input; /* +0x890 */ 587 uint32_t hdmi_ii2c_datain_select_input; /* +0x894 */ 588 uint32_t i2c1_scl_in_select_input; /* +0x898 */ 589 uint32_t i2c1_sda_in_select_input; /* +0x89C */ 590 uint32_t i2c2_scl_in_select_input; /* +0x8A0 */ 591 uint32_t i2c2_sda_in_select_input; /* +0x8A4 */ 592 uint32_t i2c3_scl_in_select_input; /* +0x8A8 */ 593 uint32_t i2c3_sda_in_select_input; /* +0x8AC */ 594 uint32_t ipu2_sens1_data10_select_input; /* +0x8B0 */ 595 uint32_t ipu2_sens1_data11_select_input; /* +0x8B4 */ 596 uint32_t ipu2_sens1_data12_select_input; /* +0x8B8 */ 597 uint32_t ipu2_sens1_data13_select_input; /* +0x8BC */ 598 uint32_t ipu2_sens1_data14_select_input; /* +0x8C0 */ 599 uint32_t ipu2_sens1_data15_select_input; /* +0x8C4 */ 600 uint32_t ipu2_sens1_data16_select_input; /* +0x8C8 */ 601 uint32_t ipu2_sens1_data17_select_input; /* +0x8CC */ 602 uint32_t ipu2_sens1_data18_select_input; /* +0x8D0 */ 603 uint32_t ipu2_sens1_data19_select_input; /* +0x8D4 */ 604 uint32_t ipu2_sens1_data_en_select_input; /* +0x8D8 */ 605 uint32_t ipu2_sens1_hsync_select_input; /* +0x8DC */ 606 uint32_t ipu2_sens1_pix_clk_select_input; /* +0x8E0 */ 607 uint32_t ipu2_sens1_vsync_select_input; /* +0x8E4 */ 608 uint32_t key_col5_select_input; /* +0x8E8 */ 609 uint32_t key_col6_select_input; /* +0x8EC */ 610 uint32_t key_col7_select_input; /* +0x8F0 */ 611 uint32_t key_row5_select_input; /* +0x8F4 */ 612 uint32_t key_row6_select_input; /* +0x8F8 */ 613 uint32_t key_row7_select_input; /* +0x8FC */ 614 uint32_t mlb_mlb_clk_in_select_input; /* +0x900 */ 615 uint32_t mlb_mlb_data_in_select_input; /* +0x904 */ 616 uint32_t mlb_mlb_sig_in_select_input; /* +0x908 */ 617 uint32_t sdma_events14_select_input; /* +0x90C */ 618 uint32_t sdma_events15_select_input; /* +0x910 */ 619 uint32_t spdif_spdif_in1_select_input; /* +0x914 */ 620 uint32_t spdif_tx_clk2_select_input; /* +0x91C */ 621 uint32_t uart1_uart_rts_b_select_input; /* +0x918 */ 622 uint32_t uart1_uart_rx_data_select_input; /* +0x920 */ 623 uint32_t uart2_uart_rts_b_select_input; /* +0x924 */ 624 uint32_t uart2_uart_rx_data_select_input; /* +0x928 */ 625 uint32_t uart3_uart_rts_b_select_input; /* +0x92C */ 626 uint32_t uart3_uart_rx_data_select_input; /* +0x930 */ 627 uint32_t uart4_uart_rts_b_select_input; /* +0x934 */ 628 uint32_t uart4_uart_rx_data_select_input; /* +0x938 */ 629 uint32_t uart5_uart_rts_b_select_input; /* +0x93C */ 630 uint32_t uart5_uart_rx_data_select_input; /* +0x940 */ 631 uint32_t usb_otg_oc_select_input; /* +0x944 */ 632 uint32_t usb_h1_oc_select_input; /* +0x948 */ 633 uint32_t usdhc1_wp_on_select_input; /* +0x94C */ 634}; 635 636static struct imx6_mux { 637 volatile struct imx6_iomuxc_regs* iomuxc; 638} _mux; 639 640static inline struct imx6_mux* get_mux_priv(const mux_sys_t* mux) { 641 return (struct imx6_mux*)mux->priv; 642} 643 644static inline void set_mux_priv(mux_sys_t* mux, struct imx6_mux* imx6_mux) 645{ 646 assert(mux != NULL); 647 assert(imx6_mux != NULL); 648 mux->priv = imx6_mux; 649} 650 651static int 652imx6_mux_feature_enable(const mux_sys_t* mux, mux_feature_t mux_feature, UNUSED enum mux_gpio_dir mgd) 653{ 654 struct imx6_mux* m; 655 if (mux == NULL || mux->priv == NULL) { 656 return -1; 657 } 658 m = get_mux_priv(mux); 659 660 assert(((int)&m->iomuxc->usdhc1_wp_on_select_input & 0xfff) == 0x94C); 661 switch (mux_feature) { 662 case MUX_I2C1: 663 ZF_LOGD("Muxing for I2C1\n"); 664 m->iomuxc->i2c1_scl_in_select_input = IOMUXC_IS_DAISY(0x0); 665 m->iomuxc->sw_mux_ctl_pad_eim_data21 = IOMUXC_MUXCTL_MODE(6) 666 | IOMUXC_MUXCTL_FORCE_INPUT; 667 m->iomuxc->i2c1_sda_in_select_input = IOMUXC_IS_DAISY(0x0); 668 m->iomuxc->sw_mux_ctl_pad_eim_data28 = IOMUXC_MUXCTL_MODE(1) 669 | IOMUXC_MUXCTL_FORCE_INPUT; 670 return 0; 671 case MUX_I2C2: 672 ZF_LOGD("Muxing for I2C2\n"); 673 m->iomuxc->i2c2_scl_in_select_input = IOMUXC_IS_DAISY(0x1); 674 m->iomuxc->sw_mux_ctl_pad_key_col3 = IOMUXC_MUXCTL_MODE(4) 675 | IOMUXC_MUXCTL_FORCE_INPUT; 676 m->iomuxc->i2c2_sda_in_select_input = IOMUXC_IS_DAISY(0x1); 677 m->iomuxc->sw_mux_ctl_pad_key_row3 = IOMUXC_MUXCTL_MODE(4) 678 | IOMUXC_MUXCTL_FORCE_INPUT; 679 return 0; 680 case MUX_I2C3: 681 ZF_LOGD("Muxing for I2C3\n"); 682 m->iomuxc->i2c3_scl_in_select_input = IOMUXC_IS_DAISY(0x2); 683 m->iomuxc->sw_mux_ctl_pad_gpio05 = IOMUXC_MUXCTL_MODE(6) 684 | IOMUXC_MUXCTL_FORCE_INPUT; 685 m->iomuxc->i2c3_sda_in_select_input = IOMUXC_IS_DAISY(0x2); 686 m->iomuxc->sw_mux_ctl_pad_gpio16 = IOMUXC_MUXCTL_MODE(6) 687 | IOMUXC_MUXCTL_FORCE_INPUT; 688 return 0; 689 case MUX_GPIO0_CLKO1: 690 ZF_LOGD("Muxing CLKO1 to MUX0\n"); 691 m->iomuxc->sw_mux_ctl_pad_gpio00 = IOMUXC_MUXCTL_MODE(0); 692 return 0; 693 694 case MUX_UART1: 695 ZF_LOGD("Muxing for UART1\n"); 696 m->iomuxc->sw_mux_ctl_pad_sd3_data6 = IOMUXC_MUXCTL_MODE(1); 697 m->iomuxc->uart1_uart_rx_data_select_input = IOMUXC_IS_DAISY(3); 698 return 0; 699 700 default: 701 return -1; 702 } 703} 704 705int 706imx6_mux_enable_gpio(mux_sys_t* mux_sys, int gpio_id) 707{ 708 static struct imx6_mux* m; 709 volatile uint32_t *reg; 710 assert(mux_sys); 711 m = (struct imx6_mux*)mux_sys->priv; 712 assert(m); 713 /* Surely there is a mathematical formula for finding the register to be set? */ 714 switch (gpio_id) { 715 716 case GPIOID(GPIO_BANK1, 0): 717 reg = &m->iomuxc->sw_mux_ctl_pad_gpio00; 718 break; 719 case GPIOID(GPIO_BANK1, 1): 720 reg = &m->iomuxc->sw_mux_ctl_pad_gpio01; 721 break; 722 case GPIOID(GPIO_BANK1, 2): 723 reg = &m->iomuxc->sw_mux_ctl_pad_gpio02; 724 break; 725 case GPIOID(GPIO_BANK1, 3): 726 reg = &m->iomuxc->sw_mux_ctl_pad_gpio03; 727 break; 728 case GPIOID(GPIO_BANK1, 4): 729 reg = &m->iomuxc->sw_mux_ctl_pad_gpio04; 730 break; 731 case GPIOID(GPIO_BANK1, 5): 732 reg = &m->iomuxc->sw_mux_ctl_pad_gpio05; 733 break; 734 case GPIOID(GPIO_BANK1, 6): 735 reg = &m->iomuxc->sw_mux_ctl_pad_gpio06; 736 break; 737 case GPIOID(GPIO_BANK1, 7): 738 reg = &m->iomuxc->sw_mux_ctl_pad_gpio07; 739 break; 740 case GPIOID(GPIO_BANK1, 8): 741 reg = &m->iomuxc->sw_mux_ctl_pad_gpio08; 742 break; 743 case GPIOID(GPIO_BANK1, 9): 744 reg = &m->iomuxc->sw_mux_ctl_pad_gpio09; 745 break; 746 747 case GPIOID(GPIO_BANK7, 11): 748 reg = &m->iomuxc->sw_mux_ctl_pad_gpio16; 749 break; 750 case GPIOID(GPIO_BANK7, 12): 751 reg = &m->iomuxc->sw_mux_ctl_pad_gpio17; 752 break; 753 case GPIOID(GPIO_BANK7, 13): 754 reg = &m->iomuxc->sw_mux_ctl_pad_gpio18; 755 break; 756 757 case GPIOID(GPIO_BANK4, 5): 758 reg = &m->iomuxc->sw_mux_ctl_pad_gpio19; 759 break; 760 761 case GPIOID(GPIO_BANK2, 0): 762 reg = &m->iomuxc->sw_mux_ctl_pad_nand_data00; 763 break; 764 case GPIOID(GPIO_BANK2, 1): 765 reg = &m->iomuxc->sw_mux_ctl_pad_nand_data01; 766 break; 767 case GPIOID(GPIO_BANK2, 2): 768 reg = &m->iomuxc->sw_mux_ctl_pad_nand_data02; 769 break; 770 case GPIOID(GPIO_BANK2, 3): 771 reg = &m->iomuxc->sw_mux_ctl_pad_nand_data03; 772 break; 773 case GPIOID(GPIO_BANK2, 4): 774 reg = &m->iomuxc->sw_mux_ctl_pad_nand_data04; 775 break; 776 case GPIOID(GPIO_BANK2, 5): 777 reg = &m->iomuxc->sw_mux_ctl_pad_nand_data05; 778 break; 779 case GPIOID(GPIO_BANK2, 6): 780 reg = &m->iomuxc->sw_mux_ctl_pad_nand_data06; 781 break; 782 case GPIOID(GPIO_BANK2, 7): 783 reg = &m->iomuxc->sw_mux_ctl_pad_nand_data07; 784 break; 785 786 default: 787 ZF_LOGD("Unable to mux GPIOID 0x%x\n", gpio_id); 788 return -1; 789 } 790 *reg = IOMUXC_MUXCTL_MODE(5); 791 return 0; 792} 793 794static void *imx6_mux_get_vaddr(const mux_sys_t *mux) { 795 struct imx6_mux* m; 796 if (mux == NULL || mux->priv == NULL) { 797 return NULL; 798 } 799 m = get_mux_priv(mux); 800 return (void *)m->iomuxc; 801} 802 803static int 804imx6_mux_init_common(mux_sys_t* mux) 805{ 806 set_mux_priv(mux, &_mux); 807 mux->feature_enable = &imx6_mux_feature_enable; 808 mux->get_mux_vaddr = &imx6_mux_get_vaddr; 809 return 0; 810} 811 812int 813imx6_mux_init(void* iomuxc, mux_sys_t* mux) 814{ 815 if (iomuxc != NULL) { 816 _mux.iomuxc = iomuxc; 817 } 818 return imx6_mux_init_common(mux); 819} 820 821int 822mux_sys_init(ps_io_ops_t* io_ops, UNUSED void *dependencies, mux_sys_t* mux) 823{ 824 MAP_IF_NULL(io_ops, IMX6_IOMUXC, _mux.iomuxc); 825 return imx6_mux_init_common(mux); 826} 827